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From: Manasi Navare <manasi.d.navare@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 08/18] drm/i915: Add MMIO helper for 6 ports with different offsets.
Date: Fri, 9 Jun 2017 15:49:13 -0700	[thread overview]
Message-ID: <20170609224912.GA14422@intel.com> (raw)
In-Reply-To: <1497047175-27250-8-git-send-email-rodrigo.vivi@intel.com>

On Fri, Jun 09, 2017 at 03:26:05PM -0700, Rodrigo Vivi wrote:
> Also new registers can have different mmio offsets
> per different lane per port.
> 
> v2: Use _PICK as PORT3 instead of creating a new
>     macro with if per port.
> v3: Use _PICK directly on MMIO_PORT6. While MMIO_PORT
>     isn't flexible enough let's continue with MMIO_PORT6
>     as we have MMIO_PORT3.
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9421915..52a15ce 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -62,6 +62,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
>  #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))
>  #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
> +#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))
> +#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f)			\
> +	_MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
>  #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
>  #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
>  
> -- 
> 1.9.1
> 
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  reply	other threads:[~2017-06-09 22:43 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-09 22:25 [PATCH 01/18] drm/i915/cnl: Implement .get_display_clock_speed() for CNL Rodrigo Vivi
2017-06-09 22:25 ` [PATCH 02/18] drm/i915/cnl: Implement .set_cdclk() " Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 03/18] drm/i915/cnl: Implement CNL display init/unit sequence Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 04/18] drm/i915/cnl: Allow dynamic cdclk changes on CNL Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 05/18] drm/i915/cnl: DDI - PLL mapping Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 06/18] drm/i915: Configure DPLL's for Cannonlake Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 07/18] drm/i915/cnl: Initialize PLLs Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 08/18] drm/i915: Add MMIO helper for 6 ports with different offsets Rodrigo Vivi
2017-06-09 22:49   ` Manasi Navare [this message]
2017-06-09 22:26 ` [PATCH 09/18] drm/i915/cnl: Add registers related to voltage swing sequences Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 10/18] drm/i915/cnl: Add DDI Buffer translation tables for Cannonlake Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 11/18] drm/i915/cnl: Implement voltage swing sequence Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 12/18] drm/i915/cnl: Enable loadgen_select bit for vswing sequence Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 13/18] drm/i915/DMC/CNL: Load DMC on CNL Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 14/18] drm/i915: Use HAS_CSR instead of gen number on DMC load Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 15/18] drm/i915/cnl: Fix Cannonlake scaler mode programing Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 16/18] drm/i915/cnl: Enable fifo underrun for Cannonlake Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 17/18] drm/i915/cnl: LSPCON support is gen9+ Rodrigo Vivi
2017-06-09 22:26 ` [PATCH 18/18] drm/i915/cnl: Enable wrpll computation for CNL Rodrigo Vivi
2017-06-12 23:59   ` Rodrigo Vivi
2017-06-09 23:03 ` ✓ Fi.CI.BAT: success for series starting with [01/18] drm/i915/cnl: Implement .get_display_clock_speed() " Patchwork

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