* [PATCH v2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read
@ 2017-06-22 16:43 Manasi Navare
2017-06-22 16:54 ` Ville Syrjälä
2017-06-22 18:08 ` ✓ Fi.CI.BAT: success for " Patchwork
0 siblings, 2 replies; 3+ messages in thread
From: Manasi Navare @ 2017-06-22 16:43 UTC (permalink / raw)
To: intel-gfx
When we read the VBT t11_t12 value for panel power cycle delay,
it is a zero based value so we need to 100ms to that. And then it
needs to be multiplied by 10 to store it in 100usecs unit same as
SW VBT.
v2:
* Change the VBT value instead of HW readout and pp div (Ville Syrjala)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bca4ac1..be9e17a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5234,6 +5234,11 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
intel_pps_dump_state("cur", &cur);
vbt = dev_priv->vbt.edp.pps;
+ /* T11_T12 delay is special and actually in units of 100ms, but zero
+ * based in the hw (so we need to add 100 ms). But the sw vbt
+ * table multiplies it with 1000 to make it in units of 100usec,
+ * too. */
+ vbt.t11_t12 += 100 * 10;
/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
* our hw here, which are all in 100usec. */
--
2.1.4
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^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read
2017-06-22 16:43 [PATCH v2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read Manasi Navare
@ 2017-06-22 16:54 ` Ville Syrjälä
2017-06-22 18:08 ` ✓ Fi.CI.BAT: success for " Patchwork
1 sibling, 0 replies; 3+ messages in thread
From: Ville Syrjälä @ 2017-06-22 16:54 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, Jun 22, 2017 at 09:43:00AM -0700, Manasi Navare wrote:
> When we read the VBT t11_t12 value for panel power cycle delay,
> it is a zero based value so we need to 100ms to that. And then it
> needs to be multiplied by 10 to store it in 100usecs unit same as
> SW VBT.
>
> v2:
> * Change the VBT value instead of HW readout and pp div (Ville Syrjala)
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index bca4ac1..be9e17a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5234,6 +5234,11 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
> intel_pps_dump_state("cur", &cur);
>
> vbt = dev_priv->vbt.edp.pps;
> + /* T11_T12 delay is special and actually in units of 100ms, but zero
> + * based in the hw (so we need to add 100 ms). But the sw vbt
> + * table multiplies it with 1000 to make it in units of 100usec,
> + * too. */
> + vbt.t11_t12 += 100 * 10;
If we ever encounter a two eDP panel system this would end up bumping
the delay twice for one of the panels. But if those panels wouldn't have
identical timings we'd anyway make a mess of things. Not sure how the
VBT would even present two different panels to us. So doing this here
seems OK to me.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
> * our hw here, which are all in 100usec. */
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 3+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read
2017-06-22 16:43 [PATCH v2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read Manasi Navare
2017-06-22 16:54 ` Ville Syrjälä
@ 2017-06-22 18:08 ` Patchwork
1 sibling, 0 replies; 3+ messages in thread
From: Patchwork @ 2017-06-22 18:08 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read
URL : https://patchwork.freedesktop.org/series/26238/
State : success
== Summary ==
Series 26238v1 drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read
https://patchwork.freedesktop.org/api/1.0/series/26238/revisions/1/mbox/
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
fail -> PASS (fi-snb-2600) fdo#100007
Test gem_exec_suspend:
Subgroup basic-s4-devices:
dmesg-warn -> PASS (fi-kbl-7560u) fdo#100125 +1
Test prime_vgem:
Subgroup basic-sync-default:
dmesg-warn -> PASS (fi-skl-6700hq) fdo#101515
fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#101515 https://bugs.freedesktop.org/show_bug.cgi?id=101515
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:446s
fi-bdw-gvtdvm total:279 pass:257 dwarn:8 dfail:0 fail:0 skip:14 time:426s
fi-bsw-n3050 total:279 pass:242 dwarn:1 dfail:0 fail:0 skip:36 time:531s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:505s
fi-byt-j1900 total:279 pass:253 dwarn:2 dfail:0 fail:0 skip:24 time:487s
fi-byt-n2820 total:279 pass:249 dwarn:2 dfail:0 fail:0 skip:28 time:486s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:605s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:436s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:412s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:419s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:503s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:472s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:466s
fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:579s
fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:581s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:454s
fi-skl-6700hq total:279 pass:222 dwarn:2 dfail:0 fail:30 skip:24 time:339s
fi-skl-6700k total:279 pass:257 dwarn:4 dfail:0 fail:0 skip:18 time:465s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:481s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:435s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:548s
fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:400s
cd6f0ef4478545aa014d92cabe4d794bfe54fe33 drm-tip: 2017y-06m-22d-16h-48m-46s UTC integration manifest
06fdf59 drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5029/
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2017-06-22 16:43 [PATCH v2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read Manasi Navare
2017-06-22 16:54 ` Ville Syrjälä
2017-06-22 18:08 ` ✓ Fi.CI.BAT: success for " Patchwork
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