From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 13/20] drm/i915: support 64K pages for the 48b PPGTT
Date: Tue, 27 Jun 2017 15:54:37 +0100 [thread overview]
Message-ID: <20170627145444.20491-14-matthew.auld@intel.com> (raw)
In-Reply-To: <20170627145444.20491-1-matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 26 ++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
2 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index be11c83d5c91..ee9ed2d6dd11 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -960,6 +960,7 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
struct i915_page_table *pt = pd->page_table[idx.pde];
dma_addr_t rem = iter->max - iter->dma;
unsigned int page_size;
+ bool maybe_64K = false;
gen8_pte_t encode = pte_encode;
gen8_pte_t *vaddr;
u16 index, max;
@@ -985,9 +986,17 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
index = idx.pte;
max = GEN8_PTES;
page_size = I915_GTT_PAGE_SIZE;
+
+ if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K && !idx.pte)
+ maybe_64K = true;
}
do {
+ if (maybe_64K && (index % 16 == 0) &&
+ (!IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) ||
+ rem < I915_GTT_PAGE_SIZE_64K))
+ maybe_64K = false;
+
GEM_BUG_ON(iter->sg->length < page_size);
vaddr[index++] = encode | iter->dma;
@@ -1010,6 +1019,23 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
kunmap_atomic(vaddr);
+
+ /* Is it safe to mark the 2M block as 64K? -- Either we have
+ * filled whole page-table with 64K entries, or filled part of
+ * it and have reached the end of the sg table and we have
+ * enough padding.
+ */
+ if (maybe_64K) {
+ if (index == max ||
+ (!iter->sg && IS_ALIGNED(vma->node.start +
+ vma->node.size,
+ I915_GTT_PAGE_SIZE_2M))) {
+ vaddr = kmap_atomic_px(pd);
+ vaddr[idx.pde] |= GEN8_PDE_IPS_64K;
+ kunmap_atomic(vaddr);
+ }
+ }
+
} while (iter->sg);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index aa4488637fc9..42be89d27193 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -149,6 +149,7 @@ typedef u64 gen8_ppgtt_pml4e_t;
#define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
#define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
+#define GEN8_PDE_IPS_64K BIT(11)
#define GEN8_PDE_PS_2M BIT(7)
#define GEN8_PDPE_PS_1G BIT(7)
--
2.9.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2017-06-27 14:55 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-27 14:54 [PATCH 00/20] huge gtt pages Matthew Auld
2017-06-27 14:54 ` [PATCH 01/20] mm/shmem: introduce shmem_file_setup_with_mnt Matthew Auld
2017-06-27 14:54 ` [PATCH 02/20] drm/i915: introduce simple gemfs Matthew Auld
2017-06-27 14:54 ` [PATCH 03/20] drm/i915/gemfs: enable THP Matthew Auld
2017-06-27 14:54 ` [PATCH 04/20] drm/i915: introduce page_size_mask to dev_info Matthew Auld
2017-06-27 14:54 ` [PATCH 05/20] drm/i915: introduce page_size members Matthew Auld
2017-06-29 6:36 ` Zhenyu Wang
2017-06-29 11:54 ` Matthew Auld
2017-06-29 11:59 ` Chris Wilson
2017-06-29 15:33 ` Zhenyu Wang
2017-06-27 14:54 ` [PATCH 06/20] drm/i915: introduce vm set_pages/clear_pages Matthew Auld
2017-06-27 14:54 ` [PATCH 07/20] drm/i915: align the vma start to the largest gtt page size Matthew Auld
2017-06-27 14:54 ` [PATCH 08/20] drm/i915: align 64K objects to 2M Matthew Auld
2017-06-27 14:54 ` [PATCH 09/20] drm/i915: enable IPS bit for 64K pages Matthew Auld
2017-06-27 14:54 ` [PATCH 10/20] drm/i915: disable GTT cache for 2M/1G pages Matthew Auld
2017-06-27 14:54 ` [PATCH 11/20] drm/i915: support 1G pages for the 48b PPGTT Matthew Auld
2017-06-27 14:54 ` [PATCH 12/20] drm/i915: support 2M " Matthew Auld
2017-06-27 14:54 ` Matthew Auld [this message]
2017-06-27 14:54 ` [PATCH 14/20] drm/i915: accurate page size tracking for the ppgtt Matthew Auld
2017-06-27 14:54 ` [PATCH 15/20] drm/i915/debugfs: include some gtt page size metrics Matthew Auld
2017-06-27 14:54 ` [PATCH 16/20] drm/i915/selftests: huge page tests Matthew Auld
2017-06-27 14:54 ` [PATCH 17/20] drm/i915/selftests: mix huge pages Matthew Auld
2017-06-27 14:54 ` [PATCH 18/20] drm/i915: enable platform support for 64K pages Matthew Auld
2017-06-27 14:54 ` [PATCH 19/20] drm/i915: enable platform support for 2M pages Matthew Auld
2017-06-27 14:54 ` [PATCH 20/20] drm/i915: enable platform support for 1G pages Matthew Auld
2017-06-27 15:14 ` ✓ Fi.CI.BAT: success for huge gtt pages (rev3) Patchwork
2017-06-27 17:19 ` [PATCH 00/20] huge gtt pages Chris Wilson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170627145444.20491-14-matthew.auld@intel.com \
--to=matthew.auld@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).