* [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code
@ 2017-07-06 14:40 Imre Deak
2017-07-06 14:40 ` [PATCH 01/18] drm/i915/chv: Add unique power well ID for the pipe A power well Imre Deak
` (21 more replies)
0 siblings, 22 replies; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
The programming of display power wells starting from HSW is pretty
similar on all platforms, but we have separate code for HSW/BDW and
GEN9+ platforms. This patchset unifies the two for clarity and to make
it easier to add power well support for future platforms. In essence
this means adding 3 attributes, irq_pipe_mask, has_vga and has_fuses
to the power well struct and perform the power well enable/disable
sequence steps selectively depending on these.
Imre Deak (18):
drm/i915/chv: Add unique power well ID for the pipe A power well
drm/i915: Unify power well ID enums
drm/i915: Assign everywhere the always-on power well ID
drm/i915/gen2: Add an ID for the display pipes power well
drm/i915/hsw,bdw: Add an ID for the global display power well
drm/i915: Check for duplicated power well IDs
drm/i915/bxt,glk: Give a proper name to the power well struct phy
field
drm/i915/gen9+: Remove redundant power well state assert during
enabling
drm/i915/gen9+: Remove redundant state check during power well
toggling
drm/i915/hsw,bdw: Remove redundant state check during power well
toggling
drm/i915/hsw,bdw: Split power well set to enable/disable helpers
drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros
drm/i915/hsw,bdw: Add irq_pipe_mask, has_vga power well attributes
drm/i915/hsw,bdw: Wait for the power well disabled state
drm/i915/hsw+: Add has_fuses power well attribute
drm/i915/gen9+: Unify the HSW/BDW and GEN9+ power well helpers
drm/i915: Move hsw_power_well_enable() next to the rest of HSW helpers
drm/i915: Gather all the power well->domain mappings to one place
drivers/gpu/drm/i915/gvt/display.c | 6 +-
drivers/gpu/drm/i915/gvt/handlers.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 15 +-
drivers/gpu/drm/i915/i915_reg.h | 69 ++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 886 ++++++++++++++------------------
5 files changed, 450 insertions(+), 534 deletions(-)
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 01/18] drm/i915/chv: Add unique power well ID for the pipe A power well
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-11 16:31 ` Rodrigo Vivi
2017-07-06 14:40 ` [PATCH 02/18] drm/i915: Unify power well ID enums Imre Deak
` (20 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
The power well IDs are used for lookup, so they must be unique on a
given platform; ensure this on CHV. This didn't cause an actual problem
since we didn't need to look up power wells which happened to share an
ID.
Mark this new power well as custom, since its programming pattern
doesn't follow that of the rest of VLV/CHV power wells.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 10 +++++-----
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64cc674..3f7beff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1077,6 +1077,8 @@ enum punit_power_well {
PUNIT_POWER_WELL_DPIO_RX0 = 10,
PUNIT_POWER_WELL_DPIO_RX1 = 11,
PUNIT_POWER_WELL_DPIO_CMN_D = 12,
+ /* - custom power well */
+ CHV_DISP_PW_PIPE_A, /* 13 */
/* Not actual bit groups. Used as IDs for lookup_power_well() */
PUNIT_POWER_WELL_ALWAYS_ON,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5eb9c5e..5f5dee4 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1672,7 +1672,7 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum pipe pipe = power_well->id;
+ enum pipe pipe = PIPE_A;
bool enabled;
u32 state, ctrl;
@@ -1702,7 +1702,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well,
bool enable)
{
- enum pipe pipe = power_well->id;
+ enum pipe pipe = PIPE_A;
u32 state;
u32 ctrl;
@@ -1735,7 +1735,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- WARN_ON_ONCE(power_well->id != PIPE_A);
+ WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A);
chv_set_pipe_power_well(dev_priv, power_well, true);
@@ -1745,7 +1745,7 @@ static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- WARN_ON_ONCE(power_well->id != PIPE_A);
+ WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A);
vlv_display_power_well_deinit(dev_priv);
@@ -2184,7 +2184,7 @@ static struct i915_power_well chv_power_wells[] = {
* required for any pipe to work.
*/
.domains = CHV_DISPLAY_POWER_DOMAINS,
- .id = PIPE_A,
+ .id = CHV_DISP_PW_PIPE_A,
.ops = &chv_pipe_power_well_ops,
},
{
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 02/18] drm/i915: Unify power well ID enums
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
2017-07-06 14:40 ` [PATCH 01/18] drm/i915/chv: Add unique power well ID for the pipe A power well Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-11 16:43 ` Rodrigo Vivi
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
2017-07-06 14:40 ` [PATCH 03/18] drm/i915: Assign everywhere the always-on power well ID Imre Deak
` (19 subsequent siblings)
21 siblings, 2 replies; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
Atm, the power well IDs are defined in separate platform specific enums,
which isn't ideal for the following reasons:
- the IDs are used by helpers like lookup_power_well() in a platform
independent way
- the always-on power well is used by multiple platforms and so needs
now separate IDs, although these IDs refer to the same thing
To make things more consistent use a single enum instead of the two
separate ones, listing the IDs per platform (or set of very similar
platforms like all GEN9/10). Replace the separate always-on power
well IDs with a single ID.
While at it also add a note clarifying the distinction between regular
power wells that follow a common programming pattern and custom ones
that are programmed in some other way. The IDs for regular power wells
need to stay fixed, since they also define the request and state HW flag
positions in their corresponding power well control register(s).
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 41 ++++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_runtime_pm.c | 29 ++++++++++++-----------
3 files changed, 44 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 81cd21e..c9b98ed 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1382,7 +1382,7 @@ struct i915_power_well {
bool hw_enabled;
u64 domains;
/* unique identifier for this power well */
- unsigned long id;
+ enum i915_power_well_id id;
/*
* Arbitraty data associated with this power well. Platform and power
* well specific.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f7beff..e4135bd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1063,9 +1063,19 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
-/* See the PUNIT HAS v0.8 for the below bits */
-enum punit_power_well {
- /* These numbers are fixed and must match the position of the pw bits */
+/**
+ * i915_power_well_id:
+ *
+ * Platform specific IDs used to look up power wells and - except for custom
+ * power wells - to define request/status register flag bit positions. As such
+ * the set of IDs on a given platform must be unique and except for custom
+ * power wells their value must stay fixed.
+ */
+enum i915_power_well_id {
+ /*
+ * VLV/CHV
+ * - PUNIT_REG_PWRGT_CTRL, PUNIT_REG_PWRGT_STATUS (PUNIT HAS v0.8)
+ */
PUNIT_POWER_WELL_RENDER = 0,
PUNIT_POWER_WELL_MEDIA = 1,
PUNIT_POWER_WELL_DISP2D = 3,
@@ -1080,13 +1090,11 @@ enum punit_power_well {
/* - custom power well */
CHV_DISP_PW_PIPE_A, /* 13 */
- /* Not actual bit groups. Used as IDs for lookup_power_well() */
- PUNIT_POWER_WELL_ALWAYS_ON,
-};
-
-enum skl_disp_power_wells {
- /* These numbers are fixed and must match the position of the pw bits */
- SKL_DISP_PW_MISC_IO,
+ /*
+ * GEN9+
+ * - HSW_PWR_WELL_DRIVER
+ */
+ SKL_DISP_PW_MISC_IO = 0,
SKL_DISP_PW_DDI_A_E,
GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
@@ -1105,13 +1113,18 @@ enum skl_disp_power_wells {
SKL_DISP_PW_1 = 14,
SKL_DISP_PW_2,
- /* Not actual bit groups. Used as IDs for lookup_power_well() */
- SKL_DISP_PW_ALWAYS_ON,
+ /* - custom power wells */
SKL_DISP_PW_DC_OFF,
-
BXT_DPIO_CMN_A,
BXT_DPIO_CMN_BC,
- GLK_DPIO_CMN_C,
+ GLK_DPIO_CMN_C, /* 19 */
+
+ /*
+ * Multiple platforms.
+ * Must start following the highest ID of any platform.
+ * - custom power wells
+ */
+ I915_DISP_PW_ALWAYS_ON = 20,
};
#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5f5dee4..ad314c1 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -50,10 +50,11 @@
*/
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
- int power_well_id);
+ enum i915_power_well_id power_well_id);
static struct i915_power_well *
-lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id);
+lookup_power_well(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id);
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain)
@@ -344,7 +345,7 @@ static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- int id = power_well->id;
+ enum i915_power_well_id id = power_well->id;
/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
WARN_ON(intel_wait_for_register(dev_priv,
@@ -354,7 +355,8 @@ static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
1));
}
-static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, int id)
+static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id id)
{
u32 req_mask = SKL_POWER_WELL_REQ(id);
u32 ret;
@@ -370,7 +372,7 @@ static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, int id)
static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- int id = power_well->id;
+ enum i915_power_well_id id = power_well->id;
bool disabled;
u32 reqs;
@@ -837,7 +839,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
case CNL_DISP_PW_AUX_D:
break;
default:
- WARN(1, "Unknown power well %lu\n", power_well->id);
+ WARN(1, "Unknown power well %u\n", power_well->id);
return;
}
@@ -1089,7 +1091,7 @@ static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
static void vlv_set_power_well(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well, bool enable)
{
- enum punit_power_well power_well_id = power_well->id;
+ enum i915_power_well_id power_well_id = power_well->id;
u32 mask;
u32 state;
u32 ctrl;
@@ -1137,7 +1139,7 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- int power_well_id = power_well->id;
+ enum i915_power_well_id power_well_id = power_well->id;
bool enabled = false;
u32 mask;
u32 state;
@@ -1324,8 +1326,9 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
-static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
- int power_well_id)
+static struct i915_power_well *
+lookup_power_well(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
int i;
@@ -2117,7 +2120,7 @@ static struct i915_power_well vlv_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = PUNIT_POWER_WELL_ALWAYS_ON,
+ .id = I915_DISP_PW_ALWAYS_ON,
},
{
.name = "display",
@@ -2202,7 +2205,7 @@ static struct i915_power_well chv_power_wells[] = {
};
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
- int power_well_id)
+ enum i915_power_well_id power_well_id)
{
struct i915_power_well *power_well;
bool ret;
@@ -2219,7 +2222,7 @@ static struct i915_power_well skl_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = SKL_DISP_PW_ALWAYS_ON,
+ .id = I915_DISP_PW_ALWAYS_ON,
},
{
.name = "power well 1",
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 03/18] drm/i915: Assign everywhere the always-on power well ID
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
2017-07-06 14:40 ` [PATCH 01/18] drm/i915/chv: Add unique power well ID for the pipe A power well Imre Deak
2017-07-06 14:40 ` [PATCH 02/18] drm/i915: Unify power well ID enums Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-11 16:45 ` Rodrigo Vivi
2017-07-06 14:40 ` [PATCH 04/18] drm/i915/gen2: Add an ID for the display pipes power well Imre Deak
` (18 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
Power well IDs are used for lookup so they must be unique. To ensure
this assign the always-on power well ID everywhere where it's missing.
This didn't cause a problem so far, since we didn't need to look up
power wells that happened to share their IDs.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index ad314c1..9601b62 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2013,6 +2013,7 @@ static struct i915_power_well i9xx_always_on_power_well[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
+ .id = I915_DISP_PW_ALWAYS_ON,
},
};
@@ -2029,6 +2030,7 @@ static struct i915_power_well i830_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
+ .id = I915_DISP_PW_ALWAYS_ON,
},
{
.name = "pipes",
@@ -2071,6 +2073,7 @@ static struct i915_power_well hsw_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
+ .id = I915_DISP_PW_ALWAYS_ON,
},
{
.name = "display",
@@ -2085,6 +2088,7 @@ static struct i915_power_well bdw_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
+ .id = I915_DISP_PW_ALWAYS_ON,
},
{
.name = "display",
@@ -2178,6 +2182,7 @@ static struct i915_power_well chv_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
+ .id = I915_DISP_PW_ALWAYS_ON,
},
{
.name = "display",
@@ -2282,6 +2287,7 @@ static struct i915_power_well bxt_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
+ .id = I915_DISP_PW_ALWAYS_ON,
},
{
.name = "power well 1",
@@ -2323,6 +2329,7 @@ static struct i915_power_well glk_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
+ .id = I915_DISP_PW_ALWAYS_ON,
},
{
.name = "power well 1",
@@ -2408,6 +2415,7 @@ static struct i915_power_well cnl_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
+ .id = I915_DISP_PW_ALWAYS_ON,
},
{
.name = "power well 1",
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 04/18] drm/i915/gen2: Add an ID for the display pipes power well
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (2 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 03/18] drm/i915: Assign everywhere the always-on power well ID Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-11 16:50 ` Rodrigo Vivi
` (2 more replies)
2017-07-06 14:40 ` [PATCH 05/18] drm/i915/hsw, bdw: Add an ID for the global display " Imre Deak
` (17 subsequent siblings)
21 siblings, 3 replies; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
Make the GEN2 power well ID assignment explicit for consistency.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e4135bd..ce90847 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1073,6 +1073,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
*/
enum i915_power_well_id {
/*
+ * GEN2
+ * - custom power well
+ */
+ I830_DISP_PW_PIPES = 0,
+
+ /*
* VLV/CHV
* - PUNIT_REG_PWRGT_CTRL, PUNIT_REG_PWRGT_STATUS (PUNIT HAS v0.8)
*/
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 9601b62..4a9d955 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2036,6 +2036,7 @@ static struct i915_power_well i830_power_wells[] = {
.name = "pipes",
.domains = I830_PIPES_POWER_DOMAINS,
.ops = &i830_pipes_power_well_ops,
+ .id = I830_DISP_PW_PIPES,
},
};
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 05/18] drm/i915/hsw, bdw: Add an ID for the global display power well
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (3 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 04/18] drm/i915/gen2: Add an ID for the display pipes power well Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-11 17:08 ` Rodrigo Vivi
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
2017-07-06 14:40 ` [PATCH 06/18] drm/i915: Check for duplicated power well IDs Imre Deak
` (16 subsequent siblings)
21 siblings, 2 replies; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
Add an ID for the HSW/BDW global display power well for consistency. The
ID is selected so that it can be used to get at the HW request and
status flags with the corresponding GEN9+ macros. Unifying the HSW/BDW
and GEN9+ versions of these macros and the power well ops using them
will be done in follow-up patches.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ce90847..f798023 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1097,6 +1097,12 @@ enum i915_power_well_id {
CHV_DISP_PW_PIPE_A, /* 13 */
/*
+ * HSW/BDW
+ * - HSW_PWR_WELL_DRIVER
+ */
+ HSW_DISP_PW_GLOBAL = 15,
+
+ /*
* GEN9+
* - HSW_PWR_WELL_DRIVER
*/
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4a9d955..27c69f9 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2080,6 +2080,7 @@ static struct i915_power_well hsw_power_wells[] = {
.name = "display",
.domains = HSW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .id = HSW_DISP_PW_GLOBAL,
},
};
@@ -2095,6 +2096,7 @@ static struct i915_power_well bdw_power_wells[] = {
.name = "display",
.domains = BDW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .id = HSW_DISP_PW_GLOBAL,
},
};
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 06/18] drm/i915: Check for duplicated power well IDs
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (4 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 05/18] drm/i915/hsw, bdw: Add an ID for the global display " Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-07 14:39 ` [PATCH v2 " Imre Deak
2017-07-11 20:42 ` [PATCH v3 " Imre Deak
2017-07-06 14:40 ` [PATCH 07/18] drm/i915/bxt, glk: Give a proper name to the power well struct phy field Imre Deak
` (15 subsequent siblings)
21 siblings, 2 replies; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
Check that all the power well IDs are unique on the given platform.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 27c69f9..f0bdb63 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2563,6 +2563,8 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
int intel_power_domains_init(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ u64 power_well_ids;
+ int i;
i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
i915.disable_power_well);
@@ -2599,6 +2601,15 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
set_power_wells(power_domains, i9xx_always_on_power_well);
}
+ power_well_ids = 0;
+ for (i = 0; i < power_domains->power_well_count; i++) {
+ enum i915_power_well_id id = power_domains->power_wells[i].id;
+
+ WARN_ON(id >= sizeof(power_well_ids) * 8);
+ WARN_ON(power_well_ids & BIT(id));
+ power_well_ids |= BIT(id);
+ }
+
return 0;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 07/18] drm/i915/bxt, glk: Give a proper name to the power well struct phy field
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (5 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 06/18] drm/i915: Check for duplicated power well IDs Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-20 13:11 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 08/18] drm/i915/gen9+: Remove redundant power well state assert during enabling Imre Deak
` (14 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
Follow-up patches will add new fields to the i915_power_well struct that
are specific to the hsw_power_well_ops helpers. Prepare for this by
changing the generic 'data' field to a union of platform specific
structs.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 +++++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++++++++++-----------
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9b98ed..b27f2fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1387,7 +1387,11 @@ struct i915_power_well {
* Arbitraty data associated with this power well. Platform and power
* well specific.
*/
- unsigned long data;
+ union {
+ struct {
+ enum dpio_phy phy;
+ } bxt;
+ };
const struct i915_power_well_ops *ops;
};
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index f0bdb63..0f3eb42 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -963,19 +963,19 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv,
static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- bxt_ddi_phy_init(dev_priv, power_well->data);
+ bxt_ddi_phy_init(dev_priv, power_well->bxt.phy);
}
static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- bxt_ddi_phy_uninit(dev_priv, power_well->data);
+ bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy);
}
static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- return bxt_ddi_phy_is_enabled(dev_priv, power_well->data);
+ return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy);
}
static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
@@ -984,16 +984,16 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
if (power_well->count > 0)
- bxt_ddi_phy_verify_state(dev_priv, power_well->data);
+ bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
if (power_well->count > 0)
- bxt_ddi_phy_verify_state(dev_priv, power_well->data);
+ bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
if (IS_GEMINILAKE(dev_priv)) {
power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C);
if (power_well->count > 0)
- bxt_ddi_phy_verify_state(dev_priv, power_well->data);
+ bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
}
}
@@ -2315,14 +2315,14 @@ static struct i915_power_well bxt_power_wells[] = {
.domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = BXT_DPIO_CMN_A,
- .data = DPIO_PHY1,
+ .bxt.phy = DPIO_PHY1,
},
{
.name = "dpio-common-bc",
.domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = BXT_DPIO_CMN_BC,
- .data = DPIO_PHY0,
+ .bxt.phy = DPIO_PHY0,
},
};
@@ -2358,21 +2358,21 @@ static struct i915_power_well glk_power_wells[] = {
.domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = BXT_DPIO_CMN_A,
- .data = DPIO_PHY1,
+ .bxt.phy = DPIO_PHY1,
},
{
.name = "dpio-common-b",
.domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = BXT_DPIO_CMN_BC,
- .data = DPIO_PHY0,
+ .bxt.phy = DPIO_PHY0,
},
{
.name = "dpio-common-c",
.domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = GLK_DPIO_CMN_C,
- .data = DPIO_PHY2,
+ .bxt.phy = DPIO_PHY2,
},
{
.name = "AUX A",
--
2.7.4
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 08/18] drm/i915/gen9+: Remove redundant power well state assert during enabling
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (6 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 07/18] drm/i915/bxt, glk: Give a proper name to the power well struct phy field Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-21 10:53 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 09/18] drm/i915/gen9+: Remove redundant state check during power well toggling Imre Deak
` (13 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
We check already for power wells that are unexpectedly on (or forced on)
during power well disabling. Those checks also account for other
power well requesters like KVMR or DEBUG. As such this check is
redundant, let's remove it to simplify things.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0f3eb42..85c592d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -852,13 +852,8 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
skl_power_well_pre_disable(dev_priv, power_well);
if (enable) {
- if (!enable_requested) {
- WARN((tmp & state_mask) &&
- !I915_READ(HSW_PWR_WELL_BIOS),
- "Invalid for power well status to be enabled, unless done by the BIOS, \
- when request is to disable!\n");
+ if (!enable_requested)
I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
- }
if (!is_enabled) {
DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 09/18] drm/i915/gen9+: Remove redundant state check during power well toggling
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (7 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 08/18] drm/i915/gen9+: Remove redundant power well state assert during enabling Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-21 11:14 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 10/18] drm/i915/hsw, bdw: " Imre Deak
` (12 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
Atm we enable/disable a power well only if it wasn't already
enabled/disabled respectively. The only reason for this I can think of
is to save the extra MMIO writes. Since the HW state matches the power
well's usage counter most of the time the overhead due to these MMIOs is
insignificant. Let's simplify the code by making the writes
unconditional.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 25 +++++++++----------------
1 file changed, 9 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 85c592d..28d2ea9 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -806,7 +806,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
{
uint32_t tmp, fuse_status;
uint32_t req_mask, state_mask;
- bool is_enabled, enable_requested, check_fuse_status = false;
+ bool check_fuse_status = false;
tmp = I915_READ(HSW_PWR_WELL_DRIVER);
fuse_status = I915_READ(SKL_FUSE_STATUS);
@@ -844,29 +844,22 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
}
req_mask = SKL_POWER_WELL_REQ(power_well->id);
- enable_requested = tmp & req_mask;
state_mask = SKL_POWER_WELL_STATE(power_well->id);
- is_enabled = tmp & state_mask;
- if (!enable && enable_requested)
+ if (!enable)
skl_power_well_pre_disable(dev_priv, power_well);
if (enable) {
- if (!enable_requested)
- I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
+ I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
- if (!is_enabled) {
- DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
- check_fuse_status = true;
- }
+ DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
+ check_fuse_status = true;
gen9_wait_for_power_well_enable(dev_priv, power_well);
} else {
- if (enable_requested) {
- I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
- POSTING_READ(HSW_PWR_WELL_DRIVER);
- DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
- }
+ I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
+ POSTING_READ(HSW_PWR_WELL_DRIVER);
+ DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
gen9_wait_for_power_well_disable(dev_priv, power_well);
}
@@ -889,7 +882,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
}
}
- if (enable && !is_enabled)
+ if (enable)
skl_power_well_post_enable(dev_priv, power_well);
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 10/18] drm/i915/hsw, bdw: Remove redundant state check during power well toggling
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (8 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 09/18] drm/i915/gen9+: Remove redundant state check during power well toggling Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-21 11:39 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 11/18] drm/i915/hsw, bdw: Split power well set to enable/disable helpers Imre Deak
` (11 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
Similarly to the GEN9 power well toggling, saving an occasional extra
MMIO write is not worth the code complexity, let's simplify things.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 36 ++++++++++++---------------------
1 file changed, 13 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 28d2ea9..00e97ee 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -399,36 +399,26 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
static void hsw_set_power_well(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well, bool enable)
{
- bool is_enabled, enable_requested;
uint32_t tmp;
tmp = I915_READ(HSW_PWR_WELL_DRIVER);
- is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
- enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
if (enable) {
- if (!enable_requested)
- I915_WRITE(HSW_PWR_WELL_DRIVER,
- HSW_PWR_WELL_ENABLE_REQUEST);
-
- if (!is_enabled) {
- DRM_DEBUG_KMS("Enabling power well\n");
- if (intel_wait_for_register(dev_priv,
- HSW_PWR_WELL_DRIVER,
- HSW_PWR_WELL_STATE_ENABLED,
- HSW_PWR_WELL_STATE_ENABLED,
- 20))
- DRM_ERROR("Timeout enabling power well\n");
- hsw_power_well_post_enable(dev_priv);
- }
+ I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE_REQUEST);
+ DRM_DEBUG_KMS("Enabling power well\n");
+ if (intel_wait_for_register(dev_priv,
+ HSW_PWR_WELL_DRIVER,
+ HSW_PWR_WELL_STATE_ENABLED,
+ HSW_PWR_WELL_STATE_ENABLED,
+ 20))
+ DRM_ERROR("Timeout enabling power well\n");
+ hsw_power_well_post_enable(dev_priv);
} else {
- if (enable_requested) {
- hsw_power_well_pre_disable(dev_priv);
- I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
- POSTING_READ(HSW_PWR_WELL_DRIVER);
- DRM_DEBUG_KMS("Requesting to disable the power well\n");
- }
+ hsw_power_well_pre_disable(dev_priv);
+ I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
+ POSTING_READ(HSW_PWR_WELL_DRIVER);
+ DRM_DEBUG_KMS("Requesting to disable the power well\n");
}
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 11/18] drm/i915/hsw, bdw: Split power well set to enable/disable helpers
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (9 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 10/18] drm/i915/hsw, bdw: " Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-21 11:51 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 12/18] drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros Imre Deak
` (10 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
We can reduce the code indentation by splitting the set helper to
separate enable/disable helpers. This also allows us to unify the
HSW/BDW and GEN9+ power well ops in follow-up patches, which introduces
some differences between the enable and disable helpers.
While at it also remove the redundant enable/disable debug messages,
the same info is printed already elsewhere.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 50 +++++++++++----------------------
1 file changed, 17 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 00e97ee..d0934bd 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -396,30 +396,26 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
!!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
}
-static void hsw_set_power_well(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well, bool enable)
+static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
{
- uint32_t tmp;
+ I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE_REQUEST);
- tmp = I915_READ(HSW_PWR_WELL_DRIVER);
+ if (intel_wait_for_register(dev_priv,
+ HSW_PWR_WELL_DRIVER,
+ HSW_PWR_WELL_STATE_ENABLED,
+ HSW_PWR_WELL_STATE_ENABLED,
+ 20))
+ DRM_ERROR("Timeout enabling power well\n");
+ hsw_power_well_post_enable(dev_priv);
+}
- if (enable) {
- I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE_REQUEST);
-
- DRM_DEBUG_KMS("Enabling power well\n");
- if (intel_wait_for_register(dev_priv,
- HSW_PWR_WELL_DRIVER,
- HSW_PWR_WELL_STATE_ENABLED,
- HSW_PWR_WELL_STATE_ENABLED,
- 20))
- DRM_ERROR("Timeout enabling power well\n");
- hsw_power_well_post_enable(dev_priv);
- } else {
- hsw_power_well_pre_disable(dev_priv);
- I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
- POSTING_READ(HSW_PWR_WELL_DRIVER);
- DRM_DEBUG_KMS("Requesting to disable the power well\n");
- }
+static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ hsw_power_well_pre_disable(dev_priv);
+ I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
+ POSTING_READ(HSW_PWR_WELL_DRIVER);
}
#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
@@ -889,18 +885,6 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
}
}
-static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- hsw_set_power_well(dev_priv, power_well, true);
-}
-
-static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- hsw_set_power_well(dev_priv, power_well, false);
-}
-
static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 12/18] drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (10 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 11/18] drm/i915/hsw, bdw: Split power well set to enable/disable helpers Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-21 12:39 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 13/18] drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes Imre Deak
` (9 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
Although on HSW/BDW there is only a single display global power well,
it's programmed the same way as other GEN9+ power wells. This also
means we can get at the HSW/BDW request and status flags the same way
it's done on GEN9+ by assigning the corresponding HSW/BDW power well ID.
This ID was assigned in a recent patch, so we can now switch to using
the same macros everywhere on HSW+.
Updating the HSW power well control register with RMW is not strictly
necessary, but this will allow us to use the same code for GEN9+.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/gvt/handlers.c | 8 +++--
drivers/gpu/drm/i915/i915_reg.h | 8 ++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 58 ++++++++++++++++++++-------------
3 files changed, 44 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 17febe8..aeecf315 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1222,10 +1222,12 @@ static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
{
write_vreg(vgpu, offset, p_data, bytes);
- if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST)
- vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED;
+ if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL))
+ vgpu_vreg(vgpu, offset) |=
+ HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
else
- vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED;
+ vgpu_vreg(vgpu, offset) &=
+ ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f798023..845f50c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1139,9 +1139,6 @@ enum i915_power_well_id {
I915_DISP_PW_ALWAYS_ON = 20,
};
-#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
-#define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1))
-
#define PUNIT_REG_PWRGT_CTRL 0x60
#define PUNIT_REG_PWRGT_STATUS 0x61
#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
@@ -8015,8 +8012,9 @@ enum {
#define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */
#define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */
#define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */
-#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
-#define HSW_PWR_WELL_STATE_ENABLED (1<<30)
+#define _HSW_PW_SHIFT(pw) ((pw) * 2)
+#define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1))
+#define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw))
#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index d0934bd..e18c38e6 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -177,8 +177,10 @@ static void intel_power_well_put(struct drm_i915_private *dev_priv,
static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- return I915_READ(HSW_PWR_WELL_DRIVER) ==
- (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
+ enum i915_power_well_id id = power_well->id;
+ u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id);
+
+ return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
}
/**
@@ -350,15 +352,15 @@ static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
WARN_ON(intel_wait_for_register(dev_priv,
HSW_PWR_WELL_DRIVER,
- SKL_POWER_WELL_STATE(id),
- SKL_POWER_WELL_STATE(id),
+ HSW_PWR_WELL_CTL_STATE(id),
+ HSW_PWR_WELL_CTL_STATE(id),
1));
}
static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv,
enum i915_power_well_id id)
{
- u32 req_mask = SKL_POWER_WELL_REQ(id);
+ u32 req_mask = HSW_PWR_WELL_CTL_REQ(id);
u32 ret;
ret = I915_READ(HSW_PWR_WELL_BIOS) & req_mask ? 1 : 0;
@@ -386,7 +388,7 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
* diagnostic message.
*/
wait_for((disabled = !(I915_READ(HSW_PWR_WELL_DRIVER) &
- SKL_POWER_WELL_STATE(id))) ||
+ HSW_PWR_WELL_CTL_STATE(id))) ||
(reqs = gen9_power_well_requesters(dev_priv, id)), 1);
if (disabled)
return;
@@ -399,12 +401,16 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE_REQUEST);
+ enum i915_power_well_id id = power_well->id;
+ u32 val;
+
+ val = I915_READ(HSW_PWR_WELL_DRIVER);
+ I915_WRITE(HSW_PWR_WELL_DRIVER, val | HSW_PWR_WELL_CTL_REQ(id));
if (intel_wait_for_register(dev_priv,
HSW_PWR_WELL_DRIVER,
- HSW_PWR_WELL_STATE_ENABLED,
- HSW_PWR_WELL_STATE_ENABLED,
+ HSW_PWR_WELL_CTL_STATE(id),
+ HSW_PWR_WELL_CTL_STATE(id),
20))
DRM_ERROR("Timeout enabling power well\n");
hsw_power_well_post_enable(dev_priv);
@@ -413,8 +419,12 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
+ enum i915_power_well_id id = power_well->id;
+ u32 val;
+
hsw_power_well_pre_disable(dev_priv);
- I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
+ val = I915_READ(HSW_PWR_WELL_DRIVER);
+ I915_WRITE(HSW_PWR_WELL_DRIVER, val & ~HSW_PWR_WELL_CTL_REQ(id));
POSTING_READ(HSW_PWR_WELL_DRIVER);
}
@@ -591,7 +601,7 @@ static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
"DC5 still not disabled to enable DC9.\n");
WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER) &
- SKL_POWER_WELL_REQ(SKL_DISP_PW_2),
+ HSW_PWR_WELL_CTL_REQ(SKL_DISP_PW_2),
"Power well 2 on.\n");
WARN_ONCE(intel_irqs_enabled(dev_priv),
"Interrupts not disabled yet.\n");
@@ -829,8 +839,8 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
return;
}
- req_mask = SKL_POWER_WELL_REQ(power_well->id);
- state_mask = SKL_POWER_WELL_STATE(power_well->id);
+ req_mask = HSW_PWR_WELL_CTL_REQ(power_well->id);
+ state_mask = HSW_PWR_WELL_CTL_STATE(power_well->id);
if (!enable)
skl_power_well_pre_disable(dev_priv, power_well);
@@ -875,21 +885,25 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
+ enum i915_power_well_id id = power_well->id;
+ u32 mask = HSW_PWR_WELL_CTL_REQ(id);
+ u32 bios_req = I915_READ(HSW_PWR_WELL_BIOS);
+
/* Take over the request bit if set by BIOS. */
- if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) {
- if (!(I915_READ(HSW_PWR_WELL_DRIVER) &
- HSW_PWR_WELL_ENABLE_REQUEST))
- I915_WRITE(HSW_PWR_WELL_DRIVER,
- HSW_PWR_WELL_ENABLE_REQUEST);
- I915_WRITE(HSW_PWR_WELL_BIOS, 0);
+ if (bios_req & mask) {
+ u32 drv_req = I915_READ(HSW_PWR_WELL_DRIVER);
+
+ if (!(drv_req & mask))
+ I915_WRITE(HSW_PWR_WELL_DRIVER, drv_req | mask);
+ I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask);
}
}
static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- uint32_t mask = SKL_POWER_WELL_REQ(power_well->id) |
- SKL_POWER_WELL_STATE(power_well->id);
+ uint32_t mask = HSW_PWR_WELL_CTL_REQ(power_well->id) |
+ HSW_PWR_WELL_CTL_STATE(power_well->id);
return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
}
@@ -897,7 +911,7 @@ static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- uint32_t mask = SKL_POWER_WELL_REQ(power_well->id);
+ uint32_t mask = HSW_PWR_WELL_CTL_REQ(power_well->id);
uint32_t bios_req = I915_READ(HSW_PWR_WELL_BIOS);
/* Take over the request bit if set by BIOS. */
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 13/18] drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (11 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 12/18] drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-11 17:02 ` Ville Syrjälä
` (2 more replies)
2017-07-06 14:40 ` [PATCH 14/18] drm/i915/hsw, bdw: Wait for the power well disabled state Imre Deak
` (8 subsequent siblings)
21 siblings, 3 replies; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
The pattern of a power well backing a set of pipe IRQ or VGA
functionality applies to all HSW+ platforms. Using power well attributes
instead of platform checks to decide whether to init/reset pipe IRQs and
VGA correspondingly is cleaner and it allows us to unify the HSW/BDW and
GEN9+ power well code in follow-up patches.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 34 ++++++++++++++++++++-------------
2 files changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b27f2fc..dc5ca5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1391,6 +1391,12 @@ struct i915_power_well {
struct {
enum dpio_phy phy;
} bxt;
+ struct {
+ /* Mask of pipes whose IRQ logic is backed by the pw */
+ u32 irq_pipe_mask;
+ /* The pw is backing the VGA functionality */
+ bool has_vga:1;
+ } hsw;
};
const struct i915_power_well_ops *ops;
};
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index e18c38e6..ab2e0ee 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -281,7 +281,8 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv,
* to be enabled, and it will only be disabled if none of the registers is
* requesting it to be enabled.
*/
-static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
+static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
+ u32 irq_pipe_mask, bool has_vga)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
@@ -295,20 +296,21 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
* sure vgacon can keep working normally without triggering interrupts
* and error messages.
*/
- vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
- outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
- vga_put(pdev, VGA_RSRC_LEGACY_IO);
+ if (has_vga) {
+ vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
+ outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
+ vga_put(pdev, VGA_RSRC_LEGACY_IO);
+ }
- if (IS_BROADWELL(dev_priv))
- gen8_irq_power_well_post_enable(dev_priv,
- 1 << PIPE_C | 1 << PIPE_B);
+ if (irq_pipe_mask)
+ gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
}
-static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
+static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
+ u32 irq_pipe_mask)
{
- if (IS_BROADWELL(dev_priv))
- gen8_irq_power_well_pre_disable(dev_priv,
- 1 << PIPE_C | 1 << PIPE_B);
+ if (irq_pipe_mask)
+ gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
}
static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -413,7 +415,9 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
HSW_PWR_WELL_CTL_STATE(id),
20))
DRM_ERROR("Timeout enabling power well\n");
- hsw_power_well_post_enable(dev_priv);
+
+ hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
+ power_well->hsw.has_vga);
}
static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
@@ -422,7 +426,8 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
enum i915_power_well_id id = power_well->id;
u32 val;
- hsw_power_well_pre_disable(dev_priv);
+ hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask);
+
val = I915_READ(HSW_PWR_WELL_DRIVER);
I915_WRITE(HSW_PWR_WELL_DRIVER, val & ~HSW_PWR_WELL_CTL_REQ(id));
POSTING_READ(HSW_PWR_WELL_DRIVER);
@@ -2057,6 +2062,7 @@ static struct i915_power_well hsw_power_wells[] = {
.domains = HSW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
+ .hsw.has_vga = true,
},
};
@@ -2073,6 +2079,8 @@ static struct i915_power_well bdw_power_wells[] = {
.domains = BDW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
},
};
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 14/18] drm/i915/hsw, bdw: Wait for the power well disabled state
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (12 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 13/18] drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-21 13:00 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 15/18] drm/i915/hsw+: Add has_fuses power well attribute Imre Deak
` (7 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
Similarly to GEN9+ waiting for the power well disabled state is a safer
option and also provides diagnostic info if the disabling didn't succeed
or the power well was forced on by an external requester. While at it
also use the existing GEN9+ helper to wait for the enabled state.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 28 +++++++++++-----------------
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index ab2e0ee..14d4ff4 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -346,8 +346,8 @@ static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
1 << PIPE_C | 1 << PIPE_B);
}
-static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
+static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
{
enum i915_power_well_id id = power_well->id;
@@ -359,8 +359,8 @@ static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
1));
}
-static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv,
- enum i915_power_well_id id)
+static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id id)
{
u32 req_mask = HSW_PWR_WELL_CTL_REQ(id);
u32 ret;
@@ -373,8 +373,8 @@ static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv,
return ret;
}
-static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
+static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
{
enum i915_power_well_id id = power_well->id;
bool disabled;
@@ -391,7 +391,7 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
*/
wait_for((disabled = !(I915_READ(HSW_PWR_WELL_DRIVER) &
HSW_PWR_WELL_CTL_STATE(id))) ||
- (reqs = gen9_power_well_requesters(dev_priv, id)), 1);
+ (reqs = hsw_power_well_requesters(dev_priv, id)), 1);
if (disabled)
return;
@@ -408,13 +408,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
val = I915_READ(HSW_PWR_WELL_DRIVER);
I915_WRITE(HSW_PWR_WELL_DRIVER, val | HSW_PWR_WELL_CTL_REQ(id));
-
- if (intel_wait_for_register(dev_priv,
- HSW_PWR_WELL_DRIVER,
- HSW_PWR_WELL_CTL_STATE(id),
- HSW_PWR_WELL_CTL_STATE(id),
- 20))
- DRM_ERROR("Timeout enabling power well\n");
+ hsw_wait_for_power_well_enable(dev_priv, power_well);
hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
power_well->hsw.has_vga);
@@ -430,7 +424,7 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
val = I915_READ(HSW_PWR_WELL_DRIVER);
I915_WRITE(HSW_PWR_WELL_DRIVER, val & ~HSW_PWR_WELL_CTL_REQ(id));
- POSTING_READ(HSW_PWR_WELL_DRIVER);
+ hsw_wait_for_power_well_disable(dev_priv, power_well);
}
#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
@@ -856,13 +850,13 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
check_fuse_status = true;
- gen9_wait_for_power_well_enable(dev_priv, power_well);
+ hsw_wait_for_power_well_enable(dev_priv, power_well);
} else {
I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
POSTING_READ(HSW_PWR_WELL_DRIVER);
DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
- gen9_wait_for_power_well_disable(dev_priv, power_well);
+ hsw_wait_for_power_well_disable(dev_priv, power_well);
}
if (check_fuse_status) {
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 15/18] drm/i915/hsw+: Add has_fuses power well attribute
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (13 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 14/18] drm/i915/hsw, bdw: Wait for the power well disabled state Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-11 17:05 ` Ville Syrjälä
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
2017-07-06 14:40 ` [PATCH 16/18] drm/i915/gen9+: Unify the HSW/BDW and GEN9+ power well helpers Imre Deak
` (6 subsequent siblings)
21 siblings, 2 replies; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
The pattern of a power well backing a set of fuses whose initialization
we need to wait for during power well enabling is common to all GEN9+
platforms. Adding support for this to the HSW power well enable helper
allows us to use the HSW/BDW power well code for GEN9+ as well in a
follow-up patch.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/gvt/display.c | 6 +++---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
drivers/gpu/drm/i915/intel_runtime_pm.c | 34 ++++++++++++++++++++++++++-------
4 files changed, 35 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 2deb05f..13599bb 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -178,9 +178,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
SDE_PORTE_HOTPLUG_SPT);
vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=
SKL_FUSE_DOWNLOAD_STATUS |
- SKL_FUSE_PG0_DIST_STATUS |
- SKL_FUSE_PG1_DIST_STATUS |
- SKL_FUSE_PG2_DIST_STATUS;
+ SKL_FUSE_PG_DIST_STATUS(0) |
+ SKL_FUSE_PG_DIST_STATUS(1) |
+ SKL_FUSE_PG_DIST_STATUS(2);
vgpu_vreg(vgpu, LCPLL1_CTL) |=
LCPLL_PLL_ENABLE |
LCPLL_PLL_LOCK;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dc5ca5a..9e97536 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1396,6 +1396,7 @@ struct i915_power_well {
u32 irq_pipe_mask;
/* The pw is backing the VGA functionality */
bool has_vga:1;
+ bool has_fuses:1;
} hsw;
};
const struct i915_power_well_ops *ops;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 845f50c..794d65c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8023,10 +8023,10 @@ enum {
/* SKL Fuse Status */
#define SKL_FUSE_STATUS _MMIO(0x42000)
-#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
-#define SKL_FUSE_PG0_DIST_STATUS (1<<27)
-#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
-#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
+#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
+/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */
+#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + 1)
+#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 14d4ff4..c204be0 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -400,16 +400,36 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
!!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
}
+static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
+ int pg)
+{
+ /* Timeout 5us for PG#0, for other PGs 1us */
+ WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS,
+ SKL_FUSE_PG_DIST_STATUS(pg),
+ SKL_FUSE_PG_DIST_STATUS(pg), 1));
+}
+
static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
enum i915_power_well_id id = power_well->id;
+ bool wait_fuses = power_well->hsw.has_fuses;
+ int pg;
u32 val;
+ if (wait_fuses) {
+ pg = SKL_PW_TO_PG(id);
+ if (pg == 1)
+ gen9_wait_for_power_well_fuses(dev_priv, pg - 1);
+ }
+
val = I915_READ(HSW_PWR_WELL_DRIVER);
I915_WRITE(HSW_PWR_WELL_DRIVER, val | HSW_PWR_WELL_CTL_REQ(id));
hsw_wait_for_power_well_enable(dev_priv, power_well);
+ if (wait_fuses)
+ gen9_wait_for_power_well_fuses(dev_priv, pg);
+
hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
power_well->hsw.has_vga);
}
@@ -810,15 +830,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
case SKL_DISP_PW_1:
if (intel_wait_for_register(dev_priv,
SKL_FUSE_STATUS,
- SKL_FUSE_PG0_DIST_STATUS,
- SKL_FUSE_PG0_DIST_STATUS,
+ SKL_FUSE_PG_DIST_STATUS(0),
+ SKL_FUSE_PG_DIST_STATUS(0),
1)) {
DRM_ERROR("PG0 not enabled\n");
return;
}
break;
case SKL_DISP_PW_2:
- if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
+ if (!(fuse_status & SKL_FUSE_PG_DIST_STATUS(1))) {
DRM_ERROR("PG1 in disabled state\n");
return;
}
@@ -863,15 +883,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
if (power_well->id == SKL_DISP_PW_1) {
if (intel_wait_for_register(dev_priv,
SKL_FUSE_STATUS,
- SKL_FUSE_PG1_DIST_STATUS,
- SKL_FUSE_PG1_DIST_STATUS,
+ SKL_FUSE_PG_DIST_STATUS(1),
+ SKL_FUSE_PG_DIST_STATUS(1),
1))
DRM_ERROR("PG1 distributing status timeout\n");
} else if (power_well->id == SKL_DISP_PW_2) {
if (intel_wait_for_register(dev_priv,
SKL_FUSE_STATUS,
- SKL_FUSE_PG2_DIST_STATUS,
- SKL_FUSE_PG2_DIST_STATUS,
+ SKL_FUSE_PG_DIST_STATUS(2),
+ SKL_FUSE_PG_DIST_STATUS(2),
1))
DRM_ERROR("PG2 distributing status timeout\n");
}
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 16/18] drm/i915/gen9+: Unify the HSW/BDW and GEN9+ power well helpers
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (14 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 15/18] drm/i915/hsw+: Add has_fuses power well attribute Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
2017-07-06 14:40 ` [PATCH 17/18] drm/i915: Move hsw_power_well_enable() next to the rest of HSW helpers Imre Deak
` (5 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
After the previous refactorings the HSW/BDW and GEN9+ power well helpers
are practically identical, so use the HSW power well helpers for GEN9+
too. This means using the HSW power well ops instead of the SKL one and
setting the irq_pipe_mask, has_vga and has_fuses attributes as needed.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 231 ++++++--------------------------
1 file changed, 43 insertions(+), 188 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index c204be0..68b7183 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -313,38 +313,6 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
}
-static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- struct pci_dev *pdev = dev_priv->drm.pdev;
-
- /*
- * After we re-enable the power well, if we touch VGA register 0x3d5
- * we'll get unclaimed register interrupts. This stops after we write
- * anything to the VGA MSR register. The vgacon module uses this
- * register all the time, so if we unbind our driver and, as a
- * consequence, bind vgacon, we'll get stuck in an infinite loop at
- * console_unlock(). So make here we touch the VGA MSR register, making
- * sure vgacon can keep working normally without triggering interrupts
- * and error messages.
- */
- if (power_well->id == SKL_DISP_PW_2) {
- vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
- outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
- vga_put(pdev, VGA_RSRC_LEGACY_IO);
-
- gen8_irq_power_well_post_enable(dev_priv,
- 1 << PIPE_C | 1 << PIPE_B);
- }
-}
-
-static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- if (power_well->id == SKL_DISP_PW_2)
- gen8_irq_power_well_pre_disable(dev_priv,
- 1 << PIPE_C | 1 << PIPE_B);
-}
static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
@@ -816,91 +784,6 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
}
-static void skl_set_power_well(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well, bool enable)
-{
- uint32_t tmp, fuse_status;
- uint32_t req_mask, state_mask;
- bool check_fuse_status = false;
-
- tmp = I915_READ(HSW_PWR_WELL_DRIVER);
- fuse_status = I915_READ(SKL_FUSE_STATUS);
-
- switch (power_well->id) {
- case SKL_DISP_PW_1:
- if (intel_wait_for_register(dev_priv,
- SKL_FUSE_STATUS,
- SKL_FUSE_PG_DIST_STATUS(0),
- SKL_FUSE_PG_DIST_STATUS(0),
- 1)) {
- DRM_ERROR("PG0 not enabled\n");
- return;
- }
- break;
- case SKL_DISP_PW_2:
- if (!(fuse_status & SKL_FUSE_PG_DIST_STATUS(1))) {
- DRM_ERROR("PG1 in disabled state\n");
- return;
- }
- break;
- case SKL_DISP_PW_MISC_IO:
- case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A, CNL_DISP_PW_DDI_A */
- case SKL_DISP_PW_DDI_B:
- case SKL_DISP_PW_DDI_C:
- case SKL_DISP_PW_DDI_D:
- case GLK_DISP_PW_AUX_A: /* CNL_DISP_PW_AUX_A */
- case GLK_DISP_PW_AUX_B: /* CNL_DISP_PW_AUX_B */
- case GLK_DISP_PW_AUX_C: /* CNL_DISP_PW_AUX_C */
- case CNL_DISP_PW_AUX_D:
- break;
- default:
- WARN(1, "Unknown power well %u\n", power_well->id);
- return;
- }
-
- req_mask = HSW_PWR_WELL_CTL_REQ(power_well->id);
- state_mask = HSW_PWR_WELL_CTL_STATE(power_well->id);
-
- if (!enable)
- skl_power_well_pre_disable(dev_priv, power_well);
-
- if (enable) {
- I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
-
- DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
- check_fuse_status = true;
-
- hsw_wait_for_power_well_enable(dev_priv, power_well);
- } else {
- I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
- POSTING_READ(HSW_PWR_WELL_DRIVER);
- DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
-
- hsw_wait_for_power_well_disable(dev_priv, power_well);
- }
-
- if (check_fuse_status) {
- if (power_well->id == SKL_DISP_PW_1) {
- if (intel_wait_for_register(dev_priv,
- SKL_FUSE_STATUS,
- SKL_FUSE_PG_DIST_STATUS(1),
- SKL_FUSE_PG_DIST_STATUS(1),
- 1))
- DRM_ERROR("PG1 distributing status timeout\n");
- } else if (power_well->id == SKL_DISP_PW_2) {
- if (intel_wait_for_register(dev_priv,
- SKL_FUSE_STATUS,
- SKL_FUSE_PG_DIST_STATUS(2),
- SKL_FUSE_PG_DIST_STATUS(2),
- 1))
- DRM_ERROR("PG2 distributing status timeout\n");
- }
- }
-
- if (enable)
- skl_power_well_post_enable(dev_priv, power_well);
-}
-
static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -918,43 +801,6 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
}
}
-static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- uint32_t mask = HSW_PWR_WELL_CTL_REQ(power_well->id) |
- HSW_PWR_WELL_CTL_STATE(power_well->id);
-
- return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
-}
-
-static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- uint32_t mask = HSW_PWR_WELL_CTL_REQ(power_well->id);
- uint32_t bios_req = I915_READ(HSW_PWR_WELL_BIOS);
-
- /* Take over the request bit if set by BIOS. */
- if (bios_req & mask) {
- uint32_t drv_req = I915_READ(HSW_PWR_WELL_DRIVER);
-
- if (!(drv_req & mask))
- I915_WRITE(HSW_PWR_WELL_DRIVER, drv_req | mask);
- I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask);
- }
-}
-
-static void skl_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- skl_set_power_well(dev_priv, power_well, true);
-}
-
-static void skl_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- skl_set_power_well(dev_priv, power_well, false);
-}
-
static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -2042,13 +1888,6 @@ static const struct i915_power_well_ops hsw_power_well_ops = {
.is_enabled = hsw_power_well_enabled,
};
-static const struct i915_power_well_ops skl_power_well_ops = {
- .sync_hw = skl_power_well_sync_hw,
- .enable = skl_power_well_enable,
- .disable = skl_power_well_disable,
- .is_enabled = skl_power_well_enabled,
-};
-
static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = gen9_dc_off_power_well_enable,
@@ -2234,14 +2073,15 @@ static struct i915_power_well skl_power_wells[] = {
.name = "power well 1",
/* Handled by the DMC firmware */
.domains = 0,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
+ .hsw.has_fuses = true,
},
{
.name = "MISC IO power well",
/* Handled by the DMC firmware */
.domains = 0,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_MISC_IO,
},
{
@@ -2253,31 +2093,34 @@ static struct i915_power_well skl_power_wells[] = {
{
.name = "power well 2",
.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
},
{
.name = "DDI A/E IO power well",
.domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_A_E,
},
{
.name = "DDI B IO power well",
.domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_B,
},
{
.name = "DDI C IO power well",
.domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_C,
},
{
.name = "DDI D IO power well",
.domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_D,
},
};
@@ -2293,8 +2136,9 @@ static struct i915_power_well bxt_power_wells[] = {
{
.name = "power well 1",
.domains = 0,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
+ .hsw.has_fuses = true,
},
{
.name = "DC off",
@@ -2305,8 +2149,11 @@ static struct i915_power_well bxt_power_wells[] = {
{
.name = "power well 2",
.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
},
{
.name = "dpio-common-a",
@@ -2336,8 +2183,9 @@ static struct i915_power_well glk_power_wells[] = {
.name = "power well 1",
/* Handled by the DMC firmware */
.domains = 0,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
+ .hsw.has_fuses = true,
},
{
.name = "DC off",
@@ -2348,8 +2196,11 @@ static struct i915_power_well glk_power_wells[] = {
{
.name = "power well 2",
.domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
},
{
.name = "dpio-common-a",
@@ -2375,37 +2226,37 @@ static struct i915_power_well glk_power_wells[] = {
{
.name = "AUX A",
.domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = GLK_DISP_PW_AUX_A,
},
{
.name = "AUX B",
.domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = GLK_DISP_PW_AUX_B,
},
{
.name = "AUX C",
.domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = GLK_DISP_PW_AUX_C,
},
{
.name = "DDI A IO power well",
.domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = GLK_DISP_PW_DDI_A,
},
{
.name = "DDI B IO power well",
.domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_B,
},
{
.name = "DDI C IO power well",
.domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_C,
},
};
@@ -2422,31 +2273,32 @@ static struct i915_power_well cnl_power_wells[] = {
.name = "power well 1",
/* Handled by the DMC firmware */
.domains = 0,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
+ .hsw.has_fuses = true,
},
{
.name = "AUX A",
.domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_AUX_A,
},
{
.name = "AUX B",
.domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_AUX_B,
},
{
.name = "AUX C",
.domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_AUX_C,
},
{
.name = "AUX D",
.domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_AUX_D,
},
{
@@ -2458,31 +2310,34 @@ static struct i915_power_well cnl_power_wells[] = {
{
.name = "power well 2",
.domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
},
{
.name = "DDI A IO power well",
.domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_DDI_A,
},
{
.name = "DDI B IO power well",
.domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_B,
},
{
.name = "DDI C IO power well",
.domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_C,
},
{
.name = "DDI D IO power well",
.domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_D,
},
};
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 17/18] drm/i915: Move hsw_power_well_enable() next to the rest of HSW helpers
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (15 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 16/18] drm/i915/gen9+: Unify the HSW/BDW and GEN9+ power well helpers Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-21 13:29 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 18/18] drm/i915: Gather all the power well->domain mappings to one place Imre Deak
` (4 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
Move the helper next to the rest of HSW specific code.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 68b7183..aaa2871 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -169,20 +169,6 @@ static void intel_power_well_put(struct drm_i915_private *dev_priv,
intel_power_well_disable(dev_priv, power_well);
}
-/*
- * We should only use the power well if we explicitly asked the hardware to
- * enable it, so check if it's enabled and also check if we've requested it to
- * be enabled.
- */
-static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- enum i915_power_well_id id = power_well->id;
- u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id);
-
- return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
-}
-
/**
* __intel_display_power_is_enabled - unlocked check for a power domain
* @dev_priv: i915 device instance
@@ -415,6 +401,20 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
hsw_wait_for_power_well_disable(dev_priv, power_well);
}
+/*
+ * We should only use the power well if we explicitly asked the hardware to
+ * enable it, so check if it's enabled and also check if we've requested it to
+ * be enabled.
+ */
+static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum i915_power_well_id id = power_well->id;
+ u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id);
+
+ return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
+}
+
#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 18/18] drm/i915: Gather all the power well->domain mappings to one place
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (16 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 17/18] drm/i915: Move hsw_power_well_enable() next to the rest of HSW helpers Imre Deak
@ 2017-07-06 14:40 ` Imre Deak
2017-07-21 13:39 ` Arkadiusz Hiler
2017-07-06 15:51 ` ✓ Fi.CI.BAT: success for drm/i915: Unify the HSW/BDW and GEN9+ power well code Patchwork
` (3 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-06 14:40 UTC (permalink / raw)
To: intel-gfx
Shuffle the power well->domain mapping macros around so they are at one
place in old->new GEN order.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 408 ++++++++++++++++----------------
1 file changed, 204 insertions(+), 204 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index aaa2871..dfb17ff 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -415,172 +415,6 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
}
-#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_AUDIO) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUDIO) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUDIO) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
-#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
-#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
-#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_AUDIO) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
{
WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
@@ -1705,37 +1539,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
intel_runtime_pm_put(dev_priv);
}
-#define HSW_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define BDW_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO) | \
+#define I830_PIPES_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DISPLAY_POWER_DOMAINS ( \
@@ -1818,13 +1628,203 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
-#define I830_PIPES_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+#define HSW_DISPLAY_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define BDW_DISPLAY_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_GMBUS) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
+#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
+#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
+#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Unify the HSW/BDW and GEN9+ power well code
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (17 preceding siblings ...)
2017-07-06 14:40 ` [PATCH 18/18] drm/i915: Gather all the power well->domain mappings to one place Imre Deak
@ 2017-07-06 15:51 ` Patchwork
2017-07-07 14:59 ` ✓ Fi.CI.BAT: success for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev2) Patchwork
` (2 subsequent siblings)
21 siblings, 0 replies; 64+ messages in thread
From: Patchwork @ 2017-07-06 15:51 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Unify the HSW/BDW and GEN9+ power well code
URL : https://patchwork.freedesktop.org/series/26922/
State : success
== Summary ==
Series 26922v1 drm/i915: Unify the HSW/BDW and GEN9+ power well code
https://patchwork.freedesktop.org/api/1.0/series/26922/revisions/1/mbox/
Test gem_exec_suspend:
Subgroup basic-s4-devices:
dmesg-warn -> PASS (fi-kbl-7560u) fdo#100125
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
dmesg-warn -> PASS (fi-pnv-d510) fdo#101597
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:444s
fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:435s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:360s
fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:523s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:504s
fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:489s
fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:485s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:598s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:434s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:410s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:420s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:484s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:459s
fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:577s
fi-kbl-r total:279 pass:260 dwarn:1 dfail:0 fail:0 skip:18 time:583s
fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:560s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:460s
fi-skl-6700hq total:279 pass:262 dwarn:0 dfail:0 fail:0 skip:17 time:586s
fi-skl-6700k total:279 pass:257 dwarn:4 dfail:0 fail:0 skip:18 time:466s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:486s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:437s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:544s
fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:406s
13173bea86ebf8643a32b8373eeadd3fdcd1cc4d drm-tip: 2017y-07m-06d-14h-15m-52s UTC integration manifest
7901382 drm/i915: Gather all the power well->domain mappings to one place
0975571 drm/i915: Move hsw_power_well_enable() next to the rest of HSW helpers
fe0d218 drm/i915/gen9+: Unify the HSW/BDW and GEN9+ power well helpers
7c8c876 drm/i915/hsw+: Add has_fuses power well attribute
367da6b drm/i915/hsw, bdw: Wait for the power well disabled state
f530fd8 drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes
62c6606 drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros
7356e02 drm/i915/hsw, bdw: Split power well set to enable/disable helpers
52a5d3d drm/i915/hsw, bdw: Remove redundant state check during power well toggling
401d3f1 drm/i915/gen9+: Remove redundant state check during power well toggling
7b08a87 drm/i915/gen9+: Remove redundant power well state assert during enabling
16f9234 drm/i915/bxt, glk: Give a proper name to the power well struct phy field
1a2425c drm/i915: Check for duplicated power well IDs
1057bcf drm/i915/hsw, bdw: Add an ID for the global display power well
6660ee8 drm/i915/gen2: Add an ID for the display pipes power well
853a3d6 drm/i915: Assign everywhere the always-on power well ID
10c6a6b drm/i915: Unify power well ID enums
4e96740 drm/i915/chv: Add unique power well ID for the pipe A power well
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5126/
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v2 06/18] drm/i915: Check for duplicated power well IDs
2017-07-06 14:40 ` [PATCH 06/18] drm/i915: Check for duplicated power well IDs Imre Deak
@ 2017-07-07 14:39 ` Imre Deak
2017-07-11 17:08 ` Ville Syrjälä
2017-07-11 20:42 ` [PATCH v3 " Imre Deak
1 sibling, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-07 14:39 UTC (permalink / raw)
To: intel-gfx
Check that all the power well IDs are unique on the given platform.
v2:
- Fix using BIT_ULL() instead of BIT() for 64 bit mask.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 27c69f9..bc17d2f 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2563,6 +2563,8 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
int intel_power_domains_init(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ u64 power_well_ids;
+ int i;
i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
i915.disable_power_well);
@@ -2599,6 +2601,15 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
set_power_wells(power_domains, i9xx_always_on_power_well);
}
+ power_well_ids = 0;
+ for (i = 0; i < power_domains->power_well_count; i++) {
+ enum i915_power_well_id id = power_domains->power_wells[i].id;
+
+ WARN_ON(id >= sizeof(power_well_ids) * 8);
+ WARN_ON(power_well_ids & BIT_ULL(id));
+ power_well_ids |= BIT_ULL(id);
+ }
+
return 0;
}
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev2)
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (18 preceding siblings ...)
2017-07-06 15:51 ` ✓ Fi.CI.BAT: success for drm/i915: Unify the HSW/BDW and GEN9+ power well code Patchwork
@ 2017-07-07 14:59 ` Patchwork
2017-07-11 21:01 ` ✗ Fi.CI.BAT: warning for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev8) Patchwork
2017-07-12 16:17 ` ✗ Fi.CI.BAT: failure for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev9) Patchwork
21 siblings, 0 replies; 64+ messages in thread
From: Patchwork @ 2017-07-07 14:59 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev2)
URL : https://patchwork.freedesktop.org/series/26922/
State : success
== Summary ==
Series 26922v2 drm/i915: Unify the HSW/BDW and GEN9+ power well code
https://patchwork.freedesktop.org/api/1.0/series/26922/revisions/2/mbox/
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail -> PASS (fi-snb-2600) fdo#100215
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
pass -> DMESG-WARN (fi-pnv-d510) fdo#101597 +1
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:444s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:355s
fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:535s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:511s
fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:493s
fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:485s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:600s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:439s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:417s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:425s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:503s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:476s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:466s
fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:593s
fi-kbl-r total:279 pass:260 dwarn:1 dfail:0 fail:0 skip:18 time:584s
fi-pnv-d510 total:279 pass:221 dwarn:3 dfail:0 fail:0 skip:55 time:565s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:462s
fi-skl-6700hq total:279 pass:262 dwarn:0 dfail:0 fail:0 skip:17 time:585s
fi-skl-6700k total:279 pass:257 dwarn:4 dfail:0 fail:0 skip:18 time:469s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:475s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:434s
fi-skl-x1585l total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:473s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:538s
fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:405s
fi-bdw-gvtdvm failed to collect. IGT log at Patchwork_5143/fi-bdw-gvtdvm/igt.log
c07f01228c2240ec9604cb9fa4647ccfe575b8a6 drm-tip: 2017y-07m-07d-10h-10m-58s UTC integration manifest
adbc9b0 drm/i915: Gather all the power well->domain mappings to one place
07a919f drm/i915: Move hsw_power_well_enable() next to the rest of HSW helpers
43c087e drm/i915/gen9+: Unify the HSW/BDW and GEN9+ power well helpers
d34c37c drm/i915/hsw+: Add has_fuses power well attribute
01897a9 drm/i915/hsw, bdw: Wait for the power well disabled state
f43b6e7 drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes
a4fc293 drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros
8270740 drm/i915/hsw, bdw: Split power well set to enable/disable helpers
3afa0ea drm/i915/hsw, bdw: Remove redundant state check during power well toggling
52856913 drm/i915/gen9+: Remove redundant state check during power well toggling
fb4372a drm/i915/gen9+: Remove redundant power well state assert during enabling
8f01d13 drm/i915/bxt, glk: Give a proper name to the power well struct phy field
ac8523e drm/i915: Check for duplicated power well IDs
d615377 drm/i915/hsw, bdw: Add an ID for the global display power well
4dfaf50 drm/i915/gen2: Add an ID for the display pipes power well
16a60f80 drm/i915: Assign everywhere the always-on power well ID
3f2d8eb drm/i915: Unify power well ID enums
2ad982b drm/i915/chv: Add unique power well ID for the pipe A power well
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5143/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 01/18] drm/i915/chv: Add unique power well ID for the pipe A power well
2017-07-06 14:40 ` [PATCH 01/18] drm/i915/chv: Add unique power well ID for the pipe A power well Imre Deak
@ 2017-07-11 16:31 ` Rodrigo Vivi
0 siblings, 0 replies; 64+ messages in thread
From: Rodrigo Vivi @ 2017-07-11 16:31 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Thu, Jul 06, 2017 at 05:40:23PM +0300, Imre Deak wrote:
> The power well IDs are used for lookup, so they must be unique on a
> given platform; ensure this on CHV. This didn't cause an actual problem
> since we didn't need to look up power wells which happened to share an
> ID.
>
> Mark this new power well as custom, since its programming pattern
> doesn't follow that of the rest of VLV/CHV power wells.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 10 +++++-----
> 2 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 64cc674..3f7beff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1077,6 +1077,8 @@ enum punit_power_well {
> PUNIT_POWER_WELL_DPIO_RX0 = 10,
> PUNIT_POWER_WELL_DPIO_RX1 = 11,
> PUNIT_POWER_WELL_DPIO_CMN_D = 12,
> + /* - custom power well */
> + CHV_DISP_PW_PIPE_A, /* 13 */
>
> /* Not actual bit groups. Used as IDs for lookup_power_well() */
> PUNIT_POWER_WELL_ALWAYS_ON,
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 5eb9c5e..5f5dee4 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1672,7 +1672,7 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
> static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - enum pipe pipe = power_well->id;
> + enum pipe pipe = PIPE_A;
> bool enabled;
> u32 state, ctrl;
>
> @@ -1702,7 +1702,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well,
> bool enable)
> {
> - enum pipe pipe = power_well->id;
> + enum pipe pipe = PIPE_A;
> u32 state;
> u32 ctrl;
>
> @@ -1735,7 +1735,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
> static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - WARN_ON_ONCE(power_well->id != PIPE_A);
> + WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A);
>
> chv_set_pipe_power_well(dev_priv, power_well, true);
>
> @@ -1745,7 +1745,7 @@ static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
> static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - WARN_ON_ONCE(power_well->id != PIPE_A);
> + WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A);
>
> vlv_display_power_well_deinit(dev_priv);
>
> @@ -2184,7 +2184,7 @@ static struct i915_power_well chv_power_wells[] = {
> * required for any pipe to work.
> */
> .domains = CHV_DISPLAY_POWER_DOMAINS,
> - .id = PIPE_A,
> + .id = CHV_DISP_PW_PIPE_A,
> .ops = &chv_pipe_power_well_ops,
> },
> {
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 02/18] drm/i915: Unify power well ID enums
2017-07-06 14:40 ` [PATCH 02/18] drm/i915: Unify power well ID enums Imre Deak
@ 2017-07-11 16:43 ` Rodrigo Vivi
2017-07-11 17:21 ` Rodrigo Vivi
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
1 sibling, 1 reply; 64+ messages in thread
From: Rodrigo Vivi @ 2017-07-11 16:43 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 6, 2017 at 7:40 AM, Imre Deak <imre.deak@intel.com> wrote:
> Atm, the power well IDs are defined in separate platform specific enums,
> which isn't ideal for the following reasons:
> - the IDs are used by helpers like lookup_power_well() in a platform
> independent way
> - the always-on power well is used by multiple platforms and so needs
> now separate IDs, although these IDs refer to the same thing
I liked the always-on unifying... so much that I believe it deserved
a separated patch.
>
> To make things more consistent use a single enum instead of the two
> separate ones, listing the IDs per platform (or set of very similar
> platforms like all GEN9/10). Replace the separate always-on power
> well IDs with a single ID.
>
> While at it also add a note clarifying the distinction between regular
> power wells that follow a common programming pattern and custom ones
> that are programmed in some other way. The IDs for regular power wells
> need to stay fixed, since they also define the request and state HW flag
> positions in their corresponding power well control register(s).
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 41 ++++++++++++++++++++++-----------
> drivers/gpu/drm/i915/intel_runtime_pm.c | 29 ++++++++++++-----------
> 3 files changed, 44 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 81cd21e..c9b98ed 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1382,7 +1382,7 @@ struct i915_power_well {
> bool hw_enabled;
> u64 domains;
> /* unique identifier for this power well */
> - unsigned long id;
> + enum i915_power_well_id id;
> /*
> * Arbitraty data associated with this power well. Platform and power
> * well specific.
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3f7beff..e4135bd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1063,9 +1063,19 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
> #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
>
> -/* See the PUNIT HAS v0.8 for the below bits */
> -enum punit_power_well {
> - /* These numbers are fixed and must match the position of the pw bits */
> +/**
> + * i915_power_well_id:
> + *
> + * Platform specific IDs used to look up power wells and - except for custom
> + * power wells - to define request/status register flag bit positions. As such
> + * the set of IDs on a given platform must be unique and except for custom
> + * power wells their value must stay fixed.
> + */
> +enum i915_power_well_id {
> + /*
> + * VLV/CHV
> + * - PUNIT_REG_PWRGT_CTRL, PUNIT_REG_PWRGT_STATUS (PUNIT HAS v0.8)
> + */
> PUNIT_POWER_WELL_RENDER = 0,
> PUNIT_POWER_WELL_MEDIA = 1,
> PUNIT_POWER_WELL_DISP2D = 3,
> @@ -1080,13 +1090,11 @@ enum punit_power_well {
> /* - custom power well */
> CHV_DISP_PW_PIPE_A, /* 13 */
>
> - /* Not actual bit groups. Used as IDs for lookup_power_well() */
> - PUNIT_POWER_WELL_ALWAYS_ON,
> -};
> -
> -enum skl_disp_power_wells {
> - /* These numbers are fixed and must match the position of the pw bits */
> - SKL_DISP_PW_MISC_IO,
> + /*
> + * GEN9+
> + * - HSW_PWR_WELL_DRIVER
> + */
> + SKL_DISP_PW_MISC_IO = 0,
> SKL_DISP_PW_DDI_A_E,
> GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
> CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
> @@ -1105,13 +1113,18 @@ enum skl_disp_power_wells {
> SKL_DISP_PW_1 = 14,
> SKL_DISP_PW_2,
>
> - /* Not actual bit groups. Used as IDs for lookup_power_well() */
> - SKL_DISP_PW_ALWAYS_ON,
> + /* - custom power wells */
> SKL_DISP_PW_DC_OFF,
> -
> BXT_DPIO_CMN_A,
> BXT_DPIO_CMN_BC,
> - GLK_DPIO_CMN_C,
> + GLK_DPIO_CMN_C, /* 19 */
> +
> + /*
> + * Multiple platforms.
> + * Must start following the highest ID of any platform.
> + * - custom power wells
> + */
> + I915_DISP_PW_ALWAYS_ON = 20,
What about just leaving
I915_DISP_PW_ALWAYS_ON,
I have the feeling that if that increases we will forget to update here....
but I will leave you to decide... so, with or without any split or
change feel free to use:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> };
>
> #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 5f5dee4..ad314c1 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -50,10 +50,11 @@
> */
>
> bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
> - int power_well_id);
> + enum i915_power_well_id power_well_id);
>
> static struct i915_power_well *
> -lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id);
> +lookup_power_well(struct drm_i915_private *dev_priv,
> + enum i915_power_well_id power_well_id);
>
> const char *
> intel_display_power_domain_str(enum intel_display_power_domain domain)
> @@ -344,7 +345,7 @@ static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
> static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - int id = power_well->id;
> + enum i915_power_well_id id = power_well->id;
>
> /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
> WARN_ON(intel_wait_for_register(dev_priv,
> @@ -354,7 +355,8 @@ static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
> 1));
> }
>
> -static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, int id)
> +static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv,
> + enum i915_power_well_id id)
> {
> u32 req_mask = SKL_POWER_WELL_REQ(id);
> u32 ret;
> @@ -370,7 +372,7 @@ static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, int id)
> static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - int id = power_well->id;
> + enum i915_power_well_id id = power_well->id;
> bool disabled;
> u32 reqs;
>
> @@ -837,7 +839,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> case CNL_DISP_PW_AUX_D:
> break;
> default:
> - WARN(1, "Unknown power well %lu\n", power_well->id);
> + WARN(1, "Unknown power well %u\n", power_well->id);
> return;
> }
>
> @@ -1089,7 +1091,7 @@ static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
> static void vlv_set_power_well(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well, bool enable)
> {
> - enum punit_power_well power_well_id = power_well->id;
> + enum i915_power_well_id power_well_id = power_well->id;
> u32 mask;
> u32 state;
> u32 ctrl;
> @@ -1137,7 +1139,7 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
> static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - int power_well_id = power_well->id;
> + enum i915_power_well_id power_well_id = power_well->id;
> bool enabled = false;
> u32 mask;
> u32 state;
> @@ -1324,8 +1326,9 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
>
> #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
>
> -static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
> - int power_well_id)
> +static struct i915_power_well *
> +lookup_power_well(struct drm_i915_private *dev_priv,
> + enum i915_power_well_id power_well_id)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> int i;
> @@ -2117,7 +2120,7 @@ static struct i915_power_well vlv_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> - .id = PUNIT_POWER_WELL_ALWAYS_ON,
> + .id = I915_DISP_PW_ALWAYS_ON,
> },
> {
> .name = "display",
> @@ -2202,7 +2205,7 @@ static struct i915_power_well chv_power_wells[] = {
> };
>
> bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
> - int power_well_id)
> + enum i915_power_well_id power_well_id)
> {
> struct i915_power_well *power_well;
> bool ret;
> @@ -2219,7 +2222,7 @@ static struct i915_power_well skl_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> - .id = SKL_DISP_PW_ALWAYS_ON,
> + .id = I915_DISP_PW_ALWAYS_ON,
> },
> {
> .name = "power well 1",
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 03/18] drm/i915: Assign everywhere the always-on power well ID
2017-07-06 14:40 ` [PATCH 03/18] drm/i915: Assign everywhere the always-on power well ID Imre Deak
@ 2017-07-11 16:45 ` Rodrigo Vivi
0 siblings, 0 replies; 64+ messages in thread
From: Rodrigo Vivi @ 2017-07-11 16:45 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
couldn't we remove now .always_on variable?
anyways:
Reviewed-by Rodrigo Vivi <rodrigo.vivi@intel.com>
On Thu, Jul 6, 2017 at 7:40 AM, Imre Deak <imre.deak@intel.com> wrote:
> Power well IDs are used for lookup so they must be unique. To ensure
> this assign the always-on power well ID everywhere where it's missing.
> This didn't cause a problem so far, since we didn't need to look up
> power wells that happened to share their IDs.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index ad314c1..9601b62 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2013,6 +2013,7 @@ static struct i915_power_well i9xx_always_on_power_well[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> + .id = I915_DISP_PW_ALWAYS_ON,
> },
> };
>
> @@ -2029,6 +2030,7 @@ static struct i915_power_well i830_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> + .id = I915_DISP_PW_ALWAYS_ON,
> },
> {
> .name = "pipes",
> @@ -2071,6 +2073,7 @@ static struct i915_power_well hsw_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> + .id = I915_DISP_PW_ALWAYS_ON,
> },
> {
> .name = "display",
> @@ -2085,6 +2088,7 @@ static struct i915_power_well bdw_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> + .id = I915_DISP_PW_ALWAYS_ON,
> },
> {
> .name = "display",
> @@ -2178,6 +2182,7 @@ static struct i915_power_well chv_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> + .id = I915_DISP_PW_ALWAYS_ON,
> },
> {
> .name = "display",
> @@ -2282,6 +2287,7 @@ static struct i915_power_well bxt_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> + .id = I915_DISP_PW_ALWAYS_ON,
> },
> {
> .name = "power well 1",
> @@ -2323,6 +2329,7 @@ static struct i915_power_well glk_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> + .id = I915_DISP_PW_ALWAYS_ON,
> },
> {
> .name = "power well 1",
> @@ -2408,6 +2415,7 @@ static struct i915_power_well cnl_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> + .id = I915_DISP_PW_ALWAYS_ON,
> },
> {
> .name = "power well 1",
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 04/18] drm/i915/gen2: Add an ID for the display pipes power well
2017-07-06 14:40 ` [PATCH 04/18] drm/i915/gen2: Add an ID for the display pipes power well Imre Deak
@ 2017-07-11 16:50 ` Rodrigo Vivi
2017-07-11 17:01 ` Ville Syrjälä
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
2 siblings, 0 replies; 64+ messages in thread
From: Rodrigo Vivi @ 2017-07-11 16:50 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Thu, Jul 6, 2017 at 7:40 AM, Imre Deak <imre.deak@intel.com> wrote:
> Make the GEN2 power well ID assignment explicit for consistency.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e4135bd..ce90847 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1073,6 +1073,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> */
> enum i915_power_well_id {
> /*
> + * GEN2
> + * - custom power well
> + */
> + I830_DISP_PW_PIPES = 0,
> +
> + /*
> * VLV/CHV
> * - PUNIT_REG_PWRGT_CTRL, PUNIT_REG_PWRGT_STATUS (PUNIT HAS v0.8)
> */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 9601b62..4a9d955 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2036,6 +2036,7 @@ static struct i915_power_well i830_power_wells[] = {
> .name = "pipes",
> .domains = I830_PIPES_POWER_DOMAINS,
> .ops = &i830_pipes_power_well_ops,
> + .id = I830_DISP_PW_PIPES,
> },
> };
>
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 04/18] drm/i915/gen2: Add an ID for the display pipes power well
2017-07-06 14:40 ` [PATCH 04/18] drm/i915/gen2: Add an ID for the display pipes power well Imre Deak
2017-07-11 16:50 ` Rodrigo Vivi
@ 2017-07-11 17:01 ` Ville Syrjälä
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
2 siblings, 0 replies; 64+ messages in thread
From: Ville Syrjälä @ 2017-07-11 17:01 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 06, 2017 at 05:40:26PM +0300, Imre Deak wrote:
> Make the GEN2 power well ID assignment explicit for consistency.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e4135bd..ce90847 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1073,6 +1073,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> */
> enum i915_power_well_id {
> /*
> + * GEN2
Just 830 actually. Rest of gen2 don't have this.
> + * - custom power well
> + */
> + I830_DISP_PW_PIPES = 0,
> +
> + /*
> * VLV/CHV
> * - PUNIT_REG_PWRGT_CTRL, PUNIT_REG_PWRGT_STATUS (PUNIT HAS v0.8)
> */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 9601b62..4a9d955 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2036,6 +2036,7 @@ static struct i915_power_well i830_power_wells[] = {
> .name = "pipes",
> .domains = I830_PIPES_POWER_DOMAINS,
> .ops = &i830_pipes_power_well_ops,
> + .id = I830_DISP_PW_PIPES,
> },
> };
>
> --
> 2.7.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 13/18] drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes
2017-07-06 14:40 ` [PATCH 13/18] drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes Imre Deak
@ 2017-07-11 17:02 ` Ville Syrjälä
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
2017-07-12 15:54 ` [PATCH v3 " Imre Deak
2 siblings, 0 replies; 64+ messages in thread
From: Ville Syrjälä @ 2017-07-11 17:02 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 06, 2017 at 05:40:35PM +0300, Imre Deak wrote:
> The pattern of a power well backing a set of pipe IRQ or VGA
> functionality applies to all HSW+ platforms. Using power well attributes
> instead of platform checks to decide whether to init/reset pipe IRQs and
> VGA correspondingly is cleaner and it allows us to unify the HSW/BDW and
> GEN9+ power well code in follow-up patches.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 34 ++++++++++++++++++++-------------
> 2 files changed, 27 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b27f2fc..dc5ca5a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1391,6 +1391,12 @@ struct i915_power_well {
> struct {
> enum dpio_phy phy;
> } bxt;
> + struct {
> + /* Mask of pipes whose IRQ logic is backed by the pw */
> + u32 irq_pipe_mask;
u8 would be plenty. Might help keep the size down by a few bytes.
> + /* The pw is backing the VGA functionality */
> + bool has_vga:1;
> + } hsw;
> };
> const struct i915_power_well_ops *ops;
> };
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index e18c38e6..ab2e0ee 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -281,7 +281,8 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv,
> * to be enabled, and it will only be disabled if none of the registers is
> * requesting it to be enabled.
> */
> -static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
> +static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
> + u32 irq_pipe_mask, bool has_vga)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
>
> @@ -295,20 +296,21 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
> * sure vgacon can keep working normally without triggering interrupts
> * and error messages.
> */
> - vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
> - outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
> - vga_put(pdev, VGA_RSRC_LEGACY_IO);
> + if (has_vga) {
> + vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
> + outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
> + vga_put(pdev, VGA_RSRC_LEGACY_IO);
> + }
>
> - if (IS_BROADWELL(dev_priv))
> - gen8_irq_power_well_post_enable(dev_priv,
> - 1 << PIPE_C | 1 << PIPE_B);
> + if (irq_pipe_mask)
> + gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
> }
>
> -static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
> +static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
> + u32 irq_pipe_mask)
> {
> - if (IS_BROADWELL(dev_priv))
> - gen8_irq_power_well_pre_disable(dev_priv,
> - 1 << PIPE_C | 1 << PIPE_B);
> + if (irq_pipe_mask)
> + gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
> }
>
> static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
> @@ -413,7 +415,9 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> HSW_PWR_WELL_CTL_STATE(id),
> 20))
> DRM_ERROR("Timeout enabling power well\n");
> - hsw_power_well_post_enable(dev_priv);
> +
> + hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
> + power_well->hsw.has_vga);
> }
>
> static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
> @@ -422,7 +426,8 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
> enum i915_power_well_id id = power_well->id;
> u32 val;
>
> - hsw_power_well_pre_disable(dev_priv);
> + hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask);
> +
> val = I915_READ(HSW_PWR_WELL_DRIVER);
> I915_WRITE(HSW_PWR_WELL_DRIVER, val & ~HSW_PWR_WELL_CTL_REQ(id));
> POSTING_READ(HSW_PWR_WELL_DRIVER);
> @@ -2057,6 +2062,7 @@ static struct i915_power_well hsw_power_wells[] = {
> .domains = HSW_DISPLAY_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = HSW_DISP_PW_GLOBAL,
> + .hsw.has_vga = true,
> },
> };
>
> @@ -2073,6 +2079,8 @@ static struct i915_power_well bdw_power_wells[] = {
> .domains = BDW_DISPLAY_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = HSW_DISP_PW_GLOBAL,
> + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> + .hsw.has_vga = true,
> },
> };
>
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 15/18] drm/i915/hsw+: Add has_fuses power well attribute
2017-07-06 14:40 ` [PATCH 15/18] drm/i915/hsw+: Add has_fuses power well attribute Imre Deak
@ 2017-07-11 17:05 ` Ville Syrjälä
2017-07-11 17:22 ` Imre Deak
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
1 sibling, 1 reply; 64+ messages in thread
From: Ville Syrjälä @ 2017-07-11 17:05 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 06, 2017 at 05:40:37PM +0300, Imre Deak wrote:
> The pattern of a power well backing a set of fuses whose initialization
> we need to wait for during power well enabling is common to all GEN9+
> platforms. Adding support for this to the HSW power well enable helper
> allows us to use the HSW/BDW power well code for GEN9+ as well in a
> follow-up patch.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/gvt/display.c | 6 +++---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
> drivers/gpu/drm/i915/intel_runtime_pm.c | 34 ++++++++++++++++++++++++++-------
> 4 files changed, 35 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index 2deb05f..13599bb 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -178,9 +178,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
> SDE_PORTE_HOTPLUG_SPT);
> vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=
> SKL_FUSE_DOWNLOAD_STATUS |
> - SKL_FUSE_PG0_DIST_STATUS |
> - SKL_FUSE_PG1_DIST_STATUS |
> - SKL_FUSE_PG2_DIST_STATUS;
> + SKL_FUSE_PG_DIST_STATUS(0) |
> + SKL_FUSE_PG_DIST_STATUS(1) |
> + SKL_FUSE_PG_DIST_STATUS(2);
> vgpu_vreg(vgpu, LCPLL1_CTL) |=
> LCPLL_PLL_ENABLE |
> LCPLL_PLL_LOCK;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index dc5ca5a..9e97536 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1396,6 +1396,7 @@ struct i915_power_well {
> u32 irq_pipe_mask;
> /* The pw is backing the VGA functionality */
> bool has_vga:1;
> + bool has_fuses:1;
> } hsw;
> };
> const struct i915_power_well_ops *ops;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 845f50c..794d65c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8023,10 +8023,10 @@ enum {
>
> /* SKL Fuse Status */
> #define SKL_FUSE_STATUS _MMIO(0x42000)
> -#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
> -#define SKL_FUSE_PG0_DIST_STATUS (1<<27)
> -#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
> -#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
> +#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
> +/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */
> +#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + 1)
> +#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
>
> /* Per-pipe DDI Function Control */
> #define _TRANS_DDI_FUNC_CTL_A 0x60400
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 14d4ff4..c204be0 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -400,16 +400,36 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
> !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
> }
>
> +static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
> + int pg)
> +{
> + /* Timeout 5us for PG#0, for other PGs 1us */
> + WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS,
> + SKL_FUSE_PG_DIST_STATUS(pg),
> + SKL_FUSE_PG_DIST_STATUS(pg), 1));
> +}
> +
> static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> enum i915_power_well_id id = power_well->id;
> + bool wait_fuses = power_well->hsw.has_fuses;
> + int pg;
> u32 val;
>
> + if (wait_fuses) {
> + pg = SKL_PW_TO_PG(id);
> + if (pg == 1)
> + gen9_wait_for_power_well_fuses(dev_priv, pg - 1);
> + }
This part looks magicy. The macro adds 1, but here you have to subtract
1 when feeding it the value, which seems odd. And apparently 1 is somehow
special, but I can't tell why.
> +
> val = I915_READ(HSW_PWR_WELL_DRIVER);
> I915_WRITE(HSW_PWR_WELL_DRIVER, val | HSW_PWR_WELL_CTL_REQ(id));
> hsw_wait_for_power_well_enable(dev_priv, power_well);
>
> + if (wait_fuses)
> + gen9_wait_for_power_well_fuses(dev_priv, pg);
> +
> hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
> power_well->hsw.has_vga);
> }
> @@ -810,15 +830,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> case SKL_DISP_PW_1:
> if (intel_wait_for_register(dev_priv,
> SKL_FUSE_STATUS,
> - SKL_FUSE_PG0_DIST_STATUS,
> - SKL_FUSE_PG0_DIST_STATUS,
> + SKL_FUSE_PG_DIST_STATUS(0),
> + SKL_FUSE_PG_DIST_STATUS(0),
> 1)) {
> DRM_ERROR("PG0 not enabled\n");
> return;
> }
> break;
> case SKL_DISP_PW_2:
> - if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
> + if (!(fuse_status & SKL_FUSE_PG_DIST_STATUS(1))) {
> DRM_ERROR("PG1 in disabled state\n");
> return;
> }
> @@ -863,15 +883,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> if (power_well->id == SKL_DISP_PW_1) {
> if (intel_wait_for_register(dev_priv,
> SKL_FUSE_STATUS,
> - SKL_FUSE_PG1_DIST_STATUS,
> - SKL_FUSE_PG1_DIST_STATUS,
> + SKL_FUSE_PG_DIST_STATUS(1),
> + SKL_FUSE_PG_DIST_STATUS(1),
> 1))
> DRM_ERROR("PG1 distributing status timeout\n");
> } else if (power_well->id == SKL_DISP_PW_2) {
> if (intel_wait_for_register(dev_priv,
> SKL_FUSE_STATUS,
> - SKL_FUSE_PG2_DIST_STATUS,
> - SKL_FUSE_PG2_DIST_STATUS,
> + SKL_FUSE_PG_DIST_STATUS(2),
> + SKL_FUSE_PG_DIST_STATUS(2),
> 1))
> DRM_ERROR("PG2 distributing status timeout\n");
> }
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 05/18] drm/i915/hsw, bdw: Add an ID for the global display power well
2017-07-06 14:40 ` [PATCH 05/18] drm/i915/hsw, bdw: Add an ID for the global display " Imre Deak
@ 2017-07-11 17:08 ` Rodrigo Vivi
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
1 sibling, 0 replies; 64+ messages in thread
From: Rodrigo Vivi @ 2017-07-11 17:08 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 6, 2017 at 7:40 AM, Imre Deak <imre.deak@intel.com> wrote:
> Add an ID for the HSW/BDW global display power well for consistency. The
> ID is selected so that it can be used to get at the HW request and
> status flags with the corresponding GEN9+ macros. Unifying the HSW/BDW
> and GEN9+ versions of these macros and the power well ops using them
> will be done in follow-up patches.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ce90847..f798023 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1097,6 +1097,12 @@ enum i915_power_well_id {
> CHV_DISP_PW_PIPE_A, /* 13 */
>
> /*
> + * HSW/BDW
> + * - HSW_PWR_WELL_DRIVER
> + */
> + HSW_DISP_PW_GLOBAL = 15,
for a moment I thought it was custom, but I decided to check and yep,
this is the right one...
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> +
> + /*
> * GEN9+
> * - HSW_PWR_WELL_DRIVER
> */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 4a9d955..27c69f9 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2080,6 +2080,7 @@ static struct i915_power_well hsw_power_wells[] = {
> .name = "display",
> .domains = HSW_DISPLAY_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> + .id = HSW_DISP_PW_GLOBAL,
> },
> };
>
> @@ -2095,6 +2096,7 @@ static struct i915_power_well bdw_power_wells[] = {
> .name = "display",
> .domains = BDW_DISPLAY_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> + .id = HSW_DISP_PW_GLOBAL,
> },
> };
>
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v2 06/18] drm/i915: Check for duplicated power well IDs
2017-07-07 14:39 ` [PATCH v2 " Imre Deak
@ 2017-07-11 17:08 ` Ville Syrjälä
0 siblings, 0 replies; 64+ messages in thread
From: Ville Syrjälä @ 2017-07-11 17:08 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Fri, Jul 07, 2017 at 05:39:07PM +0300, Imre Deak wrote:
> Check that all the power well IDs are unique on the given platform.
>
> v2:
> - Fix using BIT_ULL() instead of BIT() for 64 bit mask.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 27c69f9..bc17d2f 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2563,6 +2563,8 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
> int intel_power_domains_init(struct drm_i915_private *dev_priv)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> + u64 power_well_ids;
> + int i;
>
> i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
> i915.disable_power_well);
> @@ -2599,6 +2601,15 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> set_power_wells(power_domains, i9xx_always_on_power_well);
> }
>
> + power_well_ids = 0;
> + for (i = 0; i < power_domains->power_well_count; i++) {
> + enum i915_power_well_id id = power_domains->power_wells[i].id;
> +
> + WARN_ON(id >= sizeof(power_well_ids) * 8);
> + WARN_ON(power_well_ids & BIT_ULL(id));
> + power_well_ids |= BIT_ULL(id);
> + }
Like Rodrigo, I was also worried about conflicting power well IDs, but
this should at least give us a runtime warning. Compile time error
would be nicer, but I guess there's no good way to do that.
Maybe pull this code into a separate functions called
assert_power_well_ids_unique() or something like that? That way you
wouldn't have to actually read the code to figure out what it's doing.
> +
> return 0;
> }
>
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 02/18] drm/i915: Unify power well ID enums
2017-07-11 16:43 ` Rodrigo Vivi
@ 2017-07-11 17:21 ` Rodrigo Vivi
2017-07-11 17:36 ` Imre Deak
0 siblings, 1 reply; 64+ messages in thread
From: Rodrigo Vivi @ 2017-07-11 17:21 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, Jul 11, 2017 at 9:43 AM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> On Thu, Jul 6, 2017 at 7:40 AM, Imre Deak <imre.deak@intel.com> wrote:
>> Atm, the power well IDs are defined in separate platform specific enums,
>> which isn't ideal for the following reasons:
>> - the IDs are used by helpers like lookup_power_well() in a platform
>> independent way
>> - the always-on power well is used by multiple platforms and so needs
>> now separate IDs, although these IDs refer to the same thing
>
> I liked the always-on unifying... so much that I believe it deserved
> a separated patch.
>
>>
>> To make things more consistent use a single enum instead of the two
>> separate ones, listing the IDs per platform (or set of very similar
>> platforms like all GEN9/10). Replace the separate always-on power
>> well IDs with a single ID.
>>
>> While at it also add a note clarifying the distinction between regular
>> power wells that follow a common programming pattern and custom ones
>> that are programmed in some other way. The IDs for regular power wells
>> need to stay fixed, since they also define the request and state HW flag
>> positions in their corresponding power well control register(s).
>>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Imre Deak <imre.deak@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 +-
>> drivers/gpu/drm/i915/i915_reg.h | 41 ++++++++++++++++++++++-----------
>> drivers/gpu/drm/i915/intel_runtime_pm.c | 29 ++++++++++++-----------
>> 3 files changed, 44 insertions(+), 28 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 81cd21e..c9b98ed 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1382,7 +1382,7 @@ struct i915_power_well {
>> bool hw_enabled;
>> u64 domains;
>> /* unique identifier for this power well */
>> - unsigned long id;
>> + enum i915_power_well_id id;
>> /*
>> * Arbitraty data associated with this power well. Platform and power
>> * well specific.
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 3f7beff..e4135bd 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1063,9 +1063,19 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>> #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
>> #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
>>
>> -/* See the PUNIT HAS v0.8 for the below bits */
>> -enum punit_power_well {
>> - /* These numbers are fixed and must match the position of the pw bits */
>> +/**
>> + * i915_power_well_id:
>> + *
>> + * Platform specific IDs used to look up power wells and - except for custom
>> + * power wells - to define request/status register flag bit positions. As such
>> + * the set of IDs on a given platform must be unique and except for custom
>> + * power wells their value must stay fixed.
Actually I have one request here.
Could you please add a comment that state bit is id*2 and req is id*2+1?
Before your series this definition was right below, but with your
series applied it takes me a few extra steps to remember where it was
defined to check that HSW/BDW id 15...
>> + */
>> +enum i915_power_well_id {
>> + /*
>> + * VLV/CHV
>> + * - PUNIT_REG_PWRGT_CTRL, PUNIT_REG_PWRGT_STATUS (PUNIT HAS v0.8)
>> + */
>> PUNIT_POWER_WELL_RENDER = 0,
>> PUNIT_POWER_WELL_MEDIA = 1,
>> PUNIT_POWER_WELL_DISP2D = 3,
>> @@ -1080,13 +1090,11 @@ enum punit_power_well {
>> /* - custom power well */
>> CHV_DISP_PW_PIPE_A, /* 13 */
>>
>> - /* Not actual bit groups. Used as IDs for lookup_power_well() */
>> - PUNIT_POWER_WELL_ALWAYS_ON,
>> -};
>> -
>> -enum skl_disp_power_wells {
>> - /* These numbers are fixed and must match the position of the pw bits */
>> - SKL_DISP_PW_MISC_IO,
>> + /*
>> + * GEN9+
>> + * - HSW_PWR_WELL_DRIVER
>> + */
>> + SKL_DISP_PW_MISC_IO = 0,
>> SKL_DISP_PW_DDI_A_E,
>> GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
>> CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
>> @@ -1105,13 +1113,18 @@ enum skl_disp_power_wells {
>> SKL_DISP_PW_1 = 14,
>> SKL_DISP_PW_2,
>>
>> - /* Not actual bit groups. Used as IDs for lookup_power_well() */
>> - SKL_DISP_PW_ALWAYS_ON,
>> + /* - custom power wells */
>> SKL_DISP_PW_DC_OFF,
>> -
>> BXT_DPIO_CMN_A,
>> BXT_DPIO_CMN_BC,
>> - GLK_DPIO_CMN_C,
>> + GLK_DPIO_CMN_C, /* 19 */
>> +
>> + /*
>> + * Multiple platforms.
>> + * Must start following the highest ID of any platform.
>> + * - custom power wells
>> + */
>> + I915_DISP_PW_ALWAYS_ON = 20,
>
> What about just leaving
> I915_DISP_PW_ALWAYS_ON,
>
> I have the feeling that if that increases we will forget to update here....
>
> but I will leave you to decide... so, with or without any split or
> change feel free to use:
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
>> };
>>
>> #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
>> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> index 5f5dee4..ad314c1 100644
>> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> @@ -50,10 +50,11 @@
>> */
>>
>> bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
>> - int power_well_id);
>> + enum i915_power_well_id power_well_id);
>>
>> static struct i915_power_well *
>> -lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id);
>> +lookup_power_well(struct drm_i915_private *dev_priv,
>> + enum i915_power_well_id power_well_id);
>>
>> const char *
>> intel_display_power_domain_str(enum intel_display_power_domain domain)
>> @@ -344,7 +345,7 @@ static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
>> static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
>> struct i915_power_well *power_well)
>> {
>> - int id = power_well->id;
>> + enum i915_power_well_id id = power_well->id;
>>
>> /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
>> WARN_ON(intel_wait_for_register(dev_priv,
>> @@ -354,7 +355,8 @@ static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
>> 1));
>> }
>>
>> -static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, int id)
>> +static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv,
>> + enum i915_power_well_id id)
>> {
>> u32 req_mask = SKL_POWER_WELL_REQ(id);
>> u32 ret;
>> @@ -370,7 +372,7 @@ static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, int id)
>> static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
>> struct i915_power_well *power_well)
>> {
>> - int id = power_well->id;
>> + enum i915_power_well_id id = power_well->id;
>> bool disabled;
>> u32 reqs;
>>
>> @@ -837,7 +839,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>> case CNL_DISP_PW_AUX_D:
>> break;
>> default:
>> - WARN(1, "Unknown power well %lu\n", power_well->id);
>> + WARN(1, "Unknown power well %u\n", power_well->id);
>> return;
>> }
>>
>> @@ -1089,7 +1091,7 @@ static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
>> static void vlv_set_power_well(struct drm_i915_private *dev_priv,
>> struct i915_power_well *power_well, bool enable)
>> {
>> - enum punit_power_well power_well_id = power_well->id;
>> + enum i915_power_well_id power_well_id = power_well->id;
>> u32 mask;
>> u32 state;
>> u32 ctrl;
>> @@ -1137,7 +1139,7 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
>> static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
>> struct i915_power_well *power_well)
>> {
>> - int power_well_id = power_well->id;
>> + enum i915_power_well_id power_well_id = power_well->id;
>> bool enabled = false;
>> u32 mask;
>> u32 state;
>> @@ -1324,8 +1326,9 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
>>
>> #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
>>
>> -static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
>> - int power_well_id)
>> +static struct i915_power_well *
>> +lookup_power_well(struct drm_i915_private *dev_priv,
>> + enum i915_power_well_id power_well_id)
>> {
>> struct i915_power_domains *power_domains = &dev_priv->power_domains;
>> int i;
>> @@ -2117,7 +2120,7 @@ static struct i915_power_well vlv_power_wells[] = {
>> .always_on = 1,
>> .domains = POWER_DOMAIN_MASK,
>> .ops = &i9xx_always_on_power_well_ops,
>> - .id = PUNIT_POWER_WELL_ALWAYS_ON,
>> + .id = I915_DISP_PW_ALWAYS_ON,
>> },
>> {
>> .name = "display",
>> @@ -2202,7 +2205,7 @@ static struct i915_power_well chv_power_wells[] = {
>> };
>>
>> bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
>> - int power_well_id)
>> + enum i915_power_well_id power_well_id)
>> {
>> struct i915_power_well *power_well;
>> bool ret;
>> @@ -2219,7 +2222,7 @@ static struct i915_power_well skl_power_wells[] = {
>> .always_on = 1,
>> .domains = POWER_DOMAIN_MASK,
>> .ops = &i9xx_always_on_power_well_ops,
>> - .id = SKL_DISP_PW_ALWAYS_ON,
>> + .id = I915_DISP_PW_ALWAYS_ON,
>> },
>> {
>> .name = "power well 1",
>> --
>> 2.7.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 15/18] drm/i915/hsw+: Add has_fuses power well attribute
2017-07-11 17:05 ` Ville Syrjälä
@ 2017-07-11 17:22 ` Imre Deak
2017-07-11 17:37 ` Ville Syrjälä
0 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-11 17:22 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Jul 11, 2017 at 08:05:39PM +0300, Ville Syrjälä wrote:
> On Thu, Jul 06, 2017 at 05:40:37PM +0300, Imre Deak wrote:
> > The pattern of a power well backing a set of fuses whose initialization
> > we need to wait for during power well enabling is common to all GEN9+
> > platforms. Adding support for this to the HSW power well enable helper
> > allows us to use the HSW/BDW power well code for GEN9+ as well in a
> > follow-up patch.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/gvt/display.c | 6 +++---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 34 ++++++++++++++++++++++++++-------
> > 4 files changed, 35 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> > index 2deb05f..13599bb 100644
> > --- a/drivers/gpu/drm/i915/gvt/display.c
> > +++ b/drivers/gpu/drm/i915/gvt/display.c
> > @@ -178,9 +178,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
> > SDE_PORTE_HOTPLUG_SPT);
> > vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=
> > SKL_FUSE_DOWNLOAD_STATUS |
> > - SKL_FUSE_PG0_DIST_STATUS |
> > - SKL_FUSE_PG1_DIST_STATUS |
> > - SKL_FUSE_PG2_DIST_STATUS;
> > + SKL_FUSE_PG_DIST_STATUS(0) |
> > + SKL_FUSE_PG_DIST_STATUS(1) |
> > + SKL_FUSE_PG_DIST_STATUS(2);
> > vgpu_vreg(vgpu, LCPLL1_CTL) |=
> > LCPLL_PLL_ENABLE |
> > LCPLL_PLL_LOCK;
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index dc5ca5a..9e97536 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1396,6 +1396,7 @@ struct i915_power_well {
> > u32 irq_pipe_mask;
> > /* The pw is backing the VGA functionality */
> > bool has_vga:1;
> > + bool has_fuses:1;
> > } hsw;
> > };
> > const struct i915_power_well_ops *ops;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 845f50c..794d65c 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8023,10 +8023,10 @@ enum {
> >
> > /* SKL Fuse Status */
> > #define SKL_FUSE_STATUS _MMIO(0x42000)
> > -#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
> > -#define SKL_FUSE_PG0_DIST_STATUS (1<<27)
> > -#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
> > -#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
> > +#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
> > +/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */
> > +#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + 1)
> > +#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
> >
> > /* Per-pipe DDI Function Control */
> > #define _TRANS_DDI_FUNC_CTL_A 0x60400
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 14d4ff4..c204be0 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -400,16 +400,36 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
> > !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
> > }
> >
> > +static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
> > + int pg)
> > +{
> > + /* Timeout 5us for PG#0, for other PGs 1us */
> > + WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS,
> > + SKL_FUSE_PG_DIST_STATUS(pg),
> > + SKL_FUSE_PG_DIST_STATUS(pg), 1));
> > +}
> > +
> > static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> > struct i915_power_well *power_well)
> > {
> > enum i915_power_well_id id = power_well->id;
> > + bool wait_fuses = power_well->hsw.has_fuses;
> > + int pg;
> > u32 val;
> >
> > + if (wait_fuses) {
> > + pg = SKL_PW_TO_PG(id);
> > + if (pg == 1)
> > + gen9_wait_for_power_well_fuses(dev_priv, pg - 1);
> > + }
>
> This part looks magicy. The macro adds 1, but here you have to subtract
> 1 when feeding it the value, which seems odd.
That one maps PG1 to PW1, PG2 to PW2 etc.
> And apparently 1 is somehow special, but I can't tell why.
For power well 1 we need to wait both for fuses in PG#0 before enabling
and fuses in PG#1 after enabling the power well. For all other power
wells we only need to wait for the fuses in the corresponding PG after
enabling. I could add a comment to clarify this.
>
> > +
> > val = I915_READ(HSW_PWR_WELL_DRIVER);
> > I915_WRITE(HSW_PWR_WELL_DRIVER, val | HSW_PWR_WELL_CTL_REQ(id));
> > hsw_wait_for_power_well_enable(dev_priv, power_well);
> >
> > + if (wait_fuses)
> > + gen9_wait_for_power_well_fuses(dev_priv, pg);
> > +
> > hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
> > power_well->hsw.has_vga);
> > }
> > @@ -810,15 +830,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> > case SKL_DISP_PW_1:
> > if (intel_wait_for_register(dev_priv,
> > SKL_FUSE_STATUS,
> > - SKL_FUSE_PG0_DIST_STATUS,
> > - SKL_FUSE_PG0_DIST_STATUS,
> > + SKL_FUSE_PG_DIST_STATUS(0),
> > + SKL_FUSE_PG_DIST_STATUS(0),
> > 1)) {
> > DRM_ERROR("PG0 not enabled\n");
> > return;
> > }
> > break;
> > case SKL_DISP_PW_2:
> > - if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
> > + if (!(fuse_status & SKL_FUSE_PG_DIST_STATUS(1))) {
> > DRM_ERROR("PG1 in disabled state\n");
> > return;
> > }
> > @@ -863,15 +883,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> > if (power_well->id == SKL_DISP_PW_1) {
> > if (intel_wait_for_register(dev_priv,
> > SKL_FUSE_STATUS,
> > - SKL_FUSE_PG1_DIST_STATUS,
> > - SKL_FUSE_PG1_DIST_STATUS,
> > + SKL_FUSE_PG_DIST_STATUS(1),
> > + SKL_FUSE_PG_DIST_STATUS(1),
> > 1))
> > DRM_ERROR("PG1 distributing status timeout\n");
> > } else if (power_well->id == SKL_DISP_PW_2) {
> > if (intel_wait_for_register(dev_priv,
> > SKL_FUSE_STATUS,
> > - SKL_FUSE_PG2_DIST_STATUS,
> > - SKL_FUSE_PG2_DIST_STATUS,
> > + SKL_FUSE_PG_DIST_STATUS(2),
> > + SKL_FUSE_PG_DIST_STATUS(2),
> > 1))
> > DRM_ERROR("PG2 distributing status timeout\n");
> > }
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 02/18] drm/i915: Unify power well ID enums
2017-07-11 17:21 ` Rodrigo Vivi
@ 2017-07-11 17:36 ` Imre Deak
0 siblings, 0 replies; 64+ messages in thread
From: Imre Deak @ 2017-07-11 17:36 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Jul 11, 2017 at 10:21:55AM -0700, Rodrigo Vivi wrote:
> On Tue, Jul 11, 2017 at 9:43 AM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> > On Thu, Jul 6, 2017 at 7:40 AM, Imre Deak <imre.deak@intel.com> wrote:
> >> Atm, the power well IDs are defined in separate platform specific enums,
> >> which isn't ideal for the following reasons:
> >> - the IDs are used by helpers like lookup_power_well() in a platform
> >> independent way
> >> - the always-on power well is used by multiple platforms and so needs
> >> now separate IDs, although these IDs refer to the same thing
> >
> > I liked the always-on unifying... so much that I believe it deserved
> > a separated patch.
> >
> >>
> >> To make things more consistent use a single enum instead of the two
> >> separate ones, listing the IDs per platform (or set of very similar
> >> platforms like all GEN9/10). Replace the separate always-on power
> >> well IDs with a single ID.
> >>
> >> While at it also add a note clarifying the distinction between regular
> >> power wells that follow a common programming pattern and custom ones
> >> that are programmed in some other way. The IDs for regular power wells
> >> need to stay fixed, since they also define the request and state HW flag
> >> positions in their corresponding power well control register(s).
> >>
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Signed-off-by: Imre Deak <imre.deak@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> >> drivers/gpu/drm/i915/i915_reg.h | 41 ++++++++++++++++++++++-----------
> >> drivers/gpu/drm/i915/intel_runtime_pm.c | 29 ++++++++++++-----------
> >> 3 files changed, 44 insertions(+), 28 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index 81cd21e..c9b98ed 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -1382,7 +1382,7 @@ struct i915_power_well {
> >> bool hw_enabled;
> >> u64 domains;
> >> /* unique identifier for this power well */
> >> - unsigned long id;
> >> + enum i915_power_well_id id;
> >> /*
> >> * Arbitraty data associated with this power well. Platform and power
> >> * well specific.
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 3f7beff..e4135bd 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -1063,9 +1063,19 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >> #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
> >> #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
> >>
> >> -/* See the PUNIT HAS v0.8 for the below bits */
> >> -enum punit_power_well {
> >> - /* These numbers are fixed and must match the position of the pw bits */
> >> +/**
> >> + * i915_power_well_id:
> >> + *
> >> + * Platform specific IDs used to look up power wells and - except for custom
> >> + * power wells - to define request/status register flag bit positions. As such
> >> + * the set of IDs on a given platform must be unique and except for custom
> >> + * power wells their value must stay fixed.
>
> Actually I have one request here.
>
> Could you please add a comment that state bit is id*2 and req is id*2+1?
>
> Before your series this definition was right below, but with your
> series applied it takes me a few extra steps to remember where it was
> defined to check that HSW/BDW id 15...
That's different on VLV/CHV and HSW+. I added the actual registers below
where the mapping is described, but can copy that info to here as well.
>
> >> + */
> >> +enum i915_power_well_id {
> >> + /*
> >> + * VLV/CHV
> >> + * - PUNIT_REG_PWRGT_CTRL, PUNIT_REG_PWRGT_STATUS (PUNIT HAS v0.8)
> >> + */
> >> PUNIT_POWER_WELL_RENDER = 0,
> >> PUNIT_POWER_WELL_MEDIA = 1,
> >> PUNIT_POWER_WELL_DISP2D = 3,
> >> @@ -1080,13 +1090,11 @@ enum punit_power_well {
> >> /* - custom power well */
> >> CHV_DISP_PW_PIPE_A, /* 13 */
> >>
> >> - /* Not actual bit groups. Used as IDs for lookup_power_well() */
> >> - PUNIT_POWER_WELL_ALWAYS_ON,
> >> -};
> >> -
> >> -enum skl_disp_power_wells {
> >> - /* These numbers are fixed and must match the position of the pw bits */
> >> - SKL_DISP_PW_MISC_IO,
> >> + /*
> >> + * GEN9+
> >> + * - HSW_PWR_WELL_DRIVER
> >> + */
> >> + SKL_DISP_PW_MISC_IO = 0,
> >> SKL_DISP_PW_DDI_A_E,
> >> GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
> >> CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
> >> @@ -1105,13 +1113,18 @@ enum skl_disp_power_wells {
> >> SKL_DISP_PW_1 = 14,
> >> SKL_DISP_PW_2,
> >>
> >> - /* Not actual bit groups. Used as IDs for lookup_power_well() */
> >> - SKL_DISP_PW_ALWAYS_ON,
> >> + /* - custom power wells */
> >> SKL_DISP_PW_DC_OFF,
> >> -
> >> BXT_DPIO_CMN_A,
> >> BXT_DPIO_CMN_BC,
> >> - GLK_DPIO_CMN_C,
> >> + GLK_DPIO_CMN_C, /* 19 */
> >> +
> >> + /*
> >> + * Multiple platforms.
> >> + * Must start following the highest ID of any platform.
> >> + * - custom power wells
> >> + */
> >> + I915_DISP_PW_ALWAYS_ON = 20,
> >
> > What about just leaving
> > I915_DISP_PW_ALWAYS_ON,
> >
> > I have the feeling that if that increases we will forget to update here....
> >
> > but I will leave you to decide... so, with or without any split or
> > change feel free to use:
> >
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >
> >> };
> >>
> >> #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
> >> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> >> index 5f5dee4..ad314c1 100644
> >> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> >> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> >> @@ -50,10 +50,11 @@
> >> */
> >>
> >> bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
> >> - int power_well_id);
> >> + enum i915_power_well_id power_well_id);
> >>
> >> static struct i915_power_well *
> >> -lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id);
> >> +lookup_power_well(struct drm_i915_private *dev_priv,
> >> + enum i915_power_well_id power_well_id);
> >>
> >> const char *
> >> intel_display_power_domain_str(enum intel_display_power_domain domain)
> >> @@ -344,7 +345,7 @@ static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
> >> static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
> >> struct i915_power_well *power_well)
> >> {
> >> - int id = power_well->id;
> >> + enum i915_power_well_id id = power_well->id;
> >>
> >> /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
> >> WARN_ON(intel_wait_for_register(dev_priv,
> >> @@ -354,7 +355,8 @@ static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
> >> 1));
> >> }
> >>
> >> -static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, int id)
> >> +static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv,
> >> + enum i915_power_well_id id)
> >> {
> >> u32 req_mask = SKL_POWER_WELL_REQ(id);
> >> u32 ret;
> >> @@ -370,7 +372,7 @@ static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, int id)
> >> static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
> >> struct i915_power_well *power_well)
> >> {
> >> - int id = power_well->id;
> >> + enum i915_power_well_id id = power_well->id;
> >> bool disabled;
> >> u32 reqs;
> >>
> >> @@ -837,7 +839,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> >> case CNL_DISP_PW_AUX_D:
> >> break;
> >> default:
> >> - WARN(1, "Unknown power well %lu\n", power_well->id);
> >> + WARN(1, "Unknown power well %u\n", power_well->id);
> >> return;
> >> }
> >>
> >> @@ -1089,7 +1091,7 @@ static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
> >> static void vlv_set_power_well(struct drm_i915_private *dev_priv,
> >> struct i915_power_well *power_well, bool enable)
> >> {
> >> - enum punit_power_well power_well_id = power_well->id;
> >> + enum i915_power_well_id power_well_id = power_well->id;
> >> u32 mask;
> >> u32 state;
> >> u32 ctrl;
> >> @@ -1137,7 +1139,7 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
> >> static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
> >> struct i915_power_well *power_well)
> >> {
> >> - int power_well_id = power_well->id;
> >> + enum i915_power_well_id power_well_id = power_well->id;
> >> bool enabled = false;
> >> u32 mask;
> >> u32 state;
> >> @@ -1324,8 +1326,9 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
> >>
> >> #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
> >>
> >> -static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
> >> - int power_well_id)
> >> +static struct i915_power_well *
> >> +lookup_power_well(struct drm_i915_private *dev_priv,
> >> + enum i915_power_well_id power_well_id)
> >> {
> >> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> >> int i;
> >> @@ -2117,7 +2120,7 @@ static struct i915_power_well vlv_power_wells[] = {
> >> .always_on = 1,
> >> .domains = POWER_DOMAIN_MASK,
> >> .ops = &i9xx_always_on_power_well_ops,
> >> - .id = PUNIT_POWER_WELL_ALWAYS_ON,
> >> + .id = I915_DISP_PW_ALWAYS_ON,
> >> },
> >> {
> >> .name = "display",
> >> @@ -2202,7 +2205,7 @@ static struct i915_power_well chv_power_wells[] = {
> >> };
> >>
> >> bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
> >> - int power_well_id)
> >> + enum i915_power_well_id power_well_id)
> >> {
> >> struct i915_power_well *power_well;
> >> bool ret;
> >> @@ -2219,7 +2222,7 @@ static struct i915_power_well skl_power_wells[] = {
> >> .always_on = 1,
> >> .domains = POWER_DOMAIN_MASK,
> >> .ops = &i9xx_always_on_power_well_ops,
> >> - .id = SKL_DISP_PW_ALWAYS_ON,
> >> + .id = I915_DISP_PW_ALWAYS_ON,
> >> },
> >> {
> >> .name = "power well 1",
> >> --
> >> 2.7.4
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >
> >
> > --
> > Rodrigo Vivi
> > Blog: http://blog.vivi.eng.br
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 15/18] drm/i915/hsw+: Add has_fuses power well attribute
2017-07-11 17:22 ` Imre Deak
@ 2017-07-11 17:37 ` Ville Syrjälä
2017-07-11 17:49 ` Imre Deak
0 siblings, 1 reply; 64+ messages in thread
From: Ville Syrjälä @ 2017-07-11 17:37 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, Jul 11, 2017 at 08:22:19PM +0300, Imre Deak wrote:
> On Tue, Jul 11, 2017 at 08:05:39PM +0300, Ville Syrjälä wrote:
> > On Thu, Jul 06, 2017 at 05:40:37PM +0300, Imre Deak wrote:
> > > The pattern of a power well backing a set of fuses whose initialization
> > > we need to wait for during power well enabling is common to all GEN9+
> > > platforms. Adding support for this to the HSW power well enable helper
> > > allows us to use the HSW/BDW power well code for GEN9+ as well in a
> > > follow-up patch.
> > >
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gvt/display.c | 6 +++---
> > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 34 ++++++++++++++++++++++++++-------
> > > 4 files changed, 35 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> > > index 2deb05f..13599bb 100644
> > > --- a/drivers/gpu/drm/i915/gvt/display.c
> > > +++ b/drivers/gpu/drm/i915/gvt/display.c
> > > @@ -178,9 +178,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
> > > SDE_PORTE_HOTPLUG_SPT);
> > > vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=
> > > SKL_FUSE_DOWNLOAD_STATUS |
> > > - SKL_FUSE_PG0_DIST_STATUS |
> > > - SKL_FUSE_PG1_DIST_STATUS |
> > > - SKL_FUSE_PG2_DIST_STATUS;
> > > + SKL_FUSE_PG_DIST_STATUS(0) |
> > > + SKL_FUSE_PG_DIST_STATUS(1) |
> > > + SKL_FUSE_PG_DIST_STATUS(2);
> > > vgpu_vreg(vgpu, LCPLL1_CTL) |=
> > > LCPLL_PLL_ENABLE |
> > > LCPLL_PLL_LOCK;
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index dc5ca5a..9e97536 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1396,6 +1396,7 @@ struct i915_power_well {
> > > u32 irq_pipe_mask;
> > > /* The pw is backing the VGA functionality */
> > > bool has_vga:1;
> > > + bool has_fuses:1;
> > > } hsw;
> > > };
> > > const struct i915_power_well_ops *ops;
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 845f50c..794d65c 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -8023,10 +8023,10 @@ enum {
> > >
> > > /* SKL Fuse Status */
> > > #define SKL_FUSE_STATUS _MMIO(0x42000)
> > > -#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
> > > -#define SKL_FUSE_PG0_DIST_STATUS (1<<27)
> > > -#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
> > > -#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
> > > +#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
> > > +/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */
> > > +#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + 1)
> > > +#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
> > >
> > > /* Per-pipe DDI Function Control */
> > > #define _TRANS_DDI_FUNC_CTL_A 0x60400
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 14d4ff4..c204be0 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -400,16 +400,36 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
> > > !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
> > > }
> > >
> > > +static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
> > > + int pg)
> > > +{
> > > + /* Timeout 5us for PG#0, for other PGs 1us */
> > > + WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS,
> > > + SKL_FUSE_PG_DIST_STATUS(pg),
> > > + SKL_FUSE_PG_DIST_STATUS(pg), 1));
> > > +}
> > > +
> > > static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> > > struct i915_power_well *power_well)
> > > {
> > > enum i915_power_well_id id = power_well->id;
> > > + bool wait_fuses = power_well->hsw.has_fuses;
> > > + int pg;
> > > u32 val;
> > >
> > > + if (wait_fuses) {
> > > + pg = SKL_PW_TO_PG(id);
> > > + if (pg == 1)
> > > + gen9_wait_for_power_well_fuses(dev_priv, pg - 1);
> > > + }
> >
> > This part looks magicy. The macro adds 1, but here you have to subtract
> > 1 when feeding it the value, which seems odd.
>
> That one maps PG1 to PW1, PG2 to PW2 etc.
Would be perhaps better to replace the raw numbers with a PG enum or
something. Or maybe just pass around the power well IDs instead and
keep the PG numbers hidden from view.
>
> > And apparently 1 is somehow special, but I can't tell why.
>
> For power well 1 we need to wait both for fuses in PG#0 before enabling
> and fuses in PG#1 after enabling the power well. For all other power
> wells we only need to wait for the fuses in the corresponding PG after
> enabling. I could add a comment to clarify this.
>
> >
> > > +
> > > val = I915_READ(HSW_PWR_WELL_DRIVER);
> > > I915_WRITE(HSW_PWR_WELL_DRIVER, val | HSW_PWR_WELL_CTL_REQ(id));
> > > hsw_wait_for_power_well_enable(dev_priv, power_well);
> > >
> > > + if (wait_fuses)
> > > + gen9_wait_for_power_well_fuses(dev_priv, pg);
> > > +
> > > hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
> > > power_well->hsw.has_vga);
> > > }
> > > @@ -810,15 +830,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> > > case SKL_DISP_PW_1:
> > > if (intel_wait_for_register(dev_priv,
> > > SKL_FUSE_STATUS,
> > > - SKL_FUSE_PG0_DIST_STATUS,
> > > - SKL_FUSE_PG0_DIST_STATUS,
> > > + SKL_FUSE_PG_DIST_STATUS(0),
> > > + SKL_FUSE_PG_DIST_STATUS(0),
> > > 1)) {
> > > DRM_ERROR("PG0 not enabled\n");
> > > return;
> > > }
> > > break;
> > > case SKL_DISP_PW_2:
> > > - if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
> > > + if (!(fuse_status & SKL_FUSE_PG_DIST_STATUS(1))) {
> > > DRM_ERROR("PG1 in disabled state\n");
> > > return;
> > > }
> > > @@ -863,15 +883,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> > > if (power_well->id == SKL_DISP_PW_1) {
> > > if (intel_wait_for_register(dev_priv,
> > > SKL_FUSE_STATUS,
> > > - SKL_FUSE_PG1_DIST_STATUS,
> > > - SKL_FUSE_PG1_DIST_STATUS,
> > > + SKL_FUSE_PG_DIST_STATUS(1),
> > > + SKL_FUSE_PG_DIST_STATUS(1),
> > > 1))
> > > DRM_ERROR("PG1 distributing status timeout\n");
> > > } else if (power_well->id == SKL_DISP_PW_2) {
> > > if (intel_wait_for_register(dev_priv,
> > > SKL_FUSE_STATUS,
> > > - SKL_FUSE_PG2_DIST_STATUS,
> > > - SKL_FUSE_PG2_DIST_STATUS,
> > > + SKL_FUSE_PG_DIST_STATUS(2),
> > > + SKL_FUSE_PG_DIST_STATUS(2),
> > > 1))
> > > DRM_ERROR("PG2 distributing status timeout\n");
> > > }
> > > --
> > > 2.7.4
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel OTC
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 15/18] drm/i915/hsw+: Add has_fuses power well attribute
2017-07-11 17:37 ` Ville Syrjälä
@ 2017-07-11 17:49 ` Imre Deak
0 siblings, 0 replies; 64+ messages in thread
From: Imre Deak @ 2017-07-11 17:49 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Jul 11, 2017 at 08:37:24PM +0300, Ville Syrjälä wrote:
> On Tue, Jul 11, 2017 at 08:22:19PM +0300, Imre Deak wrote:
> > On Tue, Jul 11, 2017 at 08:05:39PM +0300, Ville Syrjälä wrote:
> > > On Thu, Jul 06, 2017 at 05:40:37PM +0300, Imre Deak wrote:
> > > > The pattern of a power well backing a set of fuses whose initialization
> > > > we need to wait for during power well enabling is common to all GEN9+
> > > > platforms. Adding support for this to the HSW power well enable helper
> > > > allows us to use the HSW/BDW power well code for GEN9+ as well in a
> > > > follow-up patch.
> > > >
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/gvt/display.c | 6 +++---
> > > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > > drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
> > > > drivers/gpu/drm/i915/intel_runtime_pm.c | 34 ++++++++++++++++++++++++++-------
> > > > 4 files changed, 35 insertions(+), 14 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> > > > index 2deb05f..13599bb 100644
> > > > --- a/drivers/gpu/drm/i915/gvt/display.c
> > > > +++ b/drivers/gpu/drm/i915/gvt/display.c
> > > > @@ -178,9 +178,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
> > > > SDE_PORTE_HOTPLUG_SPT);
> > > > vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=
> > > > SKL_FUSE_DOWNLOAD_STATUS |
> > > > - SKL_FUSE_PG0_DIST_STATUS |
> > > > - SKL_FUSE_PG1_DIST_STATUS |
> > > > - SKL_FUSE_PG2_DIST_STATUS;
> > > > + SKL_FUSE_PG_DIST_STATUS(0) |
> > > > + SKL_FUSE_PG_DIST_STATUS(1) |
> > > > + SKL_FUSE_PG_DIST_STATUS(2);
> > > > vgpu_vreg(vgpu, LCPLL1_CTL) |=
> > > > LCPLL_PLL_ENABLE |
> > > > LCPLL_PLL_LOCK;
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > > index dc5ca5a..9e97536 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > @@ -1396,6 +1396,7 @@ struct i915_power_well {
> > > > u32 irq_pipe_mask;
> > > > /* The pw is backing the VGA functionality */
> > > > bool has_vga:1;
> > > > + bool has_fuses:1;
> > > > } hsw;
> > > > };
> > > > const struct i915_power_well_ops *ops;
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 845f50c..794d65c 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -8023,10 +8023,10 @@ enum {
> > > >
> > > > /* SKL Fuse Status */
> > > > #define SKL_FUSE_STATUS _MMIO(0x42000)
> > > > -#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
> > > > -#define SKL_FUSE_PG0_DIST_STATUS (1<<27)
> > > > -#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
> > > > -#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
> > > > +#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
> > > > +/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */
> > > > +#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + 1)
> > > > +#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
> > > >
> > > > /* Per-pipe DDI Function Control */
> > > > #define _TRANS_DDI_FUNC_CTL_A 0x60400
> > > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > index 14d4ff4..c204be0 100644
> > > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > @@ -400,16 +400,36 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
> > > > !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
> > > > }
> > > >
> > > > +static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
> > > > + int pg)
> > > > +{
> > > > + /* Timeout 5us for PG#0, for other PGs 1us */
> > > > + WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS,
> > > > + SKL_FUSE_PG_DIST_STATUS(pg),
> > > > + SKL_FUSE_PG_DIST_STATUS(pg), 1));
> > > > +}
> > > > +
> > > > static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> > > > struct i915_power_well *power_well)
> > > > {
> > > > enum i915_power_well_id id = power_well->id;
> > > > + bool wait_fuses = power_well->hsw.has_fuses;
> > > > + int pg;
> > > > u32 val;
> > > >
> > > > + if (wait_fuses) {
> > > > + pg = SKL_PW_TO_PG(id);
> > > > + if (pg == 1)
> > > > + gen9_wait_for_power_well_fuses(dev_priv, pg - 1);
> > > > + }
> > >
> > > This part looks magicy. The macro adds 1, but here you have to subtract
> > > 1 when feeding it the value, which seems odd.
> >
> > That one maps PG1 to PW1, PG2 to PW2 etc.
>
> Would be perhaps better to replace the raw numbers with a PG enum or
> something. Or maybe just pass around the power well IDs instead and
> keep the PG numbers hidden from view.
Ok, can add an enum instead. Not sure about passing power well IDs;
since PW#0/PG#0 is handled by the HW we don't have an ID for it, but we
still need to refer to it somehow here.
>
> >
> > > And apparently 1 is somehow special, but I can't tell why.
> >
> > For power well 1 we need to wait both for fuses in PG#0 before enabling
> > and fuses in PG#1 after enabling the power well. For all other power
> > wells we only need to wait for the fuses in the corresponding PG after
> > enabling. I could add a comment to clarify this.
> >
> > >
> > > > +
> > > > val = I915_READ(HSW_PWR_WELL_DRIVER);
> > > > I915_WRITE(HSW_PWR_WELL_DRIVER, val | HSW_PWR_WELL_CTL_REQ(id));
> > > > hsw_wait_for_power_well_enable(dev_priv, power_well);
> > > >
> > > > + if (wait_fuses)
> > > > + gen9_wait_for_power_well_fuses(dev_priv, pg);
> > > > +
> > > > hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
> > > > power_well->hsw.has_vga);
> > > > }
> > > > @@ -810,15 +830,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> > > > case SKL_DISP_PW_1:
> > > > if (intel_wait_for_register(dev_priv,
> > > > SKL_FUSE_STATUS,
> > > > - SKL_FUSE_PG0_DIST_STATUS,
> > > > - SKL_FUSE_PG0_DIST_STATUS,
> > > > + SKL_FUSE_PG_DIST_STATUS(0),
> > > > + SKL_FUSE_PG_DIST_STATUS(0),
> > > > 1)) {
> > > > DRM_ERROR("PG0 not enabled\n");
> > > > return;
> > > > }
> > > > break;
> > > > case SKL_DISP_PW_2:
> > > > - if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
> > > > + if (!(fuse_status & SKL_FUSE_PG_DIST_STATUS(1))) {
> > > > DRM_ERROR("PG1 in disabled state\n");
> > > > return;
> > > > }
> > > > @@ -863,15 +883,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> > > > if (power_well->id == SKL_DISP_PW_1) {
> > > > if (intel_wait_for_register(dev_priv,
> > > > SKL_FUSE_STATUS,
> > > > - SKL_FUSE_PG1_DIST_STATUS,
> > > > - SKL_FUSE_PG1_DIST_STATUS,
> > > > + SKL_FUSE_PG_DIST_STATUS(1),
> > > > + SKL_FUSE_PG_DIST_STATUS(1),
> > > > 1))
> > > > DRM_ERROR("PG1 distributing status timeout\n");
> > > > } else if (power_well->id == SKL_DISP_PW_2) {
> > > > if (intel_wait_for_register(dev_priv,
> > > > SKL_FUSE_STATUS,
> > > > - SKL_FUSE_PG2_DIST_STATUS,
> > > > - SKL_FUSE_PG2_DIST_STATUS,
> > > > + SKL_FUSE_PG_DIST_STATUS(2),
> > > > + SKL_FUSE_PG_DIST_STATUS(2),
> > > > 1))
> > > > DRM_ERROR("PG2 distributing status timeout\n");
> > > > }
> > > > --
> > > > 2.7.4
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
> > > --
> > > Ville Syrjälä
> > > Intel OTC
>
> --
> Ville Syrjälä
> Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v2 02/18] drm/i915: Unify power well ID enums
2017-07-06 14:40 ` [PATCH 02/18] drm/i915: Unify power well ID enums Imre Deak
2017-07-11 16:43 ` Rodrigo Vivi
@ 2017-07-11 20:42 ` Imre Deak
1 sibling, 0 replies; 64+ messages in thread
From: Imre Deak @ 2017-07-11 20:42 UTC (permalink / raw)
To: intel-gfx
Atm, the power well IDs are defined in separate platform specific enums,
which isn't ideal for the following reasons:
- the IDs are used by helpers like lookup_power_well() in a platform
independent way
- the always-on power well is used by multiple platforms and so needs
now separate IDs, although these IDs refer to the same thing
To make things more consistent use a single enum instead of the two
separate ones, listing the IDs per platform (or set of very similar
platforms like all GEN9/10). Replace the separate always-on power
well IDs with a single ID.
While at it also add a note clarifying the distinction between regular
power wells that follow a common programming pattern and custom ones
that are programmed in some other way. The IDs for regular power wells
need to stay fixed, since they also define the request and state HW flag
positions in their corresponding power well control register(s).
v2:
- Add comment about id to req,status bit mapping to the enum. (Rodrigo)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 42 ++++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_runtime_pm.c | 29 +++++++++++++----------
3 files changed, 45 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 81cd21ecfa7d..c9b98edb9f40 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1382,7 +1382,7 @@ struct i915_power_well {
bool hw_enabled;
u64 domains;
/* unique identifier for this power well */
- unsigned long id;
+ enum i915_power_well_id id;
/*
* Arbitraty data associated with this power well. Platform and power
* well specific.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f7beff3d3c5..910fd414f18a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1063,9 +1063,20 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
-/* See the PUNIT HAS v0.8 for the below bits */
-enum punit_power_well {
- /* These numbers are fixed and must match the position of the pw bits */
+/**
+ * i915_power_well_id:
+ *
+ * Platform specific IDs used to look up power wells and - except for custom
+ * power wells - to define request/status register flag bit positions. As such
+ * the set of IDs on a given platform must be unique and except for custom
+ * power wells their value must stay fixed.
+ */
+enum i915_power_well_id {
+ /*
+ * VLV/CHV
+ * - PUNIT_REG_PWRGT_CTRL (bit: id*2),
+ * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8)
+ */
PUNIT_POWER_WELL_RENDER = 0,
PUNIT_POWER_WELL_MEDIA = 1,
PUNIT_POWER_WELL_DISP2D = 3,
@@ -1080,13 +1091,11 @@ enum punit_power_well {
/* - custom power well */
CHV_DISP_PW_PIPE_A, /* 13 */
- /* Not actual bit groups. Used as IDs for lookup_power_well() */
- PUNIT_POWER_WELL_ALWAYS_ON,
-};
-
-enum skl_disp_power_wells {
- /* These numbers are fixed and must match the position of the pw bits */
- SKL_DISP_PW_MISC_IO,
+ /*
+ * GEN9+
+ * - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1)
+ */
+ SKL_DISP_PW_MISC_IO = 0,
SKL_DISP_PW_DDI_A_E,
GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
@@ -1105,13 +1114,18 @@ enum skl_disp_power_wells {
SKL_DISP_PW_1 = 14,
SKL_DISP_PW_2,
- /* Not actual bit groups. Used as IDs for lookup_power_well() */
- SKL_DISP_PW_ALWAYS_ON,
+ /* - custom power wells */
SKL_DISP_PW_DC_OFF,
-
BXT_DPIO_CMN_A,
BXT_DPIO_CMN_BC,
- GLK_DPIO_CMN_C,
+ GLK_DPIO_CMN_C, /* 19 */
+
+ /*
+ * Multiple platforms.
+ * Must start following the highest ID of any platform.
+ * - custom power wells
+ */
+ I915_DISP_PW_ALWAYS_ON = 20,
};
#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5f5dee4beb72..ad314c1fa61d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -50,10 +50,11 @@
*/
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
- int power_well_id);
+ enum i915_power_well_id power_well_id);
static struct i915_power_well *
-lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id);
+lookup_power_well(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id);
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain)
@@ -344,7 +345,7 @@ static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- int id = power_well->id;
+ enum i915_power_well_id id = power_well->id;
/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
WARN_ON(intel_wait_for_register(dev_priv,
@@ -354,7 +355,8 @@ static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
1));
}
-static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, int id)
+static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id id)
{
u32 req_mask = SKL_POWER_WELL_REQ(id);
u32 ret;
@@ -370,7 +372,7 @@ static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, int id)
static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- int id = power_well->id;
+ enum i915_power_well_id id = power_well->id;
bool disabled;
u32 reqs;
@@ -837,7 +839,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
case CNL_DISP_PW_AUX_D:
break;
default:
- WARN(1, "Unknown power well %lu\n", power_well->id);
+ WARN(1, "Unknown power well %u\n", power_well->id);
return;
}
@@ -1089,7 +1091,7 @@ static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
static void vlv_set_power_well(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well, bool enable)
{
- enum punit_power_well power_well_id = power_well->id;
+ enum i915_power_well_id power_well_id = power_well->id;
u32 mask;
u32 state;
u32 ctrl;
@@ -1137,7 +1139,7 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- int power_well_id = power_well->id;
+ enum i915_power_well_id power_well_id = power_well->id;
bool enabled = false;
u32 mask;
u32 state;
@@ -1324,8 +1326,9 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
-static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
- int power_well_id)
+static struct i915_power_well *
+lookup_power_well(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
int i;
@@ -2117,7 +2120,7 @@ static struct i915_power_well vlv_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = PUNIT_POWER_WELL_ALWAYS_ON,
+ .id = I915_DISP_PW_ALWAYS_ON,
},
{
.name = "display",
@@ -2202,7 +2205,7 @@ static struct i915_power_well chv_power_wells[] = {
};
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
- int power_well_id)
+ enum i915_power_well_id power_well_id)
{
struct i915_power_well *power_well;
bool ret;
@@ -2219,7 +2222,7 @@ static struct i915_power_well skl_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = SKL_DISP_PW_ALWAYS_ON,
+ .id = I915_DISP_PW_ALWAYS_ON,
},
{
.name = "power well 1",
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v2 04/18] drm/i915/gen2: Add an ID for the display pipes power well
2017-07-06 14:40 ` [PATCH 04/18] drm/i915/gen2: Add an ID for the display pipes power well Imre Deak
2017-07-11 16:50 ` Rodrigo Vivi
2017-07-11 17:01 ` Ville Syrjälä
@ 2017-07-11 20:42 ` Imre Deak
2 siblings, 0 replies; 64+ messages in thread
From: Imre Deak @ 2017-07-11 20:42 UTC (permalink / raw)
To: intel-gfx
Make the I830 power well ID assignment explicit for consistency.
v2:
- s/GEN2/I830/ in the comment, since other GEN2s don't have the power
well. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (v1)
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 910fd414f18a..f9b232e22050 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1073,6 +1073,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
*/
enum i915_power_well_id {
/*
+ * I830
+ * - custom power well
+ */
+ I830_DISP_PW_PIPES = 0,
+
+ /*
* VLV/CHV
* - PUNIT_REG_PWRGT_CTRL (bit: id*2),
* PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 9601b623188c..4a9d95505f1b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2036,6 +2036,7 @@ static struct i915_power_well i830_power_wells[] = {
.name = "pipes",
.domains = I830_PIPES_POWER_DOMAINS,
.ops = &i830_pipes_power_well_ops,
+ .id = I830_DISP_PW_PIPES,
},
};
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v2 05/18] drm/i915/hsw, bdw: Add an ID for the global display power well
2017-07-06 14:40 ` [PATCH 05/18] drm/i915/hsw, bdw: Add an ID for the global display " Imre Deak
2017-07-11 17:08 ` Rodrigo Vivi
@ 2017-07-11 20:42 ` Imre Deak
1 sibling, 0 replies; 64+ messages in thread
From: Imre Deak @ 2017-07-11 20:42 UTC (permalink / raw)
To: intel-gfx
Add an ID for the HSW/BDW global display power well for consistency. The
ID is selected so that it can be used to get at the HW request and
status flags with the corresponding GEN9+ macros. Unifying the HSW/BDW
and GEN9+ versions of these macros and the power well ops using them
will be done in follow-up patches.
v2:
- Rebased on v2 of patch 2.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f9b232e22050..77280da49fba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1098,6 +1098,12 @@ enum i915_power_well_id {
CHV_DISP_PW_PIPE_A, /* 13 */
/*
+ * HSW/BDW
+ * - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1)
+ */
+ HSW_DISP_PW_GLOBAL = 15,
+
+ /*
* GEN9+
* - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1)
*/
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4a9d95505f1b..27c69f9e9df9 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2080,6 +2080,7 @@ static struct i915_power_well hsw_power_wells[] = {
.name = "display",
.domains = HSW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .id = HSW_DISP_PW_GLOBAL,
},
};
@@ -2095,6 +2096,7 @@ static struct i915_power_well bdw_power_wells[] = {
.name = "display",
.domains = BDW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .id = HSW_DISP_PW_GLOBAL,
},
};
--
2.11.0
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^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v3 06/18] drm/i915: Check for duplicated power well IDs
2017-07-06 14:40 ` [PATCH 06/18] drm/i915: Check for duplicated power well IDs Imre Deak
2017-07-07 14:39 ` [PATCH v2 " Imre Deak
@ 2017-07-11 20:42 ` Imre Deak
2017-07-20 13:08 ` Arkadiusz Hiler
1 sibling, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-11 20:42 UTC (permalink / raw)
To: intel-gfx
Check that all the power well IDs are unique on the given platform.
v2:
- Fix using BIT_ULL() instead of BIT() for 64 bit mask.
v3:
- Move the check to a separate function. (Ville)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 27c69f9e9df9..aae21dc92797 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2548,6 +2548,22 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
return mask;
}
+static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv)
+{
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ u64 power_well_ids;
+ int i;
+
+ power_well_ids = 0;
+ for (i = 0; i < power_domains->power_well_count; i++) {
+ enum i915_power_well_id id = power_domains->power_wells[i].id;
+
+ WARN_ON(id >= sizeof(power_well_ids) * 8);
+ WARN_ON(power_well_ids & BIT_ULL(id));
+ power_well_ids |= BIT_ULL(id);
+ }
+}
+
#define set_power_wells(power_domains, __power_wells) ({ \
(power_domains)->power_wells = (__power_wells); \
(power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
@@ -2599,6 +2615,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
set_power_wells(power_domains, i9xx_always_on_power_well);
}
+ assert_power_well_ids_unique(dev_priv);
+
return 0;
}
--
2.11.0
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^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v2 13/18] drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes
2017-07-06 14:40 ` [PATCH 13/18] drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes Imre Deak
2017-07-11 17:02 ` Ville Syrjälä
@ 2017-07-11 20:42 ` Imre Deak
2017-07-12 15:54 ` [PATCH v3 " Imre Deak
2 siblings, 0 replies; 64+ messages in thread
From: Imre Deak @ 2017-07-11 20:42 UTC (permalink / raw)
To: intel-gfx
The pattern of a power well backing a set of pipe IRQ or VGA
functionality applies to all HSW+ platforms. Using power well attributes
instead of platform checks to decide whether to init/reset pipe IRQs and
VGA correspondingly is cleaner and it allows us to unify the HSW/BDW and
GEN9+ power well code in follow-up patches.
v2:
- Use u8 instead of u32 for irq_pipe_mask. (Ville)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 34 ++++++++++++++++++++-------------
2 files changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b27f2fcc0ad3..6f28fbe1de0f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1391,6 +1391,12 @@ struct i915_power_well {
struct {
enum dpio_phy phy;
} bxt;
+ struct {
+ /* Mask of pipes whose IRQ logic is backed by the pw */
+ u8 irq_pipe_mask;
+ /* The pw is backing the VGA functionality */
+ bool has_vga:1;
+ } hsw;
};
const struct i915_power_well_ops *ops;
};
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5143a7302d54..aac697dcb87b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -281,7 +281,8 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv,
* to be enabled, and it will only be disabled if none of the registers is
* requesting it to be enabled.
*/
-static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
+static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
+ u32 irq_pipe_mask, bool has_vga)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
@@ -295,20 +296,21 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
* sure vgacon can keep working normally without triggering interrupts
* and error messages.
*/
- vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
- outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
- vga_put(pdev, VGA_RSRC_LEGACY_IO);
+ if (has_vga) {
+ vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
+ outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
+ vga_put(pdev, VGA_RSRC_LEGACY_IO);
+ }
- if (IS_BROADWELL(dev_priv))
- gen8_irq_power_well_post_enable(dev_priv,
- 1 << PIPE_C | 1 << PIPE_B);
+ if (irq_pipe_mask)
+ gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
}
-static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
+static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
+ u32 irq_pipe_mask)
{
- if (IS_BROADWELL(dev_priv))
- gen8_irq_power_well_pre_disable(dev_priv,
- 1 << PIPE_C | 1 << PIPE_B);
+ if (irq_pipe_mask)
+ gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
}
static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -413,7 +415,9 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
HSW_PWR_WELL_CTL_STATE(id),
20))
DRM_ERROR("Timeout enabling power well\n");
- hsw_power_well_post_enable(dev_priv);
+
+ hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
+ power_well->hsw.has_vga);
}
static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
@@ -422,7 +426,8 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
enum i915_power_well_id id = power_well->id;
u32 val;
- hsw_power_well_pre_disable(dev_priv);
+ hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask);
+
val = I915_READ(HSW_PWR_WELL_DRIVER);
I915_WRITE(HSW_PWR_WELL_DRIVER, val & ~HSW_PWR_WELL_CTL_REQ(id));
POSTING_READ(HSW_PWR_WELL_DRIVER);
@@ -2057,6 +2062,7 @@ static struct i915_power_well hsw_power_wells[] = {
.domains = HSW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
+ .hsw.has_vga = true,
},
};
@@ -2073,6 +2079,8 @@ static struct i915_power_well bdw_power_wells[] = {
.domains = BDW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
},
};
--
2.11.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v2 15/18] drm/i915/hsw+: Add has_fuses power well attribute
2017-07-06 14:40 ` [PATCH 15/18] drm/i915/hsw+: Add has_fuses power well attribute Imre Deak
2017-07-11 17:05 ` Ville Syrjälä
@ 2017-07-11 20:42 ` Imre Deak
2017-07-21 13:10 ` Arkadiusz Hiler
1 sibling, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-11 20:42 UTC (permalink / raw)
To: intel-gfx
The pattern of a power well backing a set of fuses whose initialization
we need to wait for during power well enabling is common to all GEN9+
platforms. Adding support for this to the HSW power well enable helper
allows us to use the HSW/BDW power well code for GEN9+ as well in a
follow-up patch.
v2:
- Use an enum for power gates instead of raw numbers. (Ville)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/gvt/display.c | 6 ++---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 14 +++++++----
drivers/gpu/drm/i915/intel_runtime_pm.c | 41 +++++++++++++++++++++++++++------
4 files changed, 48 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 2deb05f618fb..24cc4b012e93 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -178,9 +178,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
SDE_PORTE_HOTPLUG_SPT);
vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=
SKL_FUSE_DOWNLOAD_STATUS |
- SKL_FUSE_PG0_DIST_STATUS |
- SKL_FUSE_PG1_DIST_STATUS |
- SKL_FUSE_PG2_DIST_STATUS;
+ SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
+ SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
+ SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
vgpu_vreg(vgpu, LCPLL1_CTL) |=
LCPLL_PLL_ENABLE |
LCPLL_PLL_LOCK;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6f28fbe1de0f..4c3e3ba30643 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1396,6 +1396,7 @@ struct i915_power_well {
u8 irq_pipe_mask;
/* The pw is backing the VGA functionality */
bool has_vga:1;
+ bool has_fuses:1;
} hsw;
};
const struct i915_power_well_ops *ops;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 72b37552e9fa..c0d868737834 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8023,11 +8023,17 @@ enum {
#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
/* SKL Fuse Status */
+enum skl_power_gate {
+ SKL_PG0,
+ SKL_PG1,
+ SKL_PG2,
+};
+
#define SKL_FUSE_STATUS _MMIO(0x42000)
-#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
-#define SKL_FUSE_PG0_DIST_STATUS (1<<27)
-#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
-#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
+#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
+/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */
+#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
+#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index cd7e0545d671..b473bd1028ff 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -400,16 +400,43 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
!!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
}
+static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
+ enum skl_power_gate pg)
+{
+ /* Timeout 5us for PG#0, for other PGs 1us */
+ WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS,
+ SKL_FUSE_PG_DIST_STATUS(pg),
+ SKL_FUSE_PG_DIST_STATUS(pg), 1));
+}
+
static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
enum i915_power_well_id id = power_well->id;
+ bool wait_fuses = power_well->hsw.has_fuses;
+ enum skl_power_gate pg;
u32 val;
+ if (wait_fuses) {
+ pg = SKL_PW_TO_PG(id);
+ /*
+ * For PW1 we have to wait both for the PW0/PG0 fuse state
+ * before enabling the power well and PW1/PG1's own fuse
+ * state after the enabling. For all other power wells with
+ * fuses we only have to wait for that PW/PG's fuse state
+ * after the enabling.
+ */
+ if (pg == SKL_PG1)
+ gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
+ }
+
val = I915_READ(HSW_PWR_WELL_DRIVER);
I915_WRITE(HSW_PWR_WELL_DRIVER, val | HSW_PWR_WELL_CTL_REQ(id));
hsw_wait_for_power_well_enable(dev_priv, power_well);
+ if (wait_fuses)
+ gen9_wait_for_power_well_fuses(dev_priv, pg);
+
hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
power_well->hsw.has_vga);
}
@@ -810,15 +837,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
case SKL_DISP_PW_1:
if (intel_wait_for_register(dev_priv,
SKL_FUSE_STATUS,
- SKL_FUSE_PG0_DIST_STATUS,
- SKL_FUSE_PG0_DIST_STATUS,
+ SKL_FUSE_PG_DIST_STATUS(SKL_PG0),
+ SKL_FUSE_PG_DIST_STATUS(SKL_PG0),
1)) {
DRM_ERROR("PG0 not enabled\n");
return;
}
break;
case SKL_DISP_PW_2:
- if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
+ if (!(fuse_status & SKL_FUSE_PG_DIST_STATUS(SKL_PG1))) {
DRM_ERROR("PG1 in disabled state\n");
return;
}
@@ -863,15 +890,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
if (power_well->id == SKL_DISP_PW_1) {
if (intel_wait_for_register(dev_priv,
SKL_FUSE_STATUS,
- SKL_FUSE_PG1_DIST_STATUS,
- SKL_FUSE_PG1_DIST_STATUS,
+ SKL_FUSE_PG_DIST_STATUS(SKL_PG1),
+ SKL_FUSE_PG_DIST_STATUS(SKL_PG1),
1))
DRM_ERROR("PG1 distributing status timeout\n");
} else if (power_well->id == SKL_DISP_PW_2) {
if (intel_wait_for_register(dev_priv,
SKL_FUSE_STATUS,
- SKL_FUSE_PG2_DIST_STATUS,
- SKL_FUSE_PG2_DIST_STATUS,
+ SKL_FUSE_PG_DIST_STATUS(SKL_PG2),
+ SKL_FUSE_PG_DIST_STATUS(SKL_PG2),
1))
DRM_ERROR("PG2 distributing status timeout\n");
}
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v2 16/18] drm/i915/gen9+: Unify the HSW/BDW and GEN9+ power well helpers
2017-07-06 14:40 ` [PATCH 16/18] drm/i915/gen9+: Unify the HSW/BDW and GEN9+ power well helpers Imre Deak
@ 2017-07-11 20:42 ` Imre Deak
2017-07-21 13:22 ` Arkadiusz Hiler
0 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-11 20:42 UTC (permalink / raw)
To: intel-gfx
After the previous refactorings the HSW/BDW and GEN9+ power well helpers
are practically identical, so use the HSW power well helpers for GEN9+
too. This means using the HSW power well ops instead of the SKL one and
setting the irq_pipe_mask, has_vga and has_fuses attributes as needed.
v2:
- Rebased on v2 of patch 15.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 231 ++++++--------------------------
1 file changed, 43 insertions(+), 188 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b473bd1028ff..4e3a7d797e15 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -313,38 +313,6 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
}
-static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- struct pci_dev *pdev = dev_priv->drm.pdev;
-
- /*
- * After we re-enable the power well, if we touch VGA register 0x3d5
- * we'll get unclaimed register interrupts. This stops after we write
- * anything to the VGA MSR register. The vgacon module uses this
- * register all the time, so if we unbind our driver and, as a
- * consequence, bind vgacon, we'll get stuck in an infinite loop at
- * console_unlock(). So make here we touch the VGA MSR register, making
- * sure vgacon can keep working normally without triggering interrupts
- * and error messages.
- */
- if (power_well->id == SKL_DISP_PW_2) {
- vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
- outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
- vga_put(pdev, VGA_RSRC_LEGACY_IO);
-
- gen8_irq_power_well_post_enable(dev_priv,
- 1 << PIPE_C | 1 << PIPE_B);
- }
-}
-
-static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- if (power_well->id == SKL_DISP_PW_2)
- gen8_irq_power_well_pre_disable(dev_priv,
- 1 << PIPE_C | 1 << PIPE_B);
-}
static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
@@ -823,91 +791,6 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
}
-static void skl_set_power_well(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well, bool enable)
-{
- uint32_t tmp, fuse_status;
- uint32_t req_mask, state_mask;
- bool check_fuse_status = false;
-
- tmp = I915_READ(HSW_PWR_WELL_DRIVER);
- fuse_status = I915_READ(SKL_FUSE_STATUS);
-
- switch (power_well->id) {
- case SKL_DISP_PW_1:
- if (intel_wait_for_register(dev_priv,
- SKL_FUSE_STATUS,
- SKL_FUSE_PG_DIST_STATUS(SKL_PG0),
- SKL_FUSE_PG_DIST_STATUS(SKL_PG0),
- 1)) {
- DRM_ERROR("PG0 not enabled\n");
- return;
- }
- break;
- case SKL_DISP_PW_2:
- if (!(fuse_status & SKL_FUSE_PG_DIST_STATUS(SKL_PG1))) {
- DRM_ERROR("PG1 in disabled state\n");
- return;
- }
- break;
- case SKL_DISP_PW_MISC_IO:
- case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A, CNL_DISP_PW_DDI_A */
- case SKL_DISP_PW_DDI_B:
- case SKL_DISP_PW_DDI_C:
- case SKL_DISP_PW_DDI_D:
- case GLK_DISP_PW_AUX_A: /* CNL_DISP_PW_AUX_A */
- case GLK_DISP_PW_AUX_B: /* CNL_DISP_PW_AUX_B */
- case GLK_DISP_PW_AUX_C: /* CNL_DISP_PW_AUX_C */
- case CNL_DISP_PW_AUX_D:
- break;
- default:
- WARN(1, "Unknown power well %u\n", power_well->id);
- return;
- }
-
- req_mask = HSW_PWR_WELL_CTL_REQ(power_well->id);
- state_mask = HSW_PWR_WELL_CTL_STATE(power_well->id);
-
- if (!enable)
- skl_power_well_pre_disable(dev_priv, power_well);
-
- if (enable) {
- I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
-
- DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
- check_fuse_status = true;
-
- hsw_wait_for_power_well_enable(dev_priv, power_well);
- } else {
- I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
- POSTING_READ(HSW_PWR_WELL_DRIVER);
- DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
-
- hsw_wait_for_power_well_disable(dev_priv, power_well);
- }
-
- if (check_fuse_status) {
- if (power_well->id == SKL_DISP_PW_1) {
- if (intel_wait_for_register(dev_priv,
- SKL_FUSE_STATUS,
- SKL_FUSE_PG_DIST_STATUS(SKL_PG1),
- SKL_FUSE_PG_DIST_STATUS(SKL_PG1),
- 1))
- DRM_ERROR("PG1 distributing status timeout\n");
- } else if (power_well->id == SKL_DISP_PW_2) {
- if (intel_wait_for_register(dev_priv,
- SKL_FUSE_STATUS,
- SKL_FUSE_PG_DIST_STATUS(SKL_PG2),
- SKL_FUSE_PG_DIST_STATUS(SKL_PG2),
- 1))
- DRM_ERROR("PG2 distributing status timeout\n");
- }
- }
-
- if (enable)
- skl_power_well_post_enable(dev_priv, power_well);
-}
-
static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -925,43 +808,6 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
}
}
-static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- uint32_t mask = HSW_PWR_WELL_CTL_REQ(power_well->id) |
- HSW_PWR_WELL_CTL_STATE(power_well->id);
-
- return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
-}
-
-static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- uint32_t mask = HSW_PWR_WELL_CTL_REQ(power_well->id);
- uint32_t bios_req = I915_READ(HSW_PWR_WELL_BIOS);
-
- /* Take over the request bit if set by BIOS. */
- if (bios_req & mask) {
- uint32_t drv_req = I915_READ(HSW_PWR_WELL_DRIVER);
-
- if (!(drv_req & mask))
- I915_WRITE(HSW_PWR_WELL_DRIVER, drv_req | mask);
- I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask);
- }
-}
-
-static void skl_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- skl_set_power_well(dev_priv, power_well, true);
-}
-
-static void skl_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- skl_set_power_well(dev_priv, power_well, false);
-}
-
static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -2049,13 +1895,6 @@ static const struct i915_power_well_ops hsw_power_well_ops = {
.is_enabled = hsw_power_well_enabled,
};
-static const struct i915_power_well_ops skl_power_well_ops = {
- .sync_hw = skl_power_well_sync_hw,
- .enable = skl_power_well_enable,
- .disable = skl_power_well_disable,
- .is_enabled = skl_power_well_enabled,
-};
-
static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = gen9_dc_off_power_well_enable,
@@ -2241,14 +2080,15 @@ static struct i915_power_well skl_power_wells[] = {
.name = "power well 1",
/* Handled by the DMC firmware */
.domains = 0,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
+ .hsw.has_fuses = true,
},
{
.name = "MISC IO power well",
/* Handled by the DMC firmware */
.domains = 0,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_MISC_IO,
},
{
@@ -2260,31 +2100,34 @@ static struct i915_power_well skl_power_wells[] = {
{
.name = "power well 2",
.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
},
{
.name = "DDI A/E IO power well",
.domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_A_E,
},
{
.name = "DDI B IO power well",
.domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_B,
},
{
.name = "DDI C IO power well",
.domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_C,
},
{
.name = "DDI D IO power well",
.domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_D,
},
};
@@ -2300,8 +2143,9 @@ static struct i915_power_well bxt_power_wells[] = {
{
.name = "power well 1",
.domains = 0,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
+ .hsw.has_fuses = true,
},
{
.name = "DC off",
@@ -2312,8 +2156,11 @@ static struct i915_power_well bxt_power_wells[] = {
{
.name = "power well 2",
.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
},
{
.name = "dpio-common-a",
@@ -2343,8 +2190,9 @@ static struct i915_power_well glk_power_wells[] = {
.name = "power well 1",
/* Handled by the DMC firmware */
.domains = 0,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
+ .hsw.has_fuses = true,
},
{
.name = "DC off",
@@ -2355,8 +2203,11 @@ static struct i915_power_well glk_power_wells[] = {
{
.name = "power well 2",
.domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
},
{
.name = "dpio-common-a",
@@ -2382,37 +2233,37 @@ static struct i915_power_well glk_power_wells[] = {
{
.name = "AUX A",
.domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = GLK_DISP_PW_AUX_A,
},
{
.name = "AUX B",
.domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = GLK_DISP_PW_AUX_B,
},
{
.name = "AUX C",
.domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = GLK_DISP_PW_AUX_C,
},
{
.name = "DDI A IO power well",
.domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = GLK_DISP_PW_DDI_A,
},
{
.name = "DDI B IO power well",
.domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_B,
},
{
.name = "DDI C IO power well",
.domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_C,
},
};
@@ -2429,31 +2280,32 @@ static struct i915_power_well cnl_power_wells[] = {
.name = "power well 1",
/* Handled by the DMC firmware */
.domains = 0,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
+ .hsw.has_fuses = true,
},
{
.name = "AUX A",
.domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_AUX_A,
},
{
.name = "AUX B",
.domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_AUX_B,
},
{
.name = "AUX C",
.domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_AUX_C,
},
{
.name = "AUX D",
.domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_AUX_D,
},
{
@@ -2465,31 +2317,34 @@ static struct i915_power_well cnl_power_wells[] = {
{
.name = "power well 2",
.domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
},
{
.name = "DDI A IO power well",
.domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_DDI_A,
},
{
.name = "DDI B IO power well",
.domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_B,
},
{
.name = "DDI C IO power well",
.domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_C,
},
{
.name = "DDI D IO power well",
.domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
- .ops = &skl_power_well_ops,
+ .ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_D,
},
};
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev8)
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (19 preceding siblings ...)
2017-07-07 14:59 ` ✓ Fi.CI.BAT: success for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev2) Patchwork
@ 2017-07-11 21:01 ` Patchwork
2017-07-12 16:17 ` ✗ Fi.CI.BAT: failure for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev9) Patchwork
21 siblings, 0 replies; 64+ messages in thread
From: Patchwork @ 2017-07-11 21:01 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev8)
URL : https://patchwork.freedesktop.org/series/26922/
State : warning
== Summary ==
Series 26922v8 drm/i915: Unify the HSW/BDW and GEN9+ power well code
https://patchwork.freedesktop.org/api/1.0/series/26922/revisions/8/mbox/
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass -> DMESG-WARN (fi-kbl-7560u) fdo#100125
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass -> SKIP (fi-skl-x1585l)
Test kms_force_connector_basic:
Subgroup prune-stale-modes:
pass -> SKIP (fi-ivb-3520m) fdo#101048
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
dmesg-warn -> PASS (fi-pnv-d510) fdo#101597
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#101048 https://bugs.freedesktop.org/show_bug.cgi?id=101048
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:439s
fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:424s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:389s
fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:536s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:506s
fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:487s
fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:482s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:597s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:431s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:413s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:421s
fi-ivb-3520m total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:504s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:476s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:465s
fi-kbl-7560u total:279 pass:268 dwarn:1 dfail:0 fail:0 skip:10 time:571s
fi-kbl-r total:279 pass:260 dwarn:1 dfail:0 fail:0 skip:18 time:578s
fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:562s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:463s
fi-skl-6700hq total:279 pass:262 dwarn:0 dfail:0 fail:0 skip:17 time:581s
fi-skl-6700k total:279 pass:257 dwarn:4 dfail:0 fail:0 skip:18 time:470s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:476s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:436s
fi-skl-x1585l total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:471s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:541s
fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:402s
8ad9e19aafea47c272163c2cbf554e06ff7f9857 drm-tip: 2017y-07m-11d-19h-08m-20s UTC integration manifest
8feeefe drm/i915/chv: Add unique power well ID for the pipe A power well
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5165/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v3 13/18] drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes
2017-07-06 14:40 ` [PATCH 13/18] drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes Imre Deak
2017-07-11 17:02 ` Ville Syrjälä
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
@ 2017-07-12 15:54 ` Imre Deak
2017-07-21 12:50 ` Arkadiusz Hiler
2 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-12 15:54 UTC (permalink / raw)
To: intel-gfx
The pattern of a power well backing a set of pipe IRQ or VGA
functionality applies to all HSW+ platforms. Using power well attributes
instead of platform checks to decide whether to init/reset pipe IRQs and
VGA correspondingly is cleaner and it allows us to unify the HSW/BDW and
GEN9+ power well code in follow-up patches.
Also use u8 for pipe_mask in related helpers to match the type in the
power well struct.
v2:
- Use u8 instead of u32 for irq_pipe_mask. (Ville)
v3:
- Use u8 for pipe_mask in related helpers too for clarity.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_runtime_pm.c | 34 ++++++++++++++++++++-------------
4 files changed, 31 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b27f2fcc0ad3..6f28fbe1de0f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1391,6 +1391,12 @@ struct i915_power_well {
struct {
enum dpio_phy phy;
} bxt;
+ struct {
+ /* Mask of pipes whose IRQ logic is backed by the pw */
+ u8 irq_pipe_mask;
+ /* The pw is backing the VGA functionality */
+ bool has_vga:1;
+ } hsw;
};
const struct i915_power_well_ops *ops;
};
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index eb4f1dca2077..e04bad1943c3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3074,7 +3074,7 @@ static void gen8_irq_reset(struct drm_device *dev)
}
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
- unsigned int pipe_mask)
+ u8 pipe_mask)
{
uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
enum pipe pipe;
@@ -3088,7 +3088,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
}
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
- unsigned int pipe_mask)
+ u8 pipe_mask)
{
enum pipe pipe;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d17a32437f07..ee333f7305f4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1251,9 +1251,9 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
int intel_get_crtc_scanline(struct intel_crtc *crtc);
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
- unsigned int pipe_mask);
+ u8 pipe_mask);
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
- unsigned int pipe_mask);
+ u8 pipe_mask);
void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5143a7302d54..8f8531b32348 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -281,7 +281,8 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv,
* to be enabled, and it will only be disabled if none of the registers is
* requesting it to be enabled.
*/
-static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
+static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
+ u8 irq_pipe_mask, bool has_vga)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
@@ -295,20 +296,21 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
* sure vgacon can keep working normally without triggering interrupts
* and error messages.
*/
- vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
- outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
- vga_put(pdev, VGA_RSRC_LEGACY_IO);
+ if (has_vga) {
+ vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
+ outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
+ vga_put(pdev, VGA_RSRC_LEGACY_IO);
+ }
- if (IS_BROADWELL(dev_priv))
- gen8_irq_power_well_post_enable(dev_priv,
- 1 << PIPE_C | 1 << PIPE_B);
+ if (irq_pipe_mask)
+ gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
}
-static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
+static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
+ u8 irq_pipe_mask)
{
- if (IS_BROADWELL(dev_priv))
- gen8_irq_power_well_pre_disable(dev_priv,
- 1 << PIPE_C | 1 << PIPE_B);
+ if (irq_pipe_mask)
+ gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
}
static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -413,7 +415,9 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
HSW_PWR_WELL_CTL_STATE(id),
20))
DRM_ERROR("Timeout enabling power well\n");
- hsw_power_well_post_enable(dev_priv);
+
+ hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
+ power_well->hsw.has_vga);
}
static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
@@ -422,7 +426,8 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
enum i915_power_well_id id = power_well->id;
u32 val;
- hsw_power_well_pre_disable(dev_priv);
+ hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask);
+
val = I915_READ(HSW_PWR_WELL_DRIVER);
I915_WRITE(HSW_PWR_WELL_DRIVER, val & ~HSW_PWR_WELL_CTL_REQ(id));
POSTING_READ(HSW_PWR_WELL_DRIVER);
@@ -2057,6 +2062,7 @@ static struct i915_power_well hsw_power_wells[] = {
.domains = HSW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
+ .hsw.has_vga = true,
},
};
@@ -2073,6 +2079,8 @@ static struct i915_power_well bdw_power_wells[] = {
.domains = BDW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
},
};
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev9)
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
` (20 preceding siblings ...)
2017-07-11 21:01 ` ✗ Fi.CI.BAT: warning for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev8) Patchwork
@ 2017-07-12 16:17 ` Patchwork
2017-07-12 17:17 ` Imre Deak
21 siblings, 1 reply; 64+ messages in thread
From: Patchwork @ 2017-07-12 16:17 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev9)
URL : https://patchwork.freedesktop.org/series/26922/
State : failure
== Summary ==
Series 26922v9 drm/i915: Unify the HSW/BDW and GEN9+ power well code
https://patchwork.freedesktop.org/api/1.0/series/26922/revisions/9/mbox/
Test core_auth:
Subgroup basic-auth:
pass -> DMESG-WARN (fi-ivb-3770)
Test core_prop_blob:
Subgroup basic:
pass -> DMESG-WARN (fi-ivb-3770)
Test drv_getparams_basic:
Subgroup basic-eu-total:
pass -> DMESG-WARN (fi-ivb-3770)
Subgroup basic-subslice-total:
pass -> DMESG-WARN (fi-ivb-3770)
Test drv_hangman:
Subgroup error-state-basic:
pass -> DMESG-WARN (fi-ivb-3770)
Test gem_basic:
Subgroup bad-close:
pass -> DMESG-WARN (fi-ivb-3770)
Subgroup create-close:
pass -> DMESG-WARN (fi-ivb-3770)
Subgroup create-fd-close:
pass -> DMESG-WARN (fi-ivb-3770)
Test gem_busy:
Subgroup basic-busy-default:
pass -> DMESG-WARN (fi-ivb-3770)
Subgroup basic-hang-default:
pass -> DMESG-WARN (fi-ivb-3770)
Test gem_close_race:
Subgroup basic-process:
pass -> DMESG-WARN (fi-ivb-3770)
Subgroup basic-threads:
pass -> DMESG-WARN (fi-ivb-3770)
Test gem_cpu_reloc:
Subgroup basic:
pass -> DMESG-WARN (fi-ivb-3770)
Test gem_cs_tlb:
Subgroup basic-default:
pass -> DMESG-WARN (fi-ivb-3770)
Test gem_ctx_basic:
pass -> DMESG-WARN (fi-ivb-3770)
Test gem_ctx_create:
Subgroup basic:
pass -> DMESG-WARN (fi-ivb-3770)
Subgroup basic-files:
pass -> DMESG-WARN (fi-ivb-3770)
Test gem_ctx_exec:
Subgroup basic:
pass -> DMESG-WARN (fi-ivb-3770)
Test gem_ctx_param:
Subgroup basic:
pass -> DMESG-WARN (fi-ivb-3770)
Subgroup basic-default:
pass -> DMESG-WARN (fi-ivb-3770)
Test gem_ctx_switch:
Subgroup basic-default:
pass -> DMESG-WARN (fi-ivb-3770)
Subgroup basic-default-heavy:
pass -> DMESG-WARN (fi-ivb-3770)
Test gem_exec_basic:
Subgroup basic-blt:
pass -> DMESG-WARN (fi-ivb-3770)
Subgroup basic-bsd:
pass -> DMESG-WARN (fi-ivb-3770)
Subgroup basic-default:
pass -> INCOMPLETE (fi-ivb-3770)
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass -> DMESG-WARN (fi-kbl-7560u) fdo#100125
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
dmesg-warn -> PASS (fi-pnv-d510) fdo#101597
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:440s
fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:427s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:354s
fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:535s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:510s
fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:489s
fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:485s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:599s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:436s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:409s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:427s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:491s
fi-ivb-3770 total:27 pass:0 dwarn:24 dfail:0 fail:0 skip:2
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:459s
fi-kbl-7560u total:279 pass:268 dwarn:1 dfail:0 fail:0 skip:10 time:575s
fi-kbl-r total:279 pass:260 dwarn:1 dfail:0 fail:0 skip:18 time:580s
fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:565s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:467s
fi-skl-6700hq total:279 pass:262 dwarn:0 dfail:0 fail:0 skip:17 time:585s
fi-skl-6700k total:279 pass:257 dwarn:4 dfail:0 fail:0 skip:18 time:463s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:482s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:439s
fi-skl-x1585l total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:499s
WARNING: Long output truncated
8ad9e19aafea47c272163c2cbf554e06ff7f9857 drm-tip: 2017y-07m-11d-19h-08m-20s UTC integration manifest
7936d65 drm/i915/chv: Add unique power well ID for the pipe A power well
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5174/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev9)
2017-07-12 16:17 ` ✗ Fi.CI.BAT: failure for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev9) Patchwork
@ 2017-07-12 17:17 ` Imre Deak
2017-07-24 14:32 ` Imre Deak
0 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-12 17:17 UTC (permalink / raw)
To: intel-gfx
On Wed, Jul 12, 2017 at 04:17:08PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev9)
> URL : https://patchwork.freedesktop.org/series/26922/
> State : failure
>
> == Summary ==
>
> Series 26922v9 drm/i915: Unify the HSW/BDW and GEN9+ power well code
> https://patchwork.freedesktop.org/api/1.0/series/26922/revisions/9/mbox/
>
> Test core_auth:
> Subgroup basic-auth:
> pass -> DMESG-WARN (fi-ivb-3770)
> Test core_prop_blob:
> Subgroup basic:
> pass -> DMESG-WARN (fi-ivb-3770)
> Test drv_getparams_basic:
> Subgroup basic-eu-total:
> pass -> DMESG-WARN (fi-ivb-3770)
> Subgroup basic-subslice-total:
> pass -> DMESG-WARN (fi-ivb-3770)
> Test drv_hangman:
> Subgroup error-state-basic:
> pass -> DMESG-WARN (fi-ivb-3770)
> Test gem_basic:
> Subgroup bad-close:
> pass -> DMESG-WARN (fi-ivb-3770)
> Subgroup create-close:
> pass -> DMESG-WARN (fi-ivb-3770)
> Subgroup create-fd-close:
> pass -> DMESG-WARN (fi-ivb-3770)
> Test gem_busy:
> Subgroup basic-busy-default:
> pass -> DMESG-WARN (fi-ivb-3770)
> Subgroup basic-hang-default:
> pass -> DMESG-WARN (fi-ivb-3770)
> Test gem_close_race:
> Subgroup basic-process:
> pass -> DMESG-WARN (fi-ivb-3770)
> Subgroup basic-threads:
> pass -> DMESG-WARN (fi-ivb-3770)
> Test gem_cpu_reloc:
> Subgroup basic:
> pass -> DMESG-WARN (fi-ivb-3770)
> Test gem_cs_tlb:
> Subgroup basic-default:
> pass -> DMESG-WARN (fi-ivb-3770)
> Test gem_ctx_basic:
> pass -> DMESG-WARN (fi-ivb-3770)
> Test gem_ctx_create:
> Subgroup basic:
> pass -> DMESG-WARN (fi-ivb-3770)
> Subgroup basic-files:
> pass -> DMESG-WARN (fi-ivb-3770)
> Test gem_ctx_exec:
> Subgroup basic:
> pass -> DMESG-WARN (fi-ivb-3770)
> Test gem_ctx_param:
> Subgroup basic:
> pass -> DMESG-WARN (fi-ivb-3770)
> Subgroup basic-default:
> pass -> DMESG-WARN (fi-ivb-3770)
> Test gem_ctx_switch:
> Subgroup basic-default:
> pass -> DMESG-WARN (fi-ivb-3770)
> Subgroup basic-default-heavy:
> pass -> DMESG-WARN (fi-ivb-3770)
> Test gem_exec_basic:
> Subgroup basic-blt:
> pass -> DMESG-WARN (fi-ivb-3770)
> Subgroup basic-bsd:
> pass -> DMESG-WARN (fi-ivb-3770)
> Subgroup basic-default:
> pass -> INCOMPLETE (fi-ivb-3770)
Can't see how the above failures could be related to the change. The log has a
few errors:
[ 1.892721] irq 16: nobody cared (try booting with the "irqpoll" option)
...
[ 1.892826] Disabling IRQ #16
But that IRQ belongs to the USB driver. Then some ACPI errors like:
[ 2.246024] ACPI Warning: SystemIO range
0x0000000000000428-0x000000000000042F conflicts with OpRegion 0x0000000000000400-0x000000000000047F (\PMIO) (20170303/utaddress-247)
followed by vblank and flip timeouts on pipe A. The first one:
[ 4.768197] vblank wait timed out on crtc 0
[ 4.768210] ------------[ cut here ]------------
[ 4.768215] WARNING: CPU: 4 PID: 148 at drivers/gpu/drm/drm_vblank.c:1066 drm_wait_one_vblank+0x191/0x1a0
[ 4.768216] Modules linked in: i915 x86_pkg_temp_thermal intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul r8169 snd_hda_intel ghash_clmulni_intel snd_hda_codec snd_hwdep mii snd_hda_core snd_pcm mei_me mei lpc_ich prime_numbers
[ 4.768234] CPU: 4 PID: 148 Comm: kworker/u16:4 Not tainted 4.12.0-CI-Patchwork_5174+ #1
[ 4.768235] Hardware name: Hewlett-Packard HP Pro 3500 Series/2ABF, BIOS 8.11 10/24/2012
[ 4.768238] Workqueue: events_unbound async_run_entry_fn
[ 4.768240] task: ffff880117690040 task.stack: ffffc90000758000
[ 4.768242] RIP: 0010:drm_wait_one_vblank+0x191/0x1a0
[ 4.768243] RSP: 0018:ffffc9000075b710 EFLAGS: 00010282
[ 4.768245] RAX: 000000000000001f RBX: ffff88010e8a0000 RCX: 0000000000000006
[ 4.768246] RDX: 0000000000000006 RSI: ffffffff81cba7da RDI: ffffffff81c99e7f
[ 4.768247] RBP: ffffc9000075b768 R08: 0000000000000000 R09: 0000000000000001
[ 4.768248] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
[ 4.768249] R13: 0000000000000000 R14: 0000000000000000 R15: 000000000000007d
[ 4.768250] FS: 0000000000000000(0000) GS:ffff88011fb00000(0000) knlGS:0000000000000000
[ 4.768251] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 4.768252] CR2: 00007f106567f624 CR3: 0000000001e0f000 CR4: 00000000001406e0
[ 4.768253] Call Trace:
[ 4.768257] ? wake_atomic_t_function+0x30/0x30
[ 4.768289] ironlake_crtc_enable+0x74e/0xbb0 [i915]
[ 4.768318] ? fwtable_read8+0x2c0/0x2c0 [i915]
[ 4.768347] intel_update_crtc+0x43/0xd0 [i915]
[ 4.768373] intel_update_crtcs+0x6a/0x80 [i915]
[ 4.768397] intel_atomic_commit_tail+0x2e2/0xf70 [i915]
[ 4.768423] intel_atomic_commit+0x3fb/0x500 [i915]
[ 4.768426] ? drm_atomic_check_only+0x3b0/0x560
[ 4.768429] drm_atomic_commit+0x46/0x50
[ 4.768432] restore_fbdev_mode_atomic+0x195/0x200
[ 4.768437] restore_fbdev_mode+0x2d/0x120
[ 4.768440] drm_fb_helper_restore_fbdev_mode_unlocked+0x34/0x90
[ 4.768442] drm_fb_helper_set_par+0x28/0x50
[ 4.768469] intel_fbdev_set_par+0x15/0x60 [i915]
[ 4.768472] fbcon_init+0x57a/0x600
[ 4.768477] visual_init+0xd1/0x130
[ 4.768479] do_bind_con_driver+0x1ad/0x390
[ 4.768483] do_take_over_console+0x110/0x170
[ 4.768486] do_fbcon_takeover+0x52/0xb0
[ 4.768488] fbcon_event_notify+0x723/0x850
[ 4.768491] ? __blocking_notifier_call_chain+0x30/0x70
[ 4.768494] notifier_call_chain+0x34/0x90
[ 4.768497] __blocking_notifier_call_chain+0x48/0x70
[ 4.768500] blocking_notifier_call_chain+0x11/0x20
[ 4.768502] fb_notifier_call_chain+0x16/0x20
[ 4.768503] register_framebuffer+0x24c/0x330
[ 4.768508] drm_fb_helper_initial_config+0x232/0x400
[ 4.768535] intel_fbdev_initial_config+0x13/0x30 [i915]
[ 4.768537] async_run_entry_fn+0x34/0x160
[ 4.768540] process_one_work+0x1fe/0x670
[ 4.768545] worker_thread+0x49/0x3b0
[ 4.768549] kthread+0x10f/0x150
[ 4.768550] ? process_one_work+0x670/0x670
[ 4.768552] ? kthread_create_on_node+0x40/0x40
[ 4.768555] ret_from_fork+0x27/0x40
[ 4.768560] Code: c0 e9 23 ff ff ff 48 8b 7d a8 48 8d 75 b0 e8 c7 b3 b1 ff 45 85 f6 0f 85 12 ff ff ff 44 89 e6 48 c7 c7 e0 48 cd 81 e8 08 87 bc ff <0f> ff e9 fc fe ff ff 0f 1f 84 00 00 00 00 00 55 8b b7 f8 00 00
[ 4.768614] ---[ end trace 49df762da7305d77 ]---
> Test gem_exec_suspend:
> Subgroup basic-s4-devices:
> pass -> DMESG-WARN (fi-kbl-7560u) fdo#100125
> Test kms_pipe_crc_basic:
> Subgroup hang-read-crc-pipe-b:
> dmesg-warn -> PASS (fi-pnv-d510) fdo#101597
>
> fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
> fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
>
> fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:440s
> fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:427s
> fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:354s
> fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:535s
> fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:510s
> fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:489s
> fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:485s
> fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:599s
> fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:436s
> fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:409s
> fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:427s
> fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:491s
> fi-ivb-3770 total:27 pass:0 dwarn:24 dfail:0 fail:0 skip:2
> fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:459s
> fi-kbl-7560u total:279 pass:268 dwarn:1 dfail:0 fail:0 skip:10 time:575s
> fi-kbl-r total:279 pass:260 dwarn:1 dfail:0 fail:0 skip:18 time:580s
> fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:565s
> fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:467s
> fi-skl-6700hq total:279 pass:262 dwarn:0 dfail:0 fail:0 skip:17 time:585s
> fi-skl-6700k total:279 pass:257 dwarn:4 dfail:0 fail:0 skip:18 time:463s
> fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:482s
> fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:439s
> fi-skl-x1585l total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:499s
> WARNING: Long output truncated
>
> 8ad9e19aafea47c272163c2cbf554e06ff7f9857 drm-tip: 2017y-07m-11d-19h-08m-20s UTC integration manifest
> 7936d65 drm/i915/chv: Add unique power well ID for the pipe A power well
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5174/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v3 06/18] drm/i915: Check for duplicated power well IDs
2017-07-11 20:42 ` [PATCH v3 " Imre Deak
@ 2017-07-20 13:08 ` Arkadiusz Hiler
0 siblings, 0 replies; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-20 13:08 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, Jul 11, 2017 at 11:42:33PM +0300, Imre Deak wrote:
> Check that all the power well IDs are unique on the given platform.
>
> v2:
> - Fix using BIT_ULL() instead of BIT() for 64 bit mask.
> v3:
> - Move the check to a separate function. (Ville)
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 07/18] drm/i915/bxt, glk: Give a proper name to the power well struct phy field
2017-07-06 14:40 ` [PATCH 07/18] drm/i915/bxt, glk: Give a proper name to the power well struct phy field Imre Deak
@ 2017-07-20 13:11 ` Arkadiusz Hiler
0 siblings, 0 replies; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-20 13:11 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 06, 2017 at 05:40:29PM +0300, Imre Deak wrote:
> Follow-up patches will add new fields to the i915_power_well struct that
> are specific to the hsw_power_well_ops helpers. Prepare for this by
> changing the generic 'data' field to a union of platform specific
> structs.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 08/18] drm/i915/gen9+: Remove redundant power well state assert during enabling
2017-07-06 14:40 ` [PATCH 08/18] drm/i915/gen9+: Remove redundant power well state assert during enabling Imre Deak
@ 2017-07-21 10:53 ` Arkadiusz Hiler
0 siblings, 0 replies; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-21 10:53 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 06, 2017 at 05:40:30PM +0300, Imre Deak wrote:
> We check already for power wells that are unexpectedly on (or forced on)
> during power well disabling. Those checks also account for other
> power well requesters like KVMR or DEBUG. As such this check is
> redundant, let's remove it to simplify things.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 09/18] drm/i915/gen9+: Remove redundant state check during power well toggling
2017-07-06 14:40 ` [PATCH 09/18] drm/i915/gen9+: Remove redundant state check during power well toggling Imre Deak
@ 2017-07-21 11:14 ` Arkadiusz Hiler
2017-07-21 11:25 ` Imre Deak
0 siblings, 1 reply; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-21 11:14 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 06, 2017 at 05:40:31PM +0300, Imre Deak wrote:
> Atm we enable/disable a power well only if it wasn't already
> enabled/disabled respectively. The only reason for this I can think of
> is to save the extra MMIO writes. Since the HW state matches the power
> well's usage counter most of the time the overhead due to these MMIOs is
> insignificant. Let's simplify the code by making the writes
> unconditional.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 25 +++++++++----------------
> 1 file changed, 9 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 85c592d..28d2ea9 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -806,7 +806,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> {
> uint32_t tmp, fuse_status;
> uint32_t req_mask, state_mask;
> - bool is_enabled, enable_requested, check_fuse_status = false;
> + bool check_fuse_status = false;
>
> tmp = I915_READ(HSW_PWR_WELL_DRIVER);
> fuse_status = I915_READ(SKL_FUSE_STATUS);
> @@ -844,29 +844,22 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> }
>
> req_mask = SKL_POWER_WELL_REQ(power_well->id);
> - enable_requested = tmp & req_mask;
> state_mask = SKL_POWER_WELL_STATE(power_well->id);
> - is_enabled = tmp & state_mask;
>
> - if (!enable && enable_requested)
> + if (!enable)
> skl_power_well_pre_disable(dev_priv, power_well);
>
> if (enable) {
> - if (!enable_requested)
> - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
> + I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
>
> - if (!is_enabled) {
> - DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
> - check_fuse_status = true;
> - }
> + DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
> + check_fuse_status = true;
It's the only place we set check_fuse_status to true and now we do that
unconditionally, so the following `if (check_fuse_status)` can be
inlined here, so we can drop the variable completely.
--
Cheers,
Arek
>
> gen9_wait_for_power_well_enable(dev_priv, power_well);
> } else {
> - if (enable_requested) {
> - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
> - POSTING_READ(HSW_PWR_WELL_DRIVER);
> - DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
> - }
> + I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
> + POSTING_READ(HSW_PWR_WELL_DRIVER);
> + DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
>
> gen9_wait_for_power_well_disable(dev_priv, power_well);
> }
> @@ -889,7 +882,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> }
> }
>
> - if (enable && !is_enabled)
> + if (enable)
> skl_power_well_post_enable(dev_priv, power_well);
> }
>
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 09/18] drm/i915/gen9+: Remove redundant state check during power well toggling
2017-07-21 11:14 ` Arkadiusz Hiler
@ 2017-07-21 11:25 ` Imre Deak
2017-07-21 11:32 ` Arkadiusz Hiler
0 siblings, 1 reply; 64+ messages in thread
From: Imre Deak @ 2017-07-21 11:25 UTC (permalink / raw)
To: Arkadiusz Hiler; +Cc: intel-gfx
On Fri, Jul 21, 2017 at 02:14:33PM +0300, Arkadiusz Hiler wrote:
> On Thu, Jul 06, 2017 at 05:40:31PM +0300, Imre Deak wrote:
> > Atm we enable/disable a power well only if it wasn't already
> > enabled/disabled respectively. The only reason for this I can think of
> > is to save the extra MMIO writes. Since the HW state matches the power
> > well's usage counter most of the time the overhead due to these MMIOs is
> > insignificant. Let's simplify the code by making the writes
> > unconditional.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 25 +++++++++----------------
> > 1 file changed, 9 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 85c592d..28d2ea9 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -806,7 +806,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> > {
> > uint32_t tmp, fuse_status;
> > uint32_t req_mask, state_mask;
> > - bool is_enabled, enable_requested, check_fuse_status = false;
> > + bool check_fuse_status = false;
> >
> > tmp = I915_READ(HSW_PWR_WELL_DRIVER);
> > fuse_status = I915_READ(SKL_FUSE_STATUS);
> > @@ -844,29 +844,22 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> > }
> >
> > req_mask = SKL_POWER_WELL_REQ(power_well->id);
> > - enable_requested = tmp & req_mask;
> > state_mask = SKL_POWER_WELL_STATE(power_well->id);
> > - is_enabled = tmp & state_mask;
> >
> > - if (!enable && enable_requested)
> > + if (!enable)
> > skl_power_well_pre_disable(dev_priv, power_well);
> >
> > if (enable) {
> > - if (!enable_requested)
> > - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
> > + I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
> >
> > - if (!is_enabled) {
> > - DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
> > - check_fuse_status = true;
> > - }
> > + DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
> > + check_fuse_status = true;
>
>
> It's the only place we set check_fuse_status to true and now we do that
> unconditionally, so the following `if (check_fuse_status)` can be
> inlined here, so we can drop the variable completely.
Hm yea. Also skl_power_well_pre_disable() and
skl_power_well_post_enable() could be inlined the same way then. But
this is an incremental change to simplify things even more in the end by
removing this function and using the HSW counterpart instead. Should've
mentioned this in the commit log. Do you still want me to change this?
--Imre
>
> --
> Cheers,
> Arek
>
>
> >
> > gen9_wait_for_power_well_enable(dev_priv, power_well);
> > } else {
> > - if (enable_requested) {
> > - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
> > - POSTING_READ(HSW_PWR_WELL_DRIVER);
> > - DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
> > - }
> > + I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
> > + POSTING_READ(HSW_PWR_WELL_DRIVER);
> > + DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
> >
> > gen9_wait_for_power_well_disable(dev_priv, power_well);
> > }
> > @@ -889,7 +882,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> > }
> > }
> >
> > - if (enable && !is_enabled)
> > + if (enable)
> > skl_power_well_post_enable(dev_priv, power_well);
> > }
> >
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 09/18] drm/i915/gen9+: Remove redundant state check during power well toggling
2017-07-21 11:25 ` Imre Deak
@ 2017-07-21 11:32 ` Arkadiusz Hiler
2017-07-21 13:24 ` Arkadiusz Hiler
0 siblings, 1 reply; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-21 11:32 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Fri, Jul 21, 2017 at 02:25:18PM +0300, Imre Deak wrote:
> On Fri, Jul 21, 2017 at 02:14:33PM +0300, Arkadiusz Hiler wrote:
> > On Thu, Jul 06, 2017 at 05:40:31PM +0300, Imre Deak wrote:
> > > Atm we enable/disable a power well only if it wasn't already
> > > enabled/disabled respectively. The only reason for this I can think of
> > > is to save the extra MMIO writes. Since the HW state matches the power
> > > well's usage counter most of the time the overhead due to these MMIOs is
> > > insignificant. Let's simplify the code by making the writes
> > > unconditional.
> > >
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 25 +++++++++----------------
> > > 1 file changed, 9 insertions(+), 16 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 85c592d..28d2ea9 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -806,7 +806,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> > > {
> > > uint32_t tmp, fuse_status;
> > > uint32_t req_mask, state_mask;
> > > - bool is_enabled, enable_requested, check_fuse_status = false;
> > > + bool check_fuse_status = false;
> > >
> > > tmp = I915_READ(HSW_PWR_WELL_DRIVER);
> > > fuse_status = I915_READ(SKL_FUSE_STATUS);
> > > @@ -844,29 +844,22 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> > > }
> > >
> > > req_mask = SKL_POWER_WELL_REQ(power_well->id);
> > > - enable_requested = tmp & req_mask;
> > > state_mask = SKL_POWER_WELL_STATE(power_well->id);
> > > - is_enabled = tmp & state_mask;
> > >
> > > - if (!enable && enable_requested)
> > > + if (!enable)
> > > skl_power_well_pre_disable(dev_priv, power_well);
> > >
> > > if (enable) {
> > > - if (!enable_requested)
> > > - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
> > > + I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
> > >
> > > - if (!is_enabled) {
> > > - DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
> > > - check_fuse_status = true;
> > > - }
> > > + DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
> > > + check_fuse_status = true;
> >
> >
> > It's the only place we set check_fuse_status to true and now we do that
> > unconditionally, so the following `if (check_fuse_status)` can be
> > inlined here, so we can drop the variable completely.
>
> Hm yea. Also skl_power_well_pre_disable() and
> skl_power_well_post_enable() could be inlined the same way then. But
> this is an incremental change to simplify things even more in the end by
> removing this function and using the HSW counterpart instead. Should've
> mentioned this in the commit log. Do you still want me to change this?
>
> --Imre
Let me go through the rest of the patches. If I will be happy with the
end result then I'll r-b this patch.
There no use bashing on intermediary steps and force you to rebase the
thing if the final result is good :-)
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 10/18] drm/i915/hsw, bdw: Remove redundant state check during power well toggling
2017-07-06 14:40 ` [PATCH 10/18] drm/i915/hsw, bdw: " Imre Deak
@ 2017-07-21 11:39 ` Arkadiusz Hiler
0 siblings, 0 replies; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-21 11:39 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 06, 2017 at 05:40:32PM +0300, Imre Deak wrote:
> Similarly to the GEN9 power well toggling, saving an occasional extra
> MMIO write is not worth the code complexity, let's simplify things.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 11/18] drm/i915/hsw, bdw: Split power well set to enable/disable helpers
2017-07-06 14:40 ` [PATCH 11/18] drm/i915/hsw, bdw: Split power well set to enable/disable helpers Imre Deak
@ 2017-07-21 11:51 ` Arkadiusz Hiler
0 siblings, 0 replies; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-21 11:51 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 06, 2017 at 05:40:33PM +0300, Imre Deak wrote:
> We can reduce the code indentation by splitting the set helper to
> separate enable/disable helpers. This also allows us to unify the
> HSW/BDW and GEN9+ power well ops in follow-up patches, which introduces
> some differences between the enable and disable helpers.
>
> While at it also remove the redundant enable/disable debug messages,
> the same info is printed already elsewhere.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 12/18] drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros
2017-07-06 14:40 ` [PATCH 12/18] drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros Imre Deak
@ 2017-07-21 12:39 ` Arkadiusz Hiler
0 siblings, 0 replies; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-21 12:39 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 06, 2017 at 05:40:34PM +0300, Imre Deak wrote:
> Although on HSW/BDW there is only a single display global power well,
> it's programmed the same way as other GEN9+ power wells. This also
> means we can get at the HSW/BDW request and status flags the same way
> it's done on GEN9+ by assigning the corresponding HSW/BDW power well ID.
> This ID was assigned in a recent patch, so we can now switch to using
> the same macros everywhere on HSW+.
>
> Updating the HSW power well control register with RMW is not strictly
> necessary, but this will allow us to use the same code for GEN9+.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
_______________________________________________
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v3 13/18] drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes
2017-07-12 15:54 ` [PATCH v3 " Imre Deak
@ 2017-07-21 12:50 ` Arkadiusz Hiler
0 siblings, 0 replies; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-21 12:50 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Jul 12, 2017 at 06:54:13PM +0300, Imre Deak wrote:
> The pattern of a power well backing a set of pipe IRQ or VGA
> functionality applies to all HSW+ platforms. Using power well attributes
> instead of platform checks to decide whether to init/reset pipe IRQs and
> VGA correspondingly is cleaner and it allows us to unify the HSW/BDW and
> GEN9+ power well code in follow-up patches.
>
> Also use u8 for pipe_mask in related helpers to match the type in the
> power well struct.
>
> v2:
> - Use u8 instead of u32 for irq_pipe_mask. (Ville)
>
> v3:
> - Use u8 for pipe_mask in related helpers too for clarity.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
_______________________________________________
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 14/18] drm/i915/hsw, bdw: Wait for the power well disabled state
2017-07-06 14:40 ` [PATCH 14/18] drm/i915/hsw, bdw: Wait for the power well disabled state Imre Deak
@ 2017-07-21 13:00 ` Arkadiusz Hiler
0 siblings, 0 replies; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-21 13:00 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 06, 2017 at 05:40:36PM +0300, Imre Deak wrote:
> Similarly to GEN9+ waiting for the power well disabled state is a safer
> option and also provides diagnostic info if the disabling didn't succeed
> or the power well was forced on by an external requester. While at it
> also use the existing GEN9+ helper to wait for the enabled state.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v2 15/18] drm/i915/hsw+: Add has_fuses power well attribute
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
@ 2017-07-21 13:10 ` Arkadiusz Hiler
0 siblings, 0 replies; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-21 13:10 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, Jul 11, 2017 at 11:42:35PM +0300, Imre Deak wrote:
> The pattern of a power well backing a set of fuses whose initialization
> we need to wait for during power well enabling is common to all GEN9+
> platforms. Adding support for this to the HSW power well enable helper
> allows us to use the HSW/BDW power well code for GEN9+ as well in a
> follow-up patch.
>
> v2:
> - Use an enum for power gates instead of raw numbers. (Ville)
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v2 16/18] drm/i915/gen9+: Unify the HSW/BDW and GEN9+ power well helpers
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
@ 2017-07-21 13:22 ` Arkadiusz Hiler
0 siblings, 0 replies; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-21 13:22 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, Jul 11, 2017 at 11:42:36PM +0300, Imre Deak wrote:
> After the previous refactorings the HSW/BDW and GEN9+ power well helpers
> are practically identical, so use the HSW power well helpers for GEN9+
> too. This means using the HSW power well ops instead of the SKL one and
> setting the irq_pipe_mask, has_vga and has_fuses attributes as needed.
>
> v2:
> - Rebased on v2 of patch 15.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
_______________________________________________
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 09/18] drm/i915/gen9+: Remove redundant state check during power well toggling
2017-07-21 11:32 ` Arkadiusz Hiler
@ 2017-07-21 13:24 ` Arkadiusz Hiler
0 siblings, 0 replies; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-21 13:24 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Fri, Jul 21, 2017 at 02:32:55PM +0300, Arkadiusz Hiler wrote:
> On Fri, Jul 21, 2017 at 02:25:18PM +0300, Imre Deak wrote:
> > On Fri, Jul 21, 2017 at 02:14:33PM +0300, Arkadiusz Hiler wrote:
> > > On Thu, Jul 06, 2017 at 05:40:31PM +0300, Imre Deak wrote:
> > > > Atm we enable/disable a power well only if it wasn't already
> > > > enabled/disabled respectively. The only reason for this I can think of
> > > > is to save the extra MMIO writes. Since the HW state matches the power
> > > > well's usage counter most of the time the overhead due to these MMIOs is
> > > > insignificant. Let's simplify the code by making the writes
> > > > unconditional.
> > > >
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/intel_runtime_pm.c | 25 +++++++++----------------
> > > > 1 file changed, 9 insertions(+), 16 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > index 85c592d..28d2ea9 100644
> > > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > @@ -806,7 +806,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> > > > {
> > > > uint32_t tmp, fuse_status;
> > > > uint32_t req_mask, state_mask;
> > > > - bool is_enabled, enable_requested, check_fuse_status = false;
> > > > + bool check_fuse_status = false;
> > > >
> > > > tmp = I915_READ(HSW_PWR_WELL_DRIVER);
> > > > fuse_status = I915_READ(SKL_FUSE_STATUS);
> > > > @@ -844,29 +844,22 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> > > > }
> > > >
> > > > req_mask = SKL_POWER_WELL_REQ(power_well->id);
> > > > - enable_requested = tmp & req_mask;
> > > > state_mask = SKL_POWER_WELL_STATE(power_well->id);
> > > > - is_enabled = tmp & state_mask;
> > > >
> > > > - if (!enable && enable_requested)
> > > > + if (!enable)
> > > > skl_power_well_pre_disable(dev_priv, power_well);
> > > >
> > > > if (enable) {
> > > > - if (!enable_requested)
> > > > - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
> > > > + I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
> > > >
> > > > - if (!is_enabled) {
> > > > - DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
> > > > - check_fuse_status = true;
> > > > - }
> > > > + DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
> > > > + check_fuse_status = true;
> > >
> > >
> > > It's the only place we set check_fuse_status to true and now we do that
> > > unconditionally, so the following `if (check_fuse_status)` can be
> > > inlined here, so we can drop the variable completely.
> >
> > Hm yea. Also skl_power_well_pre_disable() and
> > skl_power_well_post_enable() could be inlined the same way then. But
> > this is an incremental change to simplify things even more in the end by
> > removing this function and using the HSW counterpart instead. Should've
> > mentioned this in the commit log. Do you still want me to change this?
> >
> > --Imre
>
> Let me go through the rest of the patches. If I will be happy with the
> end result then I'll r-b this patch.
>
> There no use bashing on intermediary steps and force you to rebase the
> thing if the final result is good :-)
Made it to the part when you get rid of it completely.
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 17/18] drm/i915: Move hsw_power_well_enable() next to the rest of HSW helpers
2017-07-06 14:40 ` [PATCH 17/18] drm/i915: Move hsw_power_well_enable() next to the rest of HSW helpers Imre Deak
@ 2017-07-21 13:29 ` Arkadiusz Hiler
0 siblings, 0 replies; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-21 13:29 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 06, 2017 at 05:40:39PM +0300, Imre Deak wrote:
> Move the helper next to the rest of HSW specific code.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 18/18] drm/i915: Gather all the power well->domain mappings to one place
2017-07-06 14:40 ` [PATCH 18/18] drm/i915: Gather all the power well->domain mappings to one place Imre Deak
@ 2017-07-21 13:39 ` Arkadiusz Hiler
0 siblings, 0 replies; 64+ messages in thread
From: Arkadiusz Hiler @ 2017-07-21 13:39 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 06, 2017 at 05:40:40PM +0300, Imre Deak wrote:
> Shuffle the power well->domain mapping macros around so they are at one
> place in old->new GEN order.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev9)
2017-07-12 17:17 ` Imre Deak
@ 2017-07-24 14:32 ` Imre Deak
0 siblings, 0 replies; 64+ messages in thread
From: Imre Deak @ 2017-07-24 14:32 UTC (permalink / raw)
To: intel-gfx, Rodrigo Vivi, Arkadiusz Hiler, Ville Syrjälä
On Wed, Jul 12, 2017 at 08:17:00PM +0300, Imre Deak wrote:
> On Wed, Jul 12, 2017 at 04:17:08PM +0000, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev9)
> > URL : https://patchwork.freedesktop.org/series/26922/
> > State : failure
> >
> > == Summary ==
> >
> > Series 26922v9 drm/i915: Unify the HSW/BDW and GEN9+ power well code
> > https://patchwork.freedesktop.org/api/1.0/series/26922/revisions/9/mbox/
Thanks for the reviews I pushed the patchset to -dinq.
> >
> > Test core_auth:
> > Subgroup basic-auth:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Test core_prop_blob:
> > Subgroup basic:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Test drv_getparams_basic:
> > Subgroup basic-eu-total:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Subgroup basic-subslice-total:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Test drv_hangman:
> > Subgroup error-state-basic:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Test gem_basic:
> > Subgroup bad-close:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Subgroup create-close:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Subgroup create-fd-close:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Test gem_busy:
> > Subgroup basic-busy-default:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Subgroup basic-hang-default:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Test gem_close_race:
> > Subgroup basic-process:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Subgroup basic-threads:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Test gem_cpu_reloc:
> > Subgroup basic:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Test gem_cs_tlb:
> > Subgroup basic-default:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Test gem_ctx_basic:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Test gem_ctx_create:
> > Subgroup basic:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Subgroup basic-files:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Test gem_ctx_exec:
> > Subgroup basic:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Test gem_ctx_param:
> > Subgroup basic:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Subgroup basic-default:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Test gem_ctx_switch:
> > Subgroup basic-default:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Subgroup basic-default-heavy:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Test gem_exec_basic:
> > Subgroup basic-blt:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Subgroup basic-bsd:
> > pass -> DMESG-WARN (fi-ivb-3770)
> > Subgroup basic-default:
> > pass -> INCOMPLETE (fi-ivb-3770)
>
> Can't see how the above failures could be related to the change. The log has a
> few errors:
> [ 1.892721] irq 16: nobody cared (try booting with the "irqpoll" option)
> ...
> [ 1.892826] Disabling IRQ #16
>
> But that IRQ belongs to the USB driver. Then some ACPI errors like:
>
> [ 2.246024] ACPI Warning: SystemIO range
> 0x0000000000000428-0x000000000000042F conflicts with OpRegion 0x0000000000000400-0x000000000000047F (\PMIO) (20170303/utaddress-247)
>
> followed by vblank and flip timeouts on pipe A. The first one:
>
> [ 4.768197] vblank wait timed out on crtc 0
> [ 4.768210] ------------[ cut here ]------------
> [ 4.768215] WARNING: CPU: 4 PID: 148 at drivers/gpu/drm/drm_vblank.c:1066 drm_wait_one_vblank+0x191/0x1a0
> [ 4.768216] Modules linked in: i915 x86_pkg_temp_thermal intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul r8169 snd_hda_intel ghash_clmulni_intel snd_hda_codec snd_hwdep mii snd_hda_core snd_pcm mei_me mei lpc_ich prime_numbers
> [ 4.768234] CPU: 4 PID: 148 Comm: kworker/u16:4 Not tainted 4.12.0-CI-Patchwork_5174+ #1
> [ 4.768235] Hardware name: Hewlett-Packard HP Pro 3500 Series/2ABF, BIOS 8.11 10/24/2012
> [ 4.768238] Workqueue: events_unbound async_run_entry_fn
> [ 4.768240] task: ffff880117690040 task.stack: ffffc90000758000
> [ 4.768242] RIP: 0010:drm_wait_one_vblank+0x191/0x1a0
> [ 4.768243] RSP: 0018:ffffc9000075b710 EFLAGS: 00010282
> [ 4.768245] RAX: 000000000000001f RBX: ffff88010e8a0000 RCX: 0000000000000006
> [ 4.768246] RDX: 0000000000000006 RSI: ffffffff81cba7da RDI: ffffffff81c99e7f
> [ 4.768247] RBP: ffffc9000075b768 R08: 0000000000000000 R09: 0000000000000001
> [ 4.768248] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
> [ 4.768249] R13: 0000000000000000 R14: 0000000000000000 R15: 000000000000007d
> [ 4.768250] FS: 0000000000000000(0000) GS:ffff88011fb00000(0000) knlGS:0000000000000000
> [ 4.768251] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [ 4.768252] CR2: 00007f106567f624 CR3: 0000000001e0f000 CR4: 00000000001406e0
> [ 4.768253] Call Trace:
> [ 4.768257] ? wake_atomic_t_function+0x30/0x30
> [ 4.768289] ironlake_crtc_enable+0x74e/0xbb0 [i915]
> [ 4.768318] ? fwtable_read8+0x2c0/0x2c0 [i915]
> [ 4.768347] intel_update_crtc+0x43/0xd0 [i915]
> [ 4.768373] intel_update_crtcs+0x6a/0x80 [i915]
> [ 4.768397] intel_atomic_commit_tail+0x2e2/0xf70 [i915]
> [ 4.768423] intel_atomic_commit+0x3fb/0x500 [i915]
> [ 4.768426] ? drm_atomic_check_only+0x3b0/0x560
> [ 4.768429] drm_atomic_commit+0x46/0x50
> [ 4.768432] restore_fbdev_mode_atomic+0x195/0x200
> [ 4.768437] restore_fbdev_mode+0x2d/0x120
> [ 4.768440] drm_fb_helper_restore_fbdev_mode_unlocked+0x34/0x90
> [ 4.768442] drm_fb_helper_set_par+0x28/0x50
> [ 4.768469] intel_fbdev_set_par+0x15/0x60 [i915]
> [ 4.768472] fbcon_init+0x57a/0x600
> [ 4.768477] visual_init+0xd1/0x130
> [ 4.768479] do_bind_con_driver+0x1ad/0x390
> [ 4.768483] do_take_over_console+0x110/0x170
> [ 4.768486] do_fbcon_takeover+0x52/0xb0
> [ 4.768488] fbcon_event_notify+0x723/0x850
> [ 4.768491] ? __blocking_notifier_call_chain+0x30/0x70
> [ 4.768494] notifier_call_chain+0x34/0x90
> [ 4.768497] __blocking_notifier_call_chain+0x48/0x70
> [ 4.768500] blocking_notifier_call_chain+0x11/0x20
> [ 4.768502] fb_notifier_call_chain+0x16/0x20
> [ 4.768503] register_framebuffer+0x24c/0x330
> [ 4.768508] drm_fb_helper_initial_config+0x232/0x400
> [ 4.768535] intel_fbdev_initial_config+0x13/0x30 [i915]
> [ 4.768537] async_run_entry_fn+0x34/0x160
> [ 4.768540] process_one_work+0x1fe/0x670
> [ 4.768545] worker_thread+0x49/0x3b0
> [ 4.768549] kthread+0x10f/0x150
> [ 4.768550] ? process_one_work+0x670/0x670
> [ 4.768552] ? kthread_create_on_node+0x40/0x40
> [ 4.768555] ret_from_fork+0x27/0x40
> [ 4.768560] Code: c0 e9 23 ff ff ff 48 8b 7d a8 48 8d 75 b0 e8 c7 b3 b1 ff 45 85 f6 0f 85 12 ff ff ff 44 89 e6 48 c7 c7 e0 48 cd 81 e8 08 87 bc ff <0f> ff e9 fc fe ff ff 0f 1f 84 00 00 00 00 00 55 8b b7 f8 00 00
> [ 4.768614] ---[ end trace 49df762da7305d77 ]---
>
> > Test gem_exec_suspend:
> > Subgroup basic-s4-devices:
> > pass -> DMESG-WARN (fi-kbl-7560u) fdo#100125
> > Test kms_pipe_crc_basic:
> > Subgroup hang-read-crc-pipe-b:
> > dmesg-warn -> PASS (fi-pnv-d510) fdo#101597
> >
> > fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
> > fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
> >
> > fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:440s
> > fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:427s
> > fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:354s
> > fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:535s
> > fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:510s
> > fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:489s
> > fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:485s
> > fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:599s
> > fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:436s
> > fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:409s
> > fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:427s
> > fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:491s
> > fi-ivb-3770 total:27 pass:0 dwarn:24 dfail:0 fail:0 skip:2
> > fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:459s
> > fi-kbl-7560u total:279 pass:268 dwarn:1 dfail:0 fail:0 skip:10 time:575s
> > fi-kbl-r total:279 pass:260 dwarn:1 dfail:0 fail:0 skip:18 time:580s
> > fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:565s
> > fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:467s
> > fi-skl-6700hq total:279 pass:262 dwarn:0 dfail:0 fail:0 skip:17 time:585s
> > fi-skl-6700k total:279 pass:257 dwarn:4 dfail:0 fail:0 skip:18 time:463s
> > fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:482s
> > fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:439s
> > fi-skl-x1585l total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:499s
> > WARNING: Long output truncated
> >
> > 8ad9e19aafea47c272163c2cbf554e06ff7f9857 drm-tip: 2017y-07m-11d-19h-08m-20s UTC integration manifest
> > 7936d65 drm/i915/chv: Add unique power well ID for the pipe A power well
> >
> > == Logs ==
> >
> > For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5174/
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 64+ messages in thread
end of thread, other threads:[~2017-07-24 14:32 UTC | newest]
Thread overview: 64+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-07-06 14:40 [PATCH 00/23] drm/i915: Unify the HSW/BDW and GEN9+ power well code Imre Deak
2017-07-06 14:40 ` [PATCH 01/18] drm/i915/chv: Add unique power well ID for the pipe A power well Imre Deak
2017-07-11 16:31 ` Rodrigo Vivi
2017-07-06 14:40 ` [PATCH 02/18] drm/i915: Unify power well ID enums Imre Deak
2017-07-11 16:43 ` Rodrigo Vivi
2017-07-11 17:21 ` Rodrigo Vivi
2017-07-11 17:36 ` Imre Deak
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
2017-07-06 14:40 ` [PATCH 03/18] drm/i915: Assign everywhere the always-on power well ID Imre Deak
2017-07-11 16:45 ` Rodrigo Vivi
2017-07-06 14:40 ` [PATCH 04/18] drm/i915/gen2: Add an ID for the display pipes power well Imre Deak
2017-07-11 16:50 ` Rodrigo Vivi
2017-07-11 17:01 ` Ville Syrjälä
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
2017-07-06 14:40 ` [PATCH 05/18] drm/i915/hsw, bdw: Add an ID for the global display " Imre Deak
2017-07-11 17:08 ` Rodrigo Vivi
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
2017-07-06 14:40 ` [PATCH 06/18] drm/i915: Check for duplicated power well IDs Imre Deak
2017-07-07 14:39 ` [PATCH v2 " Imre Deak
2017-07-11 17:08 ` Ville Syrjälä
2017-07-11 20:42 ` [PATCH v3 " Imre Deak
2017-07-20 13:08 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 07/18] drm/i915/bxt, glk: Give a proper name to the power well struct phy field Imre Deak
2017-07-20 13:11 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 08/18] drm/i915/gen9+: Remove redundant power well state assert during enabling Imre Deak
2017-07-21 10:53 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 09/18] drm/i915/gen9+: Remove redundant state check during power well toggling Imre Deak
2017-07-21 11:14 ` Arkadiusz Hiler
2017-07-21 11:25 ` Imre Deak
2017-07-21 11:32 ` Arkadiusz Hiler
2017-07-21 13:24 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 10/18] drm/i915/hsw, bdw: " Imre Deak
2017-07-21 11:39 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 11/18] drm/i915/hsw, bdw: Split power well set to enable/disable helpers Imre Deak
2017-07-21 11:51 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 12/18] drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros Imre Deak
2017-07-21 12:39 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 13/18] drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes Imre Deak
2017-07-11 17:02 ` Ville Syrjälä
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
2017-07-12 15:54 ` [PATCH v3 " Imre Deak
2017-07-21 12:50 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 14/18] drm/i915/hsw, bdw: Wait for the power well disabled state Imre Deak
2017-07-21 13:00 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 15/18] drm/i915/hsw+: Add has_fuses power well attribute Imre Deak
2017-07-11 17:05 ` Ville Syrjälä
2017-07-11 17:22 ` Imre Deak
2017-07-11 17:37 ` Ville Syrjälä
2017-07-11 17:49 ` Imre Deak
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
2017-07-21 13:10 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 16/18] drm/i915/gen9+: Unify the HSW/BDW and GEN9+ power well helpers Imre Deak
2017-07-11 20:42 ` [PATCH v2 " Imre Deak
2017-07-21 13:22 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 17/18] drm/i915: Move hsw_power_well_enable() next to the rest of HSW helpers Imre Deak
2017-07-21 13:29 ` Arkadiusz Hiler
2017-07-06 14:40 ` [PATCH 18/18] drm/i915: Gather all the power well->domain mappings to one place Imre Deak
2017-07-21 13:39 ` Arkadiusz Hiler
2017-07-06 15:51 ` ✓ Fi.CI.BAT: success for drm/i915: Unify the HSW/BDW and GEN9+ power well code Patchwork
2017-07-07 14:59 ` ✓ Fi.CI.BAT: success for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev2) Patchwork
2017-07-11 21:01 ` ✗ Fi.CI.BAT: warning for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev8) Patchwork
2017-07-12 16:17 ` ✗ Fi.CI.BAT: failure for drm/i915: Unify the HSW/BDW and GEN9+ power well code (rev9) Patchwork
2017-07-12 17:17 ` Imre Deak
2017-07-24 14:32 ` Imre Deak
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