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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Shashank Sharma <shashank.sharma@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>,
	intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v2 09/14] drm/i915: add config function for YCBCR420 outputs
Date: Fri, 14 Jul 2017 21:30:30 +0300	[thread overview]
Message-ID: <20170714183030.GN12629@intel.com> (raw)
In-Reply-To: <1499960000-9232-10-git-send-email-shashank.sharma@intel.com>

On Thu, Jul 13, 2017 at 09:03:15PM +0530, Shashank Sharma wrote:
> This patch checks encoder level support for YCBCR420 outputs.
> The logic goes as simple as this:
> If the input mode is YCBCR420-only mode: prepare HDMI for
> YCBCR420 output, else continue with RGB output mode.
> 
> It checks if the mode is YCBCR420 and source can support this
> output then it marks the ycbcr_420 output indicator into crtc
> state, for further staging in driver.
> 
> V2: Split the patch into two, kept helper functions in DRM layer.
> V3: Changed the compute_config function based on new DRM API.
> V4: Rebase
> V5: Rebase
> V6: Check and handle YCBCR420-only modes, discard the property
>     based approach (Ville)
> V7: Addressed review comments from Ville
>     - add else case in 12BPC check.
>     - extract ycbcr420 state inside hdmi_12bpc_possible function.
> 
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
> 
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |  1 +
>  drivers/gpu/drm/i915/intel_drv.h     |  3 +++
>  drivers/gpu/drm/i915/intel_hdmi.c    | 43 +++++++++++++++++++++++++++++++++---
>  3 files changed, 44 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2144adc..a5140e4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11945,6 +11945,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
>  	PIPE_CONF_CHECK_I(hdmi_scrambling);
>  	PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
>  	PIPE_CONF_CHECK_I(has_infoframe);
> +	PIPE_CONF_CHECK_I(ycbcr420);
>  
>  	PIPE_CONF_CHECK_I(has_audio);
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index d17a324..592243b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -780,6 +780,9 @@ struct intel_crtc_state {
>  
>  	/* HDMI High TMDS char rate ratio */
>  	bool hdmi_high_tmds_clock_ratio;
> +
> +	/* HDMI output type */

We'll want DP too at some point. So that's going to get stale pretty
soon.

> +	bool ycbcr420;
>  };
>  
>  struct intel_crtc {
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index cc0d100..eb6243c 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1312,6 +1312,7 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
>  	struct drm_atomic_state *state = crtc_state->base.state;
>  	struct drm_connector_state *connector_state;
>  	struct drm_connector *connector;
> +	bool output_ycbcr420 = crtc_state->ycbcr420;

Pointless variable. Just use 'crtc_state->ycbcr420' in the code
directly.

>  	int i;
>  
>  	if (HAS_GMCH_DISPLAY(dev_priv))
> @@ -1330,8 +1331,16 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
>  		if (connector_state->crtc != crtc_state->base.crtc)
>  			continue;
>  
> -		if ((info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) == 0)
> -			return false;
> +		if (output_ycbcr420) {
> +			const struct drm_hdmi_info *hdmi = &info->hdmi;
> +
> +			if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
> +				return false;
> +		} else {
> +

Bogus whitespace.

> +			if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36))
> +				return false;
> +		}
>  	}
>  
>  	/* Display Wa #1139 */
> @@ -1342,6 +1351,25 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
>  	return true;
>  }
>  
> +static bool
> +intel_hdmi_ycbcr420_config(struct drm_connector *connector,
> +			       struct intel_crtc_state *config,
> +			       int *clock_12bpc, int *clock_8bpc)
> +{
> +

Bogus whitespace.

> +	if (!connector->ycbcr_420_allowed) {
> +		DRM_ERROR("Platform doesn't support YCBCR420 output\n");
> +		return false;
> +	}
> +
> +	/* YCBCR420 TMDS rate requirement is half the pixel clock */
> +	config->port_clock /= 2;
> +	*clock_12bpc /= 2;
> +	*clock_8bpc /= 2;
> +	config->ycbcr420 = true;
> +	return true;
> +}
> +
>  bool intel_hdmi_compute_config(struct intel_encoder *encoder,
>  			       struct intel_crtc_state *pipe_config,
>  			       struct drm_connector_state *conn_state)
> @@ -1349,7 +1377,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> -	struct drm_scdc *scdc = &conn_state->connector->display_info.hdmi.scdc;
> +	struct drm_connector *connector = conn_state->connector;
> +	struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
>  	struct intel_digital_connector_state *intel_conn_state =
>  		to_intel_digital_connector_state(conn_state);
>  	int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
> @@ -1379,6 +1408,14 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
>  		clock_12bpc *= 2;
>  	}
>  
> +	if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
> +		if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
> +						&clock_12bpc, &clock_8bpc)) {
> +			DRM_ERROR("Can't support YCBCR420 output\n");
> +			return false;
> +		}
> +	}
> +
>  	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
>  		pipe_config->has_pch_encoder = true;
>  
> -- 
> 2.7.4

-- 
Ville Syrjälä
Intel OTC
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  reply	other threads:[~2017-07-14 18:30 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-13 15:33 [PATCH v2 00/14] YCBCR 4:2:0 handling in DRM layer Shashank Sharma
2017-07-13 15:33 ` [PATCH v2 01/14] drm: handle HDMI 2.0 VICs in AVI info-frames Shashank Sharma
2017-07-13 15:33 ` [PATCH v2 02/14] drm/edid: complete CEA modedb(VIC 1-107) Shashank Sharma
2017-07-13 15:33 ` [PATCH v2 03/14] drm/edid: parse sink information before CEA blocks Shashank Sharma
2017-07-13 15:33 ` [PATCH v2 04/14] drm/edid: cleanup patch for CEA extended-tag macro Shashank Sharma
2017-07-13 15:33 ` [PATCH v2 05/14] drm: add helper to validate YCBCR420 modes Shashank Sharma
2017-07-13 15:33 ` [PATCH v2 06/14] drm/edid: parse YCBCR420 videomodes from EDID Shashank Sharma
2017-07-13 16:21   ` Ville Syrjälä
2017-07-14  4:04     ` Sharma, Shashank
2017-07-14 10:33       ` [PATCH v8 " Shashank Sharma
2017-07-13 15:33 ` [PATCH v2 07/14] drm/edid: parse ycbcr 420 deep color information Shashank Sharma
2017-07-13 15:33 ` [PATCH v2 08/14] drm: add helper functions for YCBCR420 handling Shashank Sharma
2017-07-13 15:33 ` [PATCH v2 09/14] drm/i915: add config function for YCBCR420 outputs Shashank Sharma
2017-07-14 18:30   ` Ville Syrjälä [this message]
2017-07-15  4:40     ` Sharma, Shashank
2017-07-13 15:33 ` [PATCH v2 10/14] drm/i915: prepare scaler for YCBCR420 modeset Shashank Sharma
2017-07-14 18:30   ` Ville Syrjälä
2017-07-15  4:41     ` Sharma, Shashank
2017-07-13 15:33 ` [PATCH v2 11/14] drm/i915: prepare pipe for YCBCR420 output Shashank Sharma
2017-07-14 18:33   ` Ville Syrjälä
2017-07-15  4:45     ` Sharma, Shashank
2017-07-13 15:33 ` [PATCH v2 12/14] drm/i915: prepare csc unit " Shashank Sharma
2017-07-14 18:36   ` Ville Syrjälä
2017-07-15  4:46     ` Sharma, Shashank
2017-07-13 15:33 ` [PATCH v2 13/14] drm/i915: set colorspace for YCBCR420 outputs Shashank Sharma
2017-07-13 15:33 ` [PATCH v2 14/14] drm/i915/glk: set HDMI 2.0 identifier Shashank Sharma
2017-07-13 15:50 ` ✓ Fi.CI.BAT: success for YCBCR 4:2:0 handling in DRM layer (rev2) Patchwork
2017-07-14 10:57 ` ✓ Fi.CI.BAT: success for YCBCR 4:2:0 handling in DRM layer (rev3) Patchwork
2017-07-14 19:02 ` [PATCH v2 00/14] YCBCR 4:2:0 handling in DRM layer Ville Syrjälä
2017-07-15  5:03   ` Sharma, Shashank

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