Re: [PATCH] drm/i915/cnl: Add allowed DP rates for Cannonlake.

[Manasi Navare <manasi.d.navare@intel.com>]

Verified this as per the Bspec and it looks good.

Manasi

On Thu, Aug 10, 2017 at 03:40:08PM -0700, Rodrigo Vivi wrote:
> "Frequencies over 5.4 GHz only supported on certain
> DDI ports and SKUs, and requires Vccio >= 0.95V."
> 
> More specifically, for current CNL SKUs available
> (CNL-U and CNL-Y) we have:
> 
> DDI A - 5.4G eDP
> DDI B - 8.1G DP
> DDI C - 8.1G DP
> DDI D - 5.4G DP
> 
> v2: Rebase on top of source_rates changes.
> v3: Address the max 5.4 x 8.1 per DDI and also consider vccio.
> 
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 76c8a0bd17f9..ead37c449019 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -97,6 +97,9 @@ static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
>  				  324000, 432000, 540000 };
>  static const int skl_rates[] = { 162000, 216000, 270000,
>  				  324000, 432000, 540000 };
> +static const int cnl_rates[] = { 162000, 216000, 270000,
> +				 324000, 432000, 540000,
> +				 648000, 810000 };
>  static const int default_rates[] = { 162000, 270000, 540000 };
>  
>  /**
> @@ -229,8 +232,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> +	enum port port = dig_port->port;
>  	const int *source_rates;
>  	int size;
> +	u32 voltage;
>  
>  	/* This should only be done once */
>  	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
> @@ -238,6 +243,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  	if (IS_GEN9_LP(dev_priv)) {
>  		source_rates = bxt_rates;
>  		size = ARRAY_SIZE(bxt_rates);
> +	} else if (IS_CANNONLAKE(dev_priv)) {
> +		source_rates = cnl_rates;
> +		size = ARRAY_SIZE(cnl_rates);
> +		voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +		if (port == PORT_A || port == PORT_D ||
> +		    voltage == VOLTAGE_INFO_0_85V)
> +			size -= 2;
>  	} else if (IS_GEN9_BC(dev_priv)) {
>  		source_rates = skl_rates;
>  		size = ARRAY_SIZE(skl_rates);
> -- 
> 2.13.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx