* [PATCH 01/16] drm/i915: Don't enable/unmask flip interrupts
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
@ 2017-08-18 18:36 ` ville.syrjala
2017-09-14 12:09 ` Imre Deak
2017-08-18 18:36 ` [PATCH 02/16] drm/i915: Clear pipestat consistently ville.syrjala
` (20 subsequent siblings)
21 siblings, 1 reply; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
commit fd3a40242e87 ("drm/i915: Rip out legacy page_flip completion/irq
handling") removed the code to hande the flip done/pending interrupts,
but it failed to actually disable/mask those interrupts. Let's do that
now.
Also remove a stale comment that was left behind.
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 34 ++++++++--------------------------
1 file changed, 8 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e21ce9c18b6e..4bfa7fbbd72e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2925,8 +2925,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
u32 enable_mask;
enum pipe pipe;
- pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
- PIPE_CRC_DONE_INTERRUPT_STATUS;
+ pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
for_each_pipe(dev_priv, pipe)
@@ -3299,18 +3298,14 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
if (INTEL_GEN(dev_priv) >= 7) {
display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
- DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
- DE_PLANEB_FLIP_DONE_IVB |
- DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
+ DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
DE_DP_A_HOTPLUG_IVB);
} else {
display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
- DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
- DE_AUX_CHANNEL_A |
- DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
- DE_POISON);
+ DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
+ DE_PIPEA_CRC_DONE | DE_POISON);
extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
DE_DP_A_HOTPLUG);
@@ -3432,15 +3427,13 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
enum pipe pipe;
if (INTEL_GEN(dev_priv) >= 9) {
- de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
- GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
+ de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
if (IS_GEN9_LP(dev_priv))
de_port_masked |= BXT_DE_PORT_GMBUS;
} else {
- de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
- GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
+ de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
}
de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
@@ -3590,9 +3583,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
/* Unmask the interrupts that we always want on. */
dev_priv->irq_mask =
~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
- I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
- I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
- I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
+ I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
I915_WRITE16(IMR, dev_priv->irq_mask);
I915_WRITE16(IER,
@@ -3611,9 +3602,6 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
return 0;
}
-/*
- * Returns true when a page flip has completed.
- */
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
{
struct drm_device *dev = arg;
@@ -3732,9 +3720,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
dev_priv->irq_mask =
~(I915_ASLE_INTERRUPT |
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
- I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
- I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
- I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
+ I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
enable_mask =
I915_ASLE_INTERRUPT |
@@ -3919,13 +3905,9 @@ static int i965_irq_postinstall(struct drm_device *dev)
I915_DISPLAY_PORT_INTERRUPT |
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
- I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
- I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
enable_mask = ~dev_priv->irq_mask;
- enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
- I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
enable_mask |= I915_USER_INTERRUPT;
if (IS_G4X(dev_priv))
--
2.13.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH 01/16] drm/i915: Don't enable/unmask flip interrupts
2017-08-18 18:36 ` [PATCH 01/16] drm/i915: Don't enable/unmask flip interrupts ville.syrjala
@ 2017-09-14 12:09 ` Imre Deak
0 siblings, 0 replies; 35+ messages in thread
From: Imre Deak @ 2017-09-14 12:09 UTC (permalink / raw)
To: ville.syrjala; +Cc: Daniel Vetter, intel-gfx
On Fri, Aug 18, 2017 at 09:36:50PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> commit fd3a40242e87 ("drm/i915: Rip out legacy page_flip completion/irq
> handling") removed the code to hande the flip done/pending interrupts,
> but it failed to actually disable/mask those interrupts. Let's do that
> now.
>
> Also remove a stale comment that was left behind.
>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 34 ++++++++--------------------------
> 1 file changed, 8 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e21ce9c18b6e..4bfa7fbbd72e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2925,8 +2925,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
> u32 enable_mask;
> enum pipe pipe;
>
> - pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
> - PIPE_CRC_DONE_INTERRUPT_STATUS;
> + pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
>
> i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
> for_each_pipe(dev_priv, pipe)
> @@ -3299,18 +3298,14 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
>
> if (INTEL_GEN(dev_priv) >= 7) {
> display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
> - DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
> - DE_PLANEB_FLIP_DONE_IVB |
> - DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
> + DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
> extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
> DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
> DE_DP_A_HOTPLUG_IVB);
> } else {
> display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
> - DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
> - DE_AUX_CHANNEL_A |
> - DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
> - DE_POISON);
> + DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
> + DE_PIPEA_CRC_DONE | DE_POISON);
> extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
> DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
> DE_DP_A_HOTPLUG);
> @@ -3432,15 +3427,13 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> enum pipe pipe;
>
> if (INTEL_GEN(dev_priv) >= 9) {
> - de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
> - GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> + de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
> GEN9_AUX_CHANNEL_D;
> if (IS_GEN9_LP(dev_priv))
> de_port_masked |= BXT_DE_PORT_GMBUS;
> } else {
> - de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
> - GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> + de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> }
>
> de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
> @@ -3590,9 +3583,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
> /* Unmask the interrupts that we always want on. */
> dev_priv->irq_mask =
> ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> - I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
> - I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
> - I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
> + I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
> I915_WRITE16(IMR, dev_priv->irq_mask);
>
> I915_WRITE16(IER,
> @@ -3611,9 +3602,6 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
> return 0;
> }
>
> -/*
> - * Returns true when a page flip has completed.
> - */
> static irqreturn_t i8xx_irq_handler(int irq, void *arg)
> {
> struct drm_device *dev = arg;
> @@ -3732,9 +3720,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
> dev_priv->irq_mask =
> ~(I915_ASLE_INTERRUPT |
> I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> - I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
> - I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
> - I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
> + I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
>
> enable_mask =
> I915_ASLE_INTERRUPT |
> @@ -3919,13 +3905,9 @@ static int i965_irq_postinstall(struct drm_device *dev)
> I915_DISPLAY_PORT_INTERRUPT |
> I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
> - I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
> - I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
> I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
>
> enable_mask = ~dev_priv->irq_mask;
> - enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
> - I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
> enable_mask |= I915_USER_INTERRUPT;
>
> if (IS_G4X(dev_priv))
> --
> 2.13.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 02/16] drm/i915: Clear pipestat consistently
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
2017-08-18 18:36 ` [PATCH 01/16] drm/i915: Don't enable/unmask flip interrupts ville.syrjala
@ 2017-08-18 18:36 ` ville.syrjala
2017-09-14 13:51 ` Imre Deak
2017-08-18 18:36 ` [PATCH v2 03/16] drm/i915: s/GEN5/GEN3/ ville.syrjala
` (19 subsequent siblings)
21 siblings, 1 reply; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We have a lot of different ways of clearing the PIPESTAT registers.
Let's unify it all into one function. There's no magic in PIPESTAT
that would require any of the double clearing and whatnot that
some of the code tries to do. All we can really do is clear the status
bits and disable the enable bits. There is no way to mask anything
so as soon as another event happens the status bit will become set
again, and trying to clear them twice or something can't protect
against that.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 67 ++++++++++++++++++-----------------------
1 file changed, 30 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4bfa7fbbd72e..9e0ee014a055 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1709,6 +1709,19 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
}
}
+static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
+{
+ enum pipe pipe;
+
+ for_each_pipe(dev_priv, pipe) {
+ I915_WRITE(PIPESTAT(pipe),
+ PIPESTAT_INT_STATUS_MASK |
+ PIPE_FIFO_UNDERRUN_STATUS);
+
+ dev_priv->pipestat_irq_mask[pipe] = 0;
+ }
+}
+
static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
u32 iir, u32 pipe_stats[I915_MAX_PIPES])
{
@@ -2898,8 +2911,6 @@ static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
{
- enum pipe pipe;
-
if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
else
@@ -2908,12 +2919,7 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
- for_each_pipe(dev_priv, pipe) {
- I915_WRITE(PIPESTAT(pipe),
- PIPE_FIFO_UNDERRUN_STATUS |
- PIPESTAT_INT_STATUS_MASK);
- dev_priv->pipestat_irq_mask[pipe] = 0;
- }
+ i9xx_pipestat_irq_reset(dev_priv);
GEN5_IRQ_RESET(VLV_);
dev_priv->irq_mask = ~0;
@@ -3564,10 +3570,9 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
static void i8xx_irq_preinstall(struct drm_device * dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- int pipe;
- for_each_pipe(dev_priv, pipe)
- I915_WRITE(PIPESTAT(pipe), 0);
+ i9xx_pipestat_irq_reset(dev_priv);
+
I915_WRITE16(IMR, 0xffff);
I915_WRITE16(IER, 0x0);
POSTING_READ16(IER);
@@ -3679,13 +3684,9 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
static void i8xx_irq_uninstall(struct drm_device * dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- int pipe;
- for_each_pipe(dev_priv, pipe) {
- /* Clear enable bits; then clear status bits */
- I915_WRITE(PIPESTAT(pipe), 0);
- I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
- }
+ i9xx_pipestat_irq_reset(dev_priv);
+
I915_WRITE16(IMR, 0xffff);
I915_WRITE16(IER, 0x0);
I915_WRITE16(IIR, I915_READ16(IIR));
@@ -3694,16 +3695,16 @@ static void i8xx_irq_uninstall(struct drm_device * dev)
static void i915_irq_preinstall(struct drm_device * dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- int pipe;
if (I915_HAS_HOTPLUG(dev_priv)) {
i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
}
+ i9xx_pipestat_irq_reset(dev_priv);
+
I915_WRITE16(HWSTAM, 0xeffe);
- for_each_pipe(dev_priv, pipe)
- I915_WRITE(PIPESTAT(pipe), 0);
+
I915_WRITE(IMR, 0xffffffff);
I915_WRITE(IER, 0x0);
POSTING_READ(IER);
@@ -3859,36 +3860,32 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
static void i915_irq_uninstall(struct drm_device * dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- int pipe;
if (I915_HAS_HOTPLUG(dev_priv)) {
i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
}
+ i9xx_pipestat_irq_reset(dev_priv);
+
I915_WRITE16(HWSTAM, 0xffff);
- for_each_pipe(dev_priv, pipe) {
- /* Clear enable bits; then clear status bits */
- I915_WRITE(PIPESTAT(pipe), 0);
- I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
- }
+
I915_WRITE(IMR, 0xffffffff);
I915_WRITE(IER, 0x0);
-
I915_WRITE(IIR, I915_READ(IIR));
}
static void i965_irq_preinstall(struct drm_device * dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- int pipe;
i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+ i9xx_pipestat_irq_reset(dev_priv);
+
I915_WRITE(HWSTAM, 0xeffe);
- for_each_pipe(dev_priv, pipe)
- I915_WRITE(PIPESTAT(pipe), 0);
+
I915_WRITE(IMR, 0xffffffff);
I915_WRITE(IER, 0x0);
POSTING_READ(IER);
@@ -4082,7 +4079,6 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
static void i965_irq_uninstall(struct drm_device * dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- int pipe;
if (!dev_priv)
return;
@@ -4090,15 +4086,12 @@ static void i965_irq_uninstall(struct drm_device * dev)
i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+ i9xx_pipestat_irq_reset(dev_priv);
+
I915_WRITE(HWSTAM, 0xffffffff);
- for_each_pipe(dev_priv, pipe)
- I915_WRITE(PIPESTAT(pipe), 0);
+
I915_WRITE(IMR, 0xffffffff);
I915_WRITE(IER, 0x0);
-
- for_each_pipe(dev_priv, pipe)
- I915_WRITE(PIPESTAT(pipe),
- I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
I915_WRITE(IIR, I915_READ(IIR));
}
--
2.13.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH 02/16] drm/i915: Clear pipestat consistently
2017-08-18 18:36 ` [PATCH 02/16] drm/i915: Clear pipestat consistently ville.syrjala
@ 2017-09-14 13:51 ` Imre Deak
0 siblings, 0 replies; 35+ messages in thread
From: Imre Deak @ 2017-09-14 13:51 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Fri, Aug 18, 2017 at 09:36:51PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We have a lot of different ways of clearing the PIPESTAT registers.
> Let's unify it all into one function. There's no magic in PIPESTAT
> that would require any of the double clearing and whatnot that
> some of the code tries to do. All we can really do is clear the status
> bits and disable the enable bits. There is no way to mask anything
> so as soon as another event happens the status bit will become set
> again, and trying to clear them twice or something can't protect
> against that.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 67 ++++++++++++++++++-----------------------
> 1 file changed, 30 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 4bfa7fbbd72e..9e0ee014a055 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1709,6 +1709,19 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
> }
> }
>
> +static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
> +{
> + enum pipe pipe;
> +
> + for_each_pipe(dev_priv, pipe) {
> + I915_WRITE(PIPESTAT(pipe),
> + PIPESTAT_INT_STATUS_MASK |
> + PIPE_FIFO_UNDERRUN_STATUS);
> +
> + dev_priv->pipestat_irq_mask[pipe] = 0;
> + }
> +}
> +
> static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
> u32 iir, u32 pipe_stats[I915_MAX_PIPES])
> {
> @@ -2898,8 +2911,6 @@ static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
>
> static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
> {
> - enum pipe pipe;
> -
> if (IS_CHERRYVIEW(dev_priv))
> I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
> else
> @@ -2908,12 +2919,7 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
> i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
> I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
>
> - for_each_pipe(dev_priv, pipe) {
> - I915_WRITE(PIPESTAT(pipe),
> - PIPE_FIFO_UNDERRUN_STATUS |
> - PIPESTAT_INT_STATUS_MASK);
> - dev_priv->pipestat_irq_mask[pipe] = 0;
> - }
> + i9xx_pipestat_irq_reset(dev_priv);
>
> GEN5_IRQ_RESET(VLV_);
> dev_priv->irq_mask = ~0;
> @@ -3564,10 +3570,9 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
> static void i8xx_irq_preinstall(struct drm_device * dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int pipe;
>
> - for_each_pipe(dev_priv, pipe)
> - I915_WRITE(PIPESTAT(pipe), 0);
> + i9xx_pipestat_irq_reset(dev_priv);
> +
> I915_WRITE16(IMR, 0xffff);
> I915_WRITE16(IER, 0x0);
> POSTING_READ16(IER);
> @@ -3679,13 +3684,9 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
> static void i8xx_irq_uninstall(struct drm_device * dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int pipe;
>
> - for_each_pipe(dev_priv, pipe) {
> - /* Clear enable bits; then clear status bits */
> - I915_WRITE(PIPESTAT(pipe), 0);
> - I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
> - }
> + i9xx_pipestat_irq_reset(dev_priv);
> +
> I915_WRITE16(IMR, 0xffff);
> I915_WRITE16(IER, 0x0);
> I915_WRITE16(IIR, I915_READ16(IIR));
> @@ -3694,16 +3695,16 @@ static void i8xx_irq_uninstall(struct drm_device * dev)
> static void i915_irq_preinstall(struct drm_device * dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int pipe;
>
> if (I915_HAS_HOTPLUG(dev_priv)) {
> i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
> I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
> }
>
> + i9xx_pipestat_irq_reset(dev_priv);
> +
> I915_WRITE16(HWSTAM, 0xeffe);
> - for_each_pipe(dev_priv, pipe)
> - I915_WRITE(PIPESTAT(pipe), 0);
> +
> I915_WRITE(IMR, 0xffffffff);
> I915_WRITE(IER, 0x0);
> POSTING_READ(IER);
> @@ -3859,36 +3860,32 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
> static void i915_irq_uninstall(struct drm_device * dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int pipe;
>
> if (I915_HAS_HOTPLUG(dev_priv)) {
> i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
> I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
> }
>
> + i9xx_pipestat_irq_reset(dev_priv);
> +
> I915_WRITE16(HWSTAM, 0xffff);
> - for_each_pipe(dev_priv, pipe) {
> - /* Clear enable bits; then clear status bits */
> - I915_WRITE(PIPESTAT(pipe), 0);
> - I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
> - }
> +
> I915_WRITE(IMR, 0xffffffff);
> I915_WRITE(IER, 0x0);
> -
> I915_WRITE(IIR, I915_READ(IIR));
> }
>
> static void i965_irq_preinstall(struct drm_device * dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int pipe;
>
> i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
> I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
>
> + i9xx_pipestat_irq_reset(dev_priv);
> +
> I915_WRITE(HWSTAM, 0xeffe);
> - for_each_pipe(dev_priv, pipe)
> - I915_WRITE(PIPESTAT(pipe), 0);
> +
> I915_WRITE(IMR, 0xffffffff);
> I915_WRITE(IER, 0x0);
> POSTING_READ(IER);
> @@ -4082,7 +4079,6 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
> static void i965_irq_uninstall(struct drm_device * dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int pipe;
>
> if (!dev_priv)
> return;
> @@ -4090,15 +4086,12 @@ static void i965_irq_uninstall(struct drm_device * dev)
> i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
> I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
>
> + i9xx_pipestat_irq_reset(dev_priv);
> +
> I915_WRITE(HWSTAM, 0xffffffff);
> - for_each_pipe(dev_priv, pipe)
> - I915_WRITE(PIPESTAT(pipe), 0);
> +
> I915_WRITE(IMR, 0xffffffff);
> I915_WRITE(IER, 0x0);
> -
> - for_each_pipe(dev_priv, pipe)
> - I915_WRITE(PIPESTAT(pipe),
> - I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
> I915_WRITE(IIR, I915_READ(IIR));
> }
>
> --
> 2.13.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 03/16] drm/i915: s/GEN5/GEN3/
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
2017-08-18 18:36 ` [PATCH 01/16] drm/i915: Don't enable/unmask flip interrupts ville.syrjala
2017-08-18 18:36 ` [PATCH 02/16] drm/i915: Clear pipestat consistently ville.syrjala
@ 2017-08-18 18:36 ` ville.syrjala
2017-08-18 18:36 ` [PATCH 04/16] drm/i915: Use GEN3_IRQ_RESET/INIT on gen3/4 ville.syrjala
` (18 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The GEN5_IRQ_RESET/INIT macros are perfectly suitable even for
gen3/4 hardware as those have 32 bit interrupt registers. Let's
rename the macros to reflect that fact.
Gen2 on the other hand has 16 bit interrupt registers so these
macros aren't really appropriate there.
v2: Fix patch subject (Maarten)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 44 ++++++++++++++++++++---------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9e0ee014a055..8f4f1908cf55 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -126,7 +126,7 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
POSTING_READ(GEN8_##type##_IIR(which)); \
} while (0)
-#define GEN5_IRQ_RESET(type) do { \
+#define GEN3_IRQ_RESET(type) do { \
I915_WRITE(type##IMR, 0xffffffff); \
POSTING_READ(type##IMR); \
I915_WRITE(type##IER, 0); \
@@ -139,7 +139,7 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
/*
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
*/
-static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
+static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
i915_reg_t reg)
{
u32 val = I915_READ(reg);
@@ -156,14 +156,14 @@ static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
}
#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
- gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
+ gen3_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
POSTING_READ(GEN8_##type##_IMR(which)); \
} while (0)
-#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
- gen5_assert_iir_is_zero(dev_priv, type##IIR); \
+#define GEN3_IRQ_INIT(type, imr_val, ier_val) do { \
+ gen3_assert_iir_is_zero(dev_priv, type##IIR); \
I915_WRITE(type##IER, (ier_val)); \
I915_WRITE(type##IMR, (imr_val)); \
POSTING_READ(type##IMR); \
@@ -2876,7 +2876,7 @@ static void ibx_irq_reset(struct drm_i915_private *dev_priv)
if (HAS_PCH_NOP(dev_priv))
return;
- GEN5_IRQ_RESET(SDE);
+ GEN3_IRQ_RESET(SDE);
if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
I915_WRITE(SERR_INT, 0xffffffff);
@@ -2904,9 +2904,9 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
{
- GEN5_IRQ_RESET(GT);
+ GEN3_IRQ_RESET(GT);
if (INTEL_GEN(dev_priv) >= 6)
- GEN5_IRQ_RESET(GEN6_PM);
+ GEN3_IRQ_RESET(GEN6_PM);
}
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -2921,7 +2921,7 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
i9xx_pipestat_irq_reset(dev_priv);
- GEN5_IRQ_RESET(VLV_);
+ GEN3_IRQ_RESET(VLV_);
dev_priv->irq_mask = ~0;
}
@@ -2951,7 +2951,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
dev_priv->irq_mask = ~enable_mask;
- GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
+ GEN3_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
}
/* drm_dma.h hooks
@@ -2962,7 +2962,7 @@ static void ironlake_irq_reset(struct drm_device *dev)
I915_WRITE(HWSTAM, 0xffffffff);
- GEN5_IRQ_RESET(DE);
+ GEN3_IRQ_RESET(DE);
if (IS_GEN7(dev_priv))
I915_WRITE(GEN7_ERR_INT, 0xffffffff);
@@ -3009,9 +3009,9 @@ static void gen8_irq_reset(struct drm_device *dev)
POWER_DOMAIN_PIPE(pipe)))
GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
- GEN5_IRQ_RESET(GEN8_DE_PORT_);
- GEN5_IRQ_RESET(GEN8_DE_MISC_);
- GEN5_IRQ_RESET(GEN8_PCU_);
+ GEN3_IRQ_RESET(GEN8_DE_PORT_);
+ GEN3_IRQ_RESET(GEN8_DE_MISC_);
+ GEN3_IRQ_RESET(GEN8_PCU_);
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_reset(dev_priv);
@@ -3054,7 +3054,7 @@ static void cherryview_irq_preinstall(struct drm_device *dev)
gen8_gt_irq_reset(dev_priv);
- GEN5_IRQ_RESET(GEN8_PCU_);
+ GEN3_IRQ_RESET(GEN8_PCU_);
spin_lock_irq(&dev_priv->irq_lock);
if (dev_priv->display_irqs_enabled)
@@ -3249,7 +3249,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
else
mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
- gen5_assert_iir_is_zero(dev_priv, SDEIIR);
+ gen3_assert_iir_is_zero(dev_priv, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
@@ -3280,7 +3280,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
}
- GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
+ GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
if (INTEL_GEN(dev_priv) >= 6) {
/*
@@ -3293,7 +3293,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
}
dev_priv->pm_imr = 0xffffffff;
- GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
+ GEN3_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
}
}
@@ -3323,7 +3323,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
ibx_irq_pre_postinstall(dev);
- GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
+ GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
gen5_gt_irq_postinstall(dev);
@@ -3462,8 +3462,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
dev_priv->de_irq_mask[pipe],
de_pipe_enables);
- GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
- GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
+ GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
+ GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
if (IS_GEN9_LP(dev_priv))
bxt_hpd_detection_setup(dev_priv);
@@ -3549,7 +3549,7 @@ static void cherryview_irq_uninstall(struct drm_device *dev)
gen8_gt_irq_reset(dev_priv);
- GEN5_IRQ_RESET(GEN8_PCU_);
+ GEN3_IRQ_RESET(GEN8_PCU_);
spin_lock_irq(&dev_priv->irq_lock);
if (dev_priv->display_irqs_enabled)
--
2.13.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH 04/16] drm/i915: Use GEN3_IRQ_RESET/INIT on gen3/4
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (2 preceding siblings ...)
2017-08-18 18:36 ` [PATCH v2 03/16] drm/i915: s/GEN5/GEN3/ ville.syrjala
@ 2017-08-18 18:36 ` ville.syrjala
2017-08-18 19:16 ` Chris Wilson
2017-08-18 18:36 ` [PATCH 05/16] drm/i915: Introduce GEN2_IRQ_RESET/INIT ville.syrjala
` (17 subsequent siblings)
21 siblings, 1 reply; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Replace the manual IMR+IER+IIR write sequences with the appropriate
GEN3_IRQ_RESET/INIT macro invocations in gen3/4.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 24 ++++++------------------
1 file changed, 6 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8f4f1908cf55..b9790ab7a8d8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3705,9 +3705,7 @@ static void i915_irq_preinstall(struct drm_device * dev)
I915_WRITE16(HWSTAM, 0xeffe);
- I915_WRITE(IMR, 0xffffffff);
- I915_WRITE(IER, 0x0);
- POSTING_READ(IER);
+ GEN3_IRQ_RESET();
}
static int i915_irq_postinstall(struct drm_device *dev)
@@ -3739,9 +3737,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
}
- I915_WRITE(IMR, dev_priv->irq_mask);
- I915_WRITE(IER, enable_mask);
- POSTING_READ(IER);
+ GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
i915_enable_asle_pipestat(dev_priv);
@@ -3870,9 +3866,7 @@ static void i915_irq_uninstall(struct drm_device * dev)
I915_WRITE16(HWSTAM, 0xffff);
- I915_WRITE(IMR, 0xffffffff);
- I915_WRITE(IER, 0x0);
- I915_WRITE(IIR, I915_READ(IIR));
+ GEN3_IRQ_RESET();
}
static void i965_irq_preinstall(struct drm_device * dev)
@@ -3886,9 +3880,7 @@ static void i965_irq_preinstall(struct drm_device * dev)
I915_WRITE(HWSTAM, 0xeffe);
- I915_WRITE(IMR, 0xffffffff);
- I915_WRITE(IER, 0x0);
- POSTING_READ(IER);
+ GEN3_IRQ_RESET();
}
static int i965_irq_postinstall(struct drm_device *dev)
@@ -3933,9 +3925,7 @@ static int i965_irq_postinstall(struct drm_device *dev)
}
I915_WRITE(EMR, error_mask);
- I915_WRITE(IMR, dev_priv->irq_mask);
- I915_WRITE(IER, enable_mask);
- POSTING_READ(IER);
+ GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
POSTING_READ(PORT_HOTPLUG_EN);
@@ -4090,9 +4080,7 @@ static void i965_irq_uninstall(struct drm_device * dev)
I915_WRITE(HWSTAM, 0xffffffff);
- I915_WRITE(IMR, 0xffffffff);
- I915_WRITE(IER, 0x0);
- I915_WRITE(IIR, I915_READ(IIR));
+ GEN3_IRQ_RESET();
}
/**
--
2.13.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH 05/16] drm/i915: Introduce GEN2_IRQ_RESET/INIT
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (3 preceding siblings ...)
2017-08-18 18:36 ` [PATCH 04/16] drm/i915: Use GEN3_IRQ_RESET/INIT on gen3/4 ville.syrjala
@ 2017-08-18 18:36 ` ville.syrjala
2017-08-18 18:36 ` [PATCH 06/16] drm/i915: Setup EMR first on all gen2-4 ville.syrjala
` (16 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Unify the appearance of the gen2 irq code with the gen3+ code by
introducing the GEN2_IRQ_RESET/INIT macros.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 54 ++++++++++++++++++++++++++++++++---------
1 file changed, 42 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b9790ab7a8d8..4d09b88004b7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -136,6 +136,16 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
POSTING_READ(type##IIR); \
} while (0)
+#define GEN2_IRQ_RESET(type) do { \
+ I915_WRITE16(type##IMR, 0xffff); \
+ POSTING_READ16(type##IMR); \
+ I915_WRITE16(type##IER, 0); \
+ I915_WRITE16(type##IIR, 0xffff); \
+ POSTING_READ16(type##IIR); \
+ I915_WRITE16(type##IIR, 0xffff); \
+ POSTING_READ16(type##IIR); \
+} while (0)
+
/*
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
*/
@@ -155,6 +165,22 @@ static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
POSTING_READ(reg);
}
+static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv,
+ i915_reg_t reg)
+{
+ u16 val = I915_READ16(reg);
+
+ if (val == 0)
+ return;
+
+ WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
+ i915_mmio_reg_offset(reg), val);
+ I915_WRITE16(reg, 0xffff);
+ POSTING_READ16(reg);
+ I915_WRITE16(reg, 0xffff);
+ POSTING_READ16(reg);
+}
+
#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
gen3_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
@@ -169,6 +195,13 @@ static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
POSTING_READ(type##IMR); \
} while (0)
+#define GEN2_IRQ_INIT(type, imr_val, ier_val) do { \
+ gen2_assert_iir_is_zero(dev_priv, type##IIR); \
+ I915_WRITE16(type##IER, (ier_val)); \
+ I915_WRITE16(type##IMR, (imr_val)); \
+ POSTING_READ16(type##IMR); \
+} while (0)
+
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
@@ -3573,14 +3606,13 @@ static void i8xx_irq_preinstall(struct drm_device * dev)
i9xx_pipestat_irq_reset(dev_priv);
- I915_WRITE16(IMR, 0xffff);
- I915_WRITE16(IER, 0x0);
- POSTING_READ16(IER);
+ GEN2_IRQ_RESET();
}
static int i8xx_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ u16 enable_mask;
I915_WRITE16(EMR,
~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
@@ -3589,13 +3621,13 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
dev_priv->irq_mask =
~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
- I915_WRITE16(IMR, dev_priv->irq_mask);
- I915_WRITE16(IER,
- I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
- I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
- I915_USER_INTERRUPT);
- POSTING_READ16(IER);
+ enable_mask =
+ I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+ I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+ I915_USER_INTERRUPT;
+
+ GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
@@ -3687,9 +3719,7 @@ static void i8xx_irq_uninstall(struct drm_device * dev)
i9xx_pipestat_irq_reset(dev_priv);
- I915_WRITE16(IMR, 0xffff);
- I915_WRITE16(IER, 0x0);
- I915_WRITE16(IIR, I915_READ16(IIR));
+ GEN2_IRQ_RESET();
}
static void i915_irq_preinstall(struct drm_device * dev)
--
2.13.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH 06/16] drm/i915: Setup EMR first on all gen2-4
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (4 preceding siblings ...)
2017-08-18 18:36 ` [PATCH 05/16] drm/i915: Introduce GEN2_IRQ_RESET/INIT ville.syrjala
@ 2017-08-18 18:36 ` ville.syrjala
2017-08-18 18:36 ` [PATCH 07/16] drm/i915: Eliminate PORT_HOTPLUG_EN setup from gen3/4 irq_postinstall ville.syrjala
` (15 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Unify the appaerance of the gen2-4 irq postinstall hooks a little
bit by doing the EMR setup first on all the platforms.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 37 +++++++++++++++++++------------------
1 file changed, 19 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4d09b88004b7..33ecf5fcdd74 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3614,8 +3614,8 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev);
u16 enable_mask;
- I915_WRITE16(EMR,
- ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
+ I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE |
+ I915_ERROR_MEMORY_REFRESH));
/* Unmask the interrupts that we always want on. */
dev_priv->irq_mask =
@@ -3743,7 +3743,8 @@ static int i915_irq_postinstall(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev);
u32 enable_mask;
- I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
+ I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
+ I915_ERROR_MEMORY_REFRESH));
/* Unmask the interrupts that we always want on. */
dev_priv->irq_mask =
@@ -3919,6 +3920,21 @@ static int i965_irq_postinstall(struct drm_device *dev)
u32 enable_mask;
u32 error_mask;
+ /*
+ * Enable some error detection, note the instruction error mask
+ * bit is reserved, so we leave it masked.
+ */
+ if (IS_G4X(dev_priv)) {
+ error_mask = ~(GM45_ERROR_PAGE_TABLE |
+ GM45_ERROR_MEM_PRIV |
+ GM45_ERROR_CP_PRIV |
+ I915_ERROR_MEMORY_REFRESH);
+ } else {
+ error_mask = ~(I915_ERROR_PAGE_TABLE |
+ I915_ERROR_MEMORY_REFRESH);
+ }
+ I915_WRITE(EMR, error_mask);
+
/* Unmask the interrupts that we always want on. */
dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
I915_DISPLAY_PORT_INTERRUPT |
@@ -3940,21 +3956,6 @@ static int i965_irq_postinstall(struct drm_device *dev)
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
spin_unlock_irq(&dev_priv->irq_lock);
- /*
- * Enable some error detection, note the instruction error mask
- * bit is reserved, so we leave it masked.
- */
- if (IS_G4X(dev_priv)) {
- error_mask = ~(GM45_ERROR_PAGE_TABLE |
- GM45_ERROR_MEM_PRIV |
- GM45_ERROR_CP_PRIV |
- I915_ERROR_MEMORY_REFRESH);
- } else {
- error_mask = ~(I915_ERROR_PAGE_TABLE |
- I915_ERROR_MEMORY_REFRESH);
- }
- I915_WRITE(EMR, error_mask);
-
GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
--
2.13.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH 07/16] drm/i915: Eliminate PORT_HOTPLUG_EN setup from gen3/4 irq_postinstall
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (5 preceding siblings ...)
2017-08-18 18:36 ` [PATCH 06/16] drm/i915: Setup EMR first on all gen2-4 ville.syrjala
@ 2017-08-18 18:36 ` ville.syrjala
2017-08-18 18:36 ` [PATCH 08/16] drm/i915: Unify the appearance of gen3/4 irq_postistall hooks ville.syrjala
` (14 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We've already cleared PORT_HOTPLUG_EN in the .irq_preinstall hook
so doing it again in the .irq_postinstall is pointless.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 33ecf5fcdd74..d998eedcc5fd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3759,9 +3759,6 @@ static int i915_irq_postinstall(struct drm_device *dev)
I915_USER_INTERRUPT;
if (I915_HAS_HOTPLUG(dev_priv)) {
- i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
- POSTING_READ(PORT_HOTPLUG_EN);
-
/* Enable in IER... */
enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
/* and unmask in IMR */
@@ -3958,9 +3955,6 @@ static int i965_irq_postinstall(struct drm_device *dev)
GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
- i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
- POSTING_READ(PORT_HOTPLUG_EN);
-
i915_enable_asle_pipestat(dev_priv);
return 0;
--
2.13.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH 08/16] drm/i915: Unify the appearance of gen3/4 irq_postistall hooks
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (6 preceding siblings ...)
2017-08-18 18:36 ` [PATCH 07/16] drm/i915: Eliminate PORT_HOTPLUG_EN setup from gen3/4 irq_postinstall ville.syrjala
@ 2017-08-18 18:36 ` ville.syrjala
2017-08-18 18:36 ` [PATCH 09/16] drm/i915: Remove NULL dev_priv checks from irq_uninstall ville.syrjala
` (13 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Do the irq_mask/enable_mask setup in the same way on gen3/4, and also
reorder the steps to make the code more uniform.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 28 +++++++++++++++++-----------
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d998eedcc5fd..d38b03f9d305 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3767,8 +3767,6 @@ static int i915_irq_postinstall(struct drm_device *dev)
GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
- i915_enable_asle_pipestat(dev_priv);
-
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
spin_lock_irq(&dev_priv->irq_lock);
@@ -3776,6 +3774,8 @@ static int i915_irq_postinstall(struct drm_device *dev)
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
spin_unlock_irq(&dev_priv->irq_lock);
+ i915_enable_asle_pipestat(dev_priv);
+
return 0;
}
@@ -3933,18 +3933,26 @@ static int i965_irq_postinstall(struct drm_device *dev)
I915_WRITE(EMR, error_mask);
/* Unmask the interrupts that we always want on. */
- dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
- I915_DISPLAY_PORT_INTERRUPT |
- I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
- I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
- I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
+ dev_priv->irq_mask =
+ ~(I915_ASLE_INTERRUPT |
+ I915_DISPLAY_PORT_INTERRUPT |
+ I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+ I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+ I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
- enable_mask = ~dev_priv->irq_mask;
- enable_mask |= I915_USER_INTERRUPT;
+ enable_mask =
+ I915_ASLE_INTERRUPT |
+ I915_DISPLAY_PORT_INTERRUPT |
+ I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+ I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+ I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
+ I915_USER_INTERRUPT;
if (IS_G4X(dev_priv))
enable_mask |= I915_BSD_USER_INTERRUPT;
+ GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
+
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
spin_lock_irq(&dev_priv->irq_lock);
@@ -3953,8 +3961,6 @@ static int i965_irq_postinstall(struct drm_device *dev)
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
spin_unlock_irq(&dev_priv->irq_lock);
- GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
-
i915_enable_asle_pipestat(dev_priv);
return 0;
--
2.13.0
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^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH 09/16] drm/i915: Remove NULL dev_priv checks from irq_uninstall
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (7 preceding siblings ...)
2017-08-18 18:36 ` [PATCH 08/16] drm/i915: Unify the appearance of gen3/4 irq_postistall hooks ville.syrjala
@ 2017-08-18 18:36 ` ville.syrjala
2017-08-18 18:36 ` [PATCH 10/16] drm/i915: Extract PIPESTAT irq handling into separate functions ville.syrjala
` (12 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
There should be no way to land in irq_uninstall without a
valid dev_priv. Let's kill off the remaining checks, which are
probably some kind of UMS leftovers. Not all the irq_uninstall
hooks even had them anymore.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 19 -------------------
1 file changed, 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d38b03f9d305..4add2ad09798 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3542,11 +3542,6 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
static void gen8_irq_uninstall(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- if (!dev_priv)
- return;
-
gen8_irq_reset(dev);
}
@@ -3554,9 +3549,6 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- if (!dev_priv)
- return;
-
I915_WRITE(VLV_MASTER_IER, 0);
POSTING_READ(VLV_MASTER_IER);
@@ -3574,9 +3566,6 @@ static void cherryview_irq_uninstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- if (!dev_priv)
- return;
-
I915_WRITE(GEN8_MASTER_IRQ, 0);
POSTING_READ(GEN8_MASTER_IRQ);
@@ -3592,11 +3581,6 @@ static void cherryview_irq_uninstall(struct drm_device *dev)
static void ironlake_irq_uninstall(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- if (!dev_priv)
- return;
-
ironlake_irq_reset(dev);
}
@@ -4101,9 +4085,6 @@ static void i965_irq_uninstall(struct drm_device * dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- if (!dev_priv)
- return;
-
i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
--
2.13.0
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^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH 10/16] drm/i915: Extract PIPESTAT irq handling into separate functions
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (8 preceding siblings ...)
2017-08-18 18:36 ` [PATCH 09/16] drm/i915: Remove NULL dev_priv checks from irq_uninstall ville.syrjala
@ 2017-08-18 18:36 ` ville.syrjala
2017-08-18 18:37 ` [PATCH v2 11/16] drm/i915: Rewrite GMCH irq handlers to avoid loops ville.syrjala
` (11 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Extract the gen2-4 PIPESTAT irq handling into separate functions just
like we already do on VLV/CHV.
We can share valleyview_pipestat_irq_ack() on all gmch platforms to
actually read and clear the PIPESTAT status bits, so let's rename
it to i9xx_pipestat_irq_ack().
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 215 +++++++++++++++++-----------------------
1 file changed, 93 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4add2ad09798..b1c8c3a0ca9b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1755,8 +1755,8 @@ static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
}
}
-static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
- u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
+ u32 iir, u32 pipe_stats[I915_MAX_PIPES])
{
int pipe;
@@ -1813,6 +1813,74 @@ static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
spin_unlock(&dev_priv->irq_lock);
}
+static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
+ u16 iir, u32 pipe_stats[I915_MAX_PIPES])
+{
+ enum pipe pipe;
+
+ for_each_pipe(dev_priv, pipe) {
+ if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
+ drm_handle_vblank(&dev_priv->drm, pipe);
+
+ if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
+ i9xx_pipe_crc_irq_handler(dev_priv, pipe);
+
+ if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
+ intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
+ }
+}
+
+static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
+ u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+{
+ bool blc_event = false;
+ enum pipe pipe;
+
+ for_each_pipe(dev_priv, pipe) {
+ if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
+ drm_handle_vblank(&dev_priv->drm, pipe);
+
+ if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
+ blc_event = true;
+
+ if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
+ i9xx_pipe_crc_irq_handler(dev_priv, pipe);
+
+ if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
+ intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
+ }
+
+ if (blc_event || (iir & I915_ASLE_INTERRUPT))
+ intel_opregion_asle_intr(dev_priv);
+}
+
+static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
+ u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+{
+ bool blc_event = false;
+ enum pipe pipe;
+
+ for_each_pipe(dev_priv, pipe) {
+ if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
+ drm_handle_vblank(&dev_priv->drm, pipe);
+
+ if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
+ blc_event = true;
+
+ if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
+ i9xx_pipe_crc_irq_handler(dev_priv, pipe);
+
+ if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
+ intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
+ }
+
+ if (blc_event || (iir & I915_ASLE_INTERRUPT))
+ intel_opregion_asle_intr(dev_priv);
+
+ if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
+ gmbus_irq_handler(dev_priv);
+}
+
static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
u32 pipe_stats[I915_MAX_PIPES])
{
@@ -1928,7 +1996,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
/* Call regardless, as some status bits might not be
* signalled in iir */
- valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
+ i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
if (iir & (I915_LPE_PIPE_A_INTERRUPT |
I915_LPE_PIPE_B_INTERRUPT))
@@ -2012,7 +2080,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
/* Call regardless, as some status bits might not be
* signalled in iir */
- valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
+ i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
if (iir & (I915_LPE_PIPE_A_INTERRUPT |
I915_LPE_PIPE_B_INTERRUPT |
@@ -3628,8 +3696,6 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
struct drm_device *dev = arg;
struct drm_i915_private *dev_priv = to_i915(dev);
u16 iir, new_iir;
- u32 pipe_stats[2];
- int pipe;
irqreturn_t ret;
if (!intel_irqs_enabled(dev_priv))
@@ -3644,26 +3710,14 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
goto out;
while (iir) {
- /* Can't rely on pipestat interrupt bit in iir as it might
- * have been cleared after the pipestat interrupt was received.
- * It doesn't set the bit in iir again, but it still produces
- * interrupts (for non-MSI).
- */
- spin_lock(&dev_priv->irq_lock);
+ u32 pipe_stats[I915_MAX_PIPES] = {};
+
if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
- for_each_pipe(dev_priv, pipe) {
- i915_reg_t reg = PIPESTAT(pipe);
- pipe_stats[pipe] = I915_READ(reg);
-
- /*
- * Clear the PIPE*STAT regs before the IIR
- */
- if (pipe_stats[pipe] & 0x8000ffff)
- I915_WRITE(reg, pipe_stats[pipe]);
- }
- spin_unlock(&dev_priv->irq_lock);
+ /* Call regardless, as some status bits might not be
+ * signalled in iir */
+ i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
I915_WRITE16(IIR, iir);
new_iir = I915_READ16(IIR); /* Flush posted writes */
@@ -3671,21 +3725,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
if (iir & I915_USER_INTERRUPT)
notify_ring(dev_priv->engine[RCS]);
- for_each_pipe(dev_priv, pipe) {
- int plane = pipe;
- if (HAS_FBC(dev_priv))
- plane = !plane;
-
- if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
- drm_handle_vblank(&dev_priv->drm, pipe);
-
- if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
- i9xx_pipe_crc_irq_handler(dev_priv, pipe);
-
- if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
- intel_cpu_fifo_underrun_irq_handler(dev_priv,
- pipe);
- }
+ i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
iir = new_iir;
}
@@ -3767,8 +3807,8 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
{
struct drm_device *dev = arg;
struct drm_i915_private *dev_priv = to_i915(dev);
- u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
- int pipe, ret = IRQ_NONE;
+ u32 iir, new_iir;
+ int ret = IRQ_NONE;
if (!intel_irqs_enabled(dev_priv))
return IRQ_NONE;
@@ -3778,29 +3818,15 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
iir = I915_READ(IIR);
do {
- bool irq_received = (iir) != 0;
- bool blc_event = false;
+ u32 pipe_stats[I915_MAX_PIPES] = {};
+ bool irq_received = iir != 0;
- /* Can't rely on pipestat interrupt bit in iir as it might
- * have been cleared after the pipestat interrupt was received.
- * It doesn't set the bit in iir again, but it still produces
- * interrupts (for non-MSI).
- */
- spin_lock(&dev_priv->irq_lock);
if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
- for_each_pipe(dev_priv, pipe) {
- i915_reg_t reg = PIPESTAT(pipe);
- pipe_stats[pipe] = I915_READ(reg);
-
- /* Clear the PIPE*STAT regs before the IIR */
- if (pipe_stats[pipe] & 0x8000ffff) {
- I915_WRITE(reg, pipe_stats[pipe]);
- irq_received = true;
- }
- }
- spin_unlock(&dev_priv->irq_lock);
+ /* Call regardless, as some status bits might not be
+ * signalled in iir */
+ i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
if (!irq_received)
break;
@@ -3819,27 +3845,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
if (iir & I915_USER_INTERRUPT)
notify_ring(dev_priv->engine[RCS]);
- for_each_pipe(dev_priv, pipe) {
- int plane = pipe;
- if (HAS_FBC(dev_priv))
- plane = !plane;
-
- if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
- drm_handle_vblank(&dev_priv->drm, pipe);
-
- if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
- blc_event = true;
-
- if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
- i9xx_pipe_crc_irq_handler(dev_priv, pipe);
-
- if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
- intel_cpu_fifo_underrun_irq_handler(dev_priv,
- pipe);
- }
-
- if (blc_event || (iir & I915_ASLE_INTERRUPT))
- intel_opregion_asle_intr(dev_priv);
+ i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
/* With MSI, interrupts are only generated when iir
* transitions from zero to nonzero. If another bit got
@@ -3980,8 +3986,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
struct drm_device *dev = arg;
struct drm_i915_private *dev_priv = to_i915(dev);
u32 iir, new_iir;
- u32 pipe_stats[I915_MAX_PIPES];
- int ret = IRQ_NONE, pipe;
+ int ret = IRQ_NONE;
if (!intel_irqs_enabled(dev_priv))
return IRQ_NONE;
@@ -3992,31 +3997,15 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
iir = I915_READ(IIR);
for (;;) {
- bool irq_received = (iir) != 0;
- bool blc_event = false;
+ u32 pipe_stats[I915_MAX_PIPES] = {};
+ bool irq_received = iir != 0;
- /* Can't rely on pipestat interrupt bit in iir as it might
- * have been cleared after the pipestat interrupt was received.
- * It doesn't set the bit in iir again, but it still produces
- * interrupts (for non-MSI).
- */
- spin_lock(&dev_priv->irq_lock);
if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
- for_each_pipe(dev_priv, pipe) {
- i915_reg_t reg = PIPESTAT(pipe);
- pipe_stats[pipe] = I915_READ(reg);
-
- /*
- * Clear the PIPE*STAT regs before the IIR
- */
- if (pipe_stats[pipe] & 0x8000ffff) {
- I915_WRITE(reg, pipe_stats[pipe]);
- irq_received = true;
- }
- }
- spin_unlock(&dev_priv->irq_lock);
+ /* Call regardless, as some status bits might not be
+ * signalled in iir */
+ i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
if (!irq_received)
break;
@@ -4038,25 +4027,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
if (iir & I915_BSD_USER_INTERRUPT)
notify_ring(dev_priv->engine[VCS]);
- for_each_pipe(dev_priv, pipe) {
- if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
- drm_handle_vblank(&dev_priv->drm, pipe);
-
- if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
- blc_event = true;
-
- if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
- i9xx_pipe_crc_irq_handler(dev_priv, pipe);
-
- if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
- intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
- }
-
- if (blc_event || (iir & I915_ASLE_INTERRUPT))
- intel_opregion_asle_intr(dev_priv);
-
- if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
- gmbus_irq_handler(dev_priv);
+ i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
/* With MSI, interrupts are only generated when iir
* transitions from zero to nonzero. If another bit got
--
2.13.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH v2 11/16] drm/i915: Rewrite GMCH irq handlers to avoid loops
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (9 preceding siblings ...)
2017-08-18 18:36 ` [PATCH 10/16] drm/i915: Extract PIPESTAT irq handling into separate functions ville.syrjala
@ 2017-08-18 18:37 ` ville.syrjala
2017-08-18 19:20 ` Chris Wilson
2017-08-18 18:37 ` [PATCH 12/16] drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode ville.syrjala
` (10 subsequent siblings)
21 siblings, 1 reply; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Eliminate the loops from the gen2-3 irq handlers. Since we don't use
MSI anymore on these platforms, and thus the CPU interrupt will be level
triggered, we shouldn't need to play any tricks with IER to induce edges
from IIR. IIR itself still detects only edges from PIPESTAT & co. on
gen4 but since IIR is double buffered and we only clear one bit per irq
handler invocation we can use the normal "clear PIPESTAT & co. -> clear
IIR" approach to ack the interrupts. On gen2 everything is level
triggered, and gen3 presumably follows either the gen2 or gen4 approach
since nothing else would really make sense.
v2: Drop the IER tricks since we no longer use MSI
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 143 ++++++++++++++--------------------------
1 file changed, 51 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b1c8c3a0ca9b..ec5f9675581a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3695,8 +3695,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
{
struct drm_device *dev = arg;
struct drm_i915_private *dev_priv = to_i915(dev);
- u16 iir, new_iir;
- irqreturn_t ret;
+ irqreturn_t ret = IRQ_NONE;
if (!intel_irqs_enabled(dev_priv))
return IRQ_NONE;
@@ -3704,34 +3703,31 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
disable_rpm_wakeref_asserts(dev_priv);
- ret = IRQ_NONE;
- iir = I915_READ16(IIR);
- if (iir == 0)
- goto out;
-
- while (iir) {
+ do {
u32 pipe_stats[I915_MAX_PIPES] = {};
+ u16 iir;
- if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
- DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
+ iir = I915_READ16(IIR);
+ if (iir == 0)
+ break;
+
+ ret = IRQ_HANDLED;
/* Call regardless, as some status bits might not be
* signalled in iir */
i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
I915_WRITE16(IIR, iir);
- new_iir = I915_READ16(IIR); /* Flush posted writes */
if (iir & I915_USER_INTERRUPT)
notify_ring(dev_priv->engine[RCS]);
- i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
+ if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
+ DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
- iir = new_iir;
- }
- ret = IRQ_HANDLED;
+ i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
+ } while (0);
-out:
enable_rpm_wakeref_asserts(dev_priv);
return ret;
@@ -3807,8 +3803,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
{
struct drm_device *dev = arg;
struct drm_i915_private *dev_priv = to_i915(dev);
- u32 iir, new_iir;
- int ret = IRQ_NONE;
+ irqreturn_t ret = IRQ_NONE;
if (!intel_irqs_enabled(dev_priv))
return IRQ_NONE;
@@ -3816,55 +3811,38 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
disable_rpm_wakeref_asserts(dev_priv);
- iir = I915_READ(IIR);
do {
u32 pipe_stats[I915_MAX_PIPES] = {};
- bool irq_received = iir != 0;
+ u32 hotplug_status = 0;
+ u32 iir;
- if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
- DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
+ iir = I915_READ(IIR);
+ if (iir == 0)
+ break;
+
+ ret = IRQ_HANDLED;
+
+ if (I915_HAS_HOTPLUG(dev_priv) &&
+ iir & I915_DISPLAY_PORT_INTERRUPT)
+ hotplug_status = i9xx_hpd_irq_ack(dev_priv);
/* Call regardless, as some status bits might not be
* signalled in iir */
i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
- if (!irq_received)
- break;
-
- /* Consume port. Then clear IIR or we'll miss events */
- if (I915_HAS_HOTPLUG(dev_priv) &&
- iir & I915_DISPLAY_PORT_INTERRUPT) {
- u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
- if (hotplug_status)
- i9xx_hpd_irq_handler(dev_priv, hotplug_status);
- }
-
I915_WRITE(IIR, iir);
- new_iir = I915_READ(IIR); /* Flush posted writes */
if (iir & I915_USER_INTERRUPT)
notify_ring(dev_priv->engine[RCS]);
- i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
+ if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
+ DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
- /* With MSI, interrupts are only generated when iir
- * transitions from zero to nonzero. If another bit got
- * set while we were handling the existing iir bits, then
- * we would never get another interrupt.
- *
- * This is fine on non-MSI as well, as if we hit this path
- * we avoid exiting the interrupt handler only to generate
- * another one.
- *
- * Note that for MSI this could cause a stray interrupt report
- * if an interrupt landed in the time between writing IIR and
- * the posting read. This should be rare enough to never
- * trigger the 99% of 100,000 interrupts test for disabling
- * stray interrupts.
- */
- ret = IRQ_HANDLED;
- iir = new_iir;
- } while (iir);
+ if (hotplug_status)
+ i9xx_hpd_irq_handler(dev_priv, hotplug_status);
+
+ i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
+ } while (0);
enable_rpm_wakeref_asserts(dev_priv);
@@ -3985,8 +3963,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
{
struct drm_device *dev = arg;
struct drm_i915_private *dev_priv = to_i915(dev);
- u32 iir, new_iir;
- int ret = IRQ_NONE;
+ irqreturn_t ret = IRQ_NONE;
if (!intel_irqs_enabled(dev_priv))
return IRQ_NONE;
@@ -3994,58 +3971,40 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
disable_rpm_wakeref_asserts(dev_priv);
- iir = I915_READ(IIR);
-
- for (;;) {
+ do {
u32 pipe_stats[I915_MAX_PIPES] = {};
- bool irq_received = iir != 0;
-
- if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
- DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
-
- /* Call regardless, as some status bits might not be
- * signalled in iir */
- i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
+ u32 hotplug_status = 0;
+ u32 iir;
- if (!irq_received)
+ iir = I915_READ(IIR);
+ if (iir == 0)
break;
ret = IRQ_HANDLED;
- /* Consume port. Then clear IIR or we'll miss events */
- if (iir & I915_DISPLAY_PORT_INTERRUPT) {
- u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
- if (hotplug_status)
- i9xx_hpd_irq_handler(dev_priv, hotplug_status);
- }
+ if (iir & I915_DISPLAY_PORT_INTERRUPT)
+ hotplug_status = i9xx_hpd_irq_ack(dev_priv);
+
+ /* Call regardless, as some status bits might not be
+ * signalled in iir */
+ i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
I915_WRITE(IIR, iir);
- new_iir = I915_READ(IIR); /* Flush posted writes */
if (iir & I915_USER_INTERRUPT)
notify_ring(dev_priv->engine[RCS]);
+
if (iir & I915_BSD_USER_INTERRUPT)
notify_ring(dev_priv->engine[VCS]);
- i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
+ if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
+ DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
- /* With MSI, interrupts are only generated when iir
- * transitions from zero to nonzero. If another bit got
- * set while we were handling the existing iir bits, then
- * we would never get another interrupt.
- *
- * This is fine on non-MSI as well, as if we hit this path
- * we avoid exiting the interrupt handler only to generate
- * another one.
- *
- * Note that for MSI this could cause a stray interrupt report
- * if an interrupt landed in the time between writing IIR and
- * the posting read. This should be rare enough to never
- * trigger the 99% of 100,000 interrupts test for disabling
- * stray interrupts.
- */
- iir = new_iir;
- }
+ if (hotplug_status)
+ i9xx_hpd_irq_handler(dev_priv, hotplug_status);
+
+ i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
+ } while (0);
enable_rpm_wakeref_asserts(dev_priv);
--
2.13.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH v2 11/16] drm/i915: Rewrite GMCH irq handlers to avoid loops
2017-08-18 18:37 ` [PATCH v2 11/16] drm/i915: Rewrite GMCH irq handlers to avoid loops ville.syrjala
@ 2017-08-18 19:20 ` Chris Wilson
0 siblings, 0 replies; 35+ messages in thread
From: Chris Wilson @ 2017-08-18 19:20 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
Quoting ville.syrjala@linux.intel.com (2017-08-18 19:37:00)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Eliminate the loops from the gen2-3 irq handlers. Since we don't use
> MSI anymore on these platforms, and thus the CPU interrupt will be level
> triggered, we shouldn't need to play any tricks with IER to induce edges
> from IIR. IIR itself still detects only edges from PIPESTAT & co. on
> gen4 but since IIR is double buffered and we only clear one bit per irq
> handler invocation we can use the normal "clear PIPESTAT & co. -> clear
> IIR" approach to ack the interrupts. On gen2 everything is level
> triggered, and gen3 presumably follows either the gen2 or gen4 approach
> since nothing else would really make sense.
>
> v2: Drop the IER tricks since we no longer use MSI
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> #v1
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 12/16] drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (10 preceding siblings ...)
2017-08-18 18:37 ` [PATCH v2 11/16] drm/i915: Rewrite GMCH irq handlers to avoid loops ville.syrjala
@ 2017-08-18 18:37 ` ville.syrjala
2017-08-18 18:37 ` [PATCH 13/16] drm/i915: Gen3 HWSTAM is actually 32 bits ville.syrjala
` (9 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The execlist code already masks everything in the ring HWSTAM, but
the ringbuffer code doesn't. Let's go ahead and do that. Pre-gen6
platforms setup HWSTAM during irq setup already since there's just
the one register, and it also contains bits for non-ring interrupts.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cdf084ef5aae..72fecd84094d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -427,6 +427,9 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
mmio = RING_HWS_PGA(engine->mmio_base);
}
+ if (INTEL_GEN(dev_priv) >= 6)
+ I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
+
I915_WRITE(mmio, engine->status_page.ggtt_offset);
POSTING_READ(mmio);
--
2.13.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH 13/16] drm/i915: Gen3 HWSTAM is actually 32 bits
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (11 preceding siblings ...)
2017-08-18 18:37 ` [PATCH 12/16] drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode ville.syrjala
@ 2017-08-18 18:37 ` ville.syrjala
2017-08-18 18:37 ` [PATCH 14/16] drm/i915: Clean up the HWSTAM mess ville.syrjala
` (8 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Bspec claims that HWSTAM is only 16 bits on gen3, but the other
interrupts registers are 32 bits and there are 18 valid interrupt
bits. Hence a 16 bit HWSTAM wouldn't be able to contain all the
bits, so it seems the spec is incorrect about the size of the
register. And indeed I can clear bits 16 and 17 just fine with
a 32 bit write. So let's adjust the code to treat the register
as 32 bits.
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ec5f9675581a..1963456f479a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3753,7 +3753,7 @@ static void i915_irq_preinstall(struct drm_device * dev)
i9xx_pipestat_irq_reset(dev_priv);
- I915_WRITE16(HWSTAM, 0xeffe);
+ I915_WRITE(HWSTAM, 0xffffeffe);
GEN3_IRQ_RESET();
}
@@ -3860,7 +3860,7 @@ static void i915_irq_uninstall(struct drm_device * dev)
i9xx_pipestat_irq_reset(dev_priv);
- I915_WRITE16(HWSTAM, 0xffff);
+ I915_WRITE(HWSTAM, 0xffffffff);
GEN3_IRQ_RESET();
}
--
2.13.0
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^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH 14/16] drm/i915: Clean up the HWSTAM mess
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (12 preceding siblings ...)
2017-08-18 18:37 ` [PATCH 13/16] drm/i915: Gen3 HWSTAM is actually 32 bits ville.syrjala
@ 2017-08-18 18:37 ` ville.syrjala
2017-08-18 18:37 ` [PATCH 15/16] drm/i915: Remove duplicated irq_preinstall/uninstall hooks ville.syrjala
` (7 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently we're unmasking some random looking bits in HWSTAM
on gen3/4/5. The two bits we apparently unmask are 0 and 12,
and also bits 16-31 on gen4/5.
What those bits do depends on the gen as follows:
bit 0: Breakpoint (gen2), ASLE (gen3), reserved (gen4), render user interrupt (gen5)
bit 12: Sync flush statusa (gen2-4), reserved (gen5)
bit 16-31: The ones that can unmasked seem to be mostly some
display stuff on gen4. Bit 18 is the PIPE_CONTROL notify,
which might be the only intresting one. On gen5 all the
bits are reserved.
So I don't know whether we actually depend on that status page write
somehow. Extra seqno coherency by accident perhaps? Except we don't
even unmask the user interrupt bit in HWSTAM except on gen5, and
sync flush isn't something we use normally, so seems unlikely. So
let's just assume we don't need any of this and mask everything in
HWSTAM.
From gen6 onwards there's a separate HWSTAM for each engine, and so
we deal with them during the engine setup.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1963456f479a..a2f0548ee942 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3061,7 +3061,8 @@ static void ironlake_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- I915_WRITE(HWSTAM, 0xffffffff);
+ if (IS_GEN5(dev_priv))
+ I915_WRITE(HWSTAM, 0xffffffff);
GEN3_IRQ_RESET(DE);
if (IS_GEN7(dev_priv))
@@ -3420,8 +3421,6 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
dev_priv->irq_mask = ~display_mask;
- I915_WRITE(HWSTAM, 0xeffe);
-
ibx_irq_pre_postinstall(dev);
GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
@@ -3622,8 +3621,6 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
gen5_gt_irq_reset(dev_priv);
- I915_WRITE(HWSTAM, 0xffffffff);
-
spin_lock_irq(&dev_priv->irq_lock);
if (dev_priv->display_irqs_enabled)
vlv_display_irq_reset(dev_priv);
@@ -3658,6 +3655,8 @@ static void i8xx_irq_preinstall(struct drm_device * dev)
i9xx_pipestat_irq_reset(dev_priv);
+ I915_WRITE16(HWSTAM, 0xffff);
+
GEN2_IRQ_RESET();
}
@@ -3739,6 +3738,8 @@ static void i8xx_irq_uninstall(struct drm_device * dev)
i9xx_pipestat_irq_reset(dev_priv);
+ I915_WRITE16(HWSTAM, 0xffff);
+
GEN2_IRQ_RESET();
}
@@ -3753,7 +3754,7 @@ static void i915_irq_preinstall(struct drm_device * dev)
i9xx_pipestat_irq_reset(dev_priv);
- I915_WRITE(HWSTAM, 0xffffeffe);
+ I915_WRITE(HWSTAM, 0xffffffff);
GEN3_IRQ_RESET();
}
@@ -3874,7 +3875,7 @@ static void i965_irq_preinstall(struct drm_device * dev)
i9xx_pipestat_irq_reset(dev_priv);
- I915_WRITE(HWSTAM, 0xeffe);
+ I915_WRITE(HWSTAM, 0xffffffff);
GEN3_IRQ_RESET();
}
--
2.13.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH 15/16] drm/i915: Remove duplicated irq_preinstall/uninstall hooks
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (13 preceding siblings ...)
2017-08-18 18:37 ` [PATCH 14/16] drm/i915: Clean up the HWSTAM mess ville.syrjala
@ 2017-08-18 18:37 ` ville.syrjala
2017-08-18 18:37 ` [PATCH 16/16] drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4x ville.syrjala
` (6 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
All the irq_preinstall and irq_uninstall hooks are now identical. Let's
just rename them all the irq_reset and remove the pointless duplicates.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 117 ++++++----------------------------------
1 file changed, 17 insertions(+), 100 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a2f0548ee942..d145bc1bd0fc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3073,7 +3073,7 @@ static void ironlake_irq_reset(struct drm_device *dev)
ibx_irq_reset(dev_priv);
}
-static void valleyview_irq_preinstall(struct drm_device *dev)
+static void valleyview_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3147,7 +3147,7 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
synchronize_irq(dev_priv->drm.irq);
}
-static void cherryview_irq_preinstall(struct drm_device *dev)
+static void cherryview_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3607,49 +3607,7 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
return 0;
}
-static void gen8_irq_uninstall(struct drm_device *dev)
-{
- gen8_irq_reset(dev);
-}
-
-static void valleyview_irq_uninstall(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- I915_WRITE(VLV_MASTER_IER, 0);
- POSTING_READ(VLV_MASTER_IER);
-
- gen5_gt_irq_reset(dev_priv);
-
- spin_lock_irq(&dev_priv->irq_lock);
- if (dev_priv->display_irqs_enabled)
- vlv_display_irq_reset(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
-}
-
-static void cherryview_irq_uninstall(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- I915_WRITE(GEN8_MASTER_IRQ, 0);
- POSTING_READ(GEN8_MASTER_IRQ);
-
- gen8_gt_irq_reset(dev_priv);
-
- GEN3_IRQ_RESET(GEN8_PCU_);
-
- spin_lock_irq(&dev_priv->irq_lock);
- if (dev_priv->display_irqs_enabled)
- vlv_display_irq_reset(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
-}
-
-static void ironlake_irq_uninstall(struct drm_device *dev)
-{
- ironlake_irq_reset(dev);
-}
-
-static void i8xx_irq_preinstall(struct drm_device * dev)
+static void i8xx_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3732,18 +3690,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
return ret;
}
-static void i8xx_irq_uninstall(struct drm_device * dev)
-{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- i9xx_pipestat_irq_reset(dev_priv);
-
- I915_WRITE16(HWSTAM, 0xffff);
-
- GEN2_IRQ_RESET();
-}
-
-static void i915_irq_preinstall(struct drm_device * dev)
+static void i915_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3850,23 +3797,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
return ret;
}
-static void i915_irq_uninstall(struct drm_device * dev)
-{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- if (I915_HAS_HOTPLUG(dev_priv)) {
- i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
- I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
- }
-
- i9xx_pipestat_irq_reset(dev_priv);
-
- I915_WRITE(HWSTAM, 0xffffffff);
-
- GEN3_IRQ_RESET();
-}
-
-static void i965_irq_preinstall(struct drm_device * dev)
+static void i965_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -4012,20 +3943,6 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
return ret;
}
-static void i965_irq_uninstall(struct drm_device * dev)
-{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
- I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
-
- i9xx_pipestat_irq_reset(dev_priv);
-
- I915_WRITE(HWSTAM, 0xffffffff);
-
- GEN3_IRQ_RESET();
-}
-
/**
* intel_irq_init - initializes irq support
* @dev_priv: i915 device instance
@@ -4106,17 +4023,17 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (IS_CHERRYVIEW(dev_priv)) {
dev->driver->irq_handler = cherryview_irq_handler;
- dev->driver->irq_preinstall = cherryview_irq_preinstall;
+ dev->driver->irq_preinstall = cherryview_irq_reset;
dev->driver->irq_postinstall = cherryview_irq_postinstall;
- dev->driver->irq_uninstall = cherryview_irq_uninstall;
+ dev->driver->irq_uninstall = cherryview_irq_reset;
dev->driver->enable_vblank = i965_enable_vblank;
dev->driver->disable_vblank = i965_disable_vblank;
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
} else if (IS_VALLEYVIEW(dev_priv)) {
dev->driver->irq_handler = valleyview_irq_handler;
- dev->driver->irq_preinstall = valleyview_irq_preinstall;
+ dev->driver->irq_preinstall = valleyview_irq_reset;
dev->driver->irq_postinstall = valleyview_irq_postinstall;
- dev->driver->irq_uninstall = valleyview_irq_uninstall;
+ dev->driver->irq_uninstall = valleyview_irq_reset;
dev->driver->enable_vblank = i965_enable_vblank;
dev->driver->disable_vblank = i965_disable_vblank;
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
@@ -4124,7 +4041,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->irq_handler = gen8_irq_handler;
dev->driver->irq_preinstall = gen8_irq_reset;
dev->driver->irq_postinstall = gen8_irq_postinstall;
- dev->driver->irq_uninstall = gen8_irq_uninstall;
+ dev->driver->irq_uninstall = gen8_irq_reset;
dev->driver->enable_vblank = gen8_enable_vblank;
dev->driver->disable_vblank = gen8_disable_vblank;
if (IS_GEN9_LP(dev_priv))
@@ -4138,29 +4055,29 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->irq_handler = ironlake_irq_handler;
dev->driver->irq_preinstall = ironlake_irq_reset;
dev->driver->irq_postinstall = ironlake_irq_postinstall;
- dev->driver->irq_uninstall = ironlake_irq_uninstall;
+ dev->driver->irq_uninstall = ironlake_irq_reset;
dev->driver->enable_vblank = ironlake_enable_vblank;
dev->driver->disable_vblank = ironlake_disable_vblank;
dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
} else {
if (IS_GEN2(dev_priv)) {
- dev->driver->irq_preinstall = i8xx_irq_preinstall;
+ dev->driver->irq_preinstall = i8xx_irq_reset;
dev->driver->irq_postinstall = i8xx_irq_postinstall;
dev->driver->irq_handler = i8xx_irq_handler;
- dev->driver->irq_uninstall = i8xx_irq_uninstall;
+ dev->driver->irq_uninstall = i8xx_irq_reset;
dev->driver->enable_vblank = i8xx_enable_vblank;
dev->driver->disable_vblank = i8xx_disable_vblank;
} else if (IS_GEN3(dev_priv)) {
- dev->driver->irq_preinstall = i915_irq_preinstall;
+ dev->driver->irq_preinstall = i915_irq_reset;
dev->driver->irq_postinstall = i915_irq_postinstall;
- dev->driver->irq_uninstall = i915_irq_uninstall;
+ dev->driver->irq_uninstall = i915_irq_reset;
dev->driver->irq_handler = i915_irq_handler;
dev->driver->enable_vblank = i8xx_enable_vblank;
dev->driver->disable_vblank = i8xx_disable_vblank;
} else {
- dev->driver->irq_preinstall = i965_irq_preinstall;
+ dev->driver->irq_preinstall = i965_irq_reset;
dev->driver->irq_postinstall = i965_irq_postinstall;
- dev->driver->irq_uninstall = i965_irq_uninstall;
+ dev->driver->irq_uninstall = i965_irq_reset;
dev->driver->irq_handler = i965_irq_handler;
dev->driver->enable_vblank = i965_enable_vblank;
dev->driver->disable_vblank = i965_disable_vblank;
--
2.13.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH 16/16] drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4x
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (14 preceding siblings ...)
2017-08-18 18:37 ` [PATCH 15/16] drm/i915: Remove duplicated irq_preinstall/uninstall hooks ville.syrjala
@ 2017-08-18 18:37 ` ville.syrjala
2017-08-18 18:44 ` Jiri Kosina
2017-08-18 19:41 ` ✓ Fi.CI.BAT: success for drm/i915: Redo old gmch irq handling (rev2) Patchwork
` (5 subsequent siblings)
21 siblings, 1 reply; 35+ messages in thread
From: ville.syrjala @ 2017-08-18 18:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter, Jiri Kosina
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Now that we're not using MSI anymore on gen4 we can start
using GMBUS and AUX interrupts again. These were disable on
account of them causing the hardware to somehow generate
legacy interrupts even when MSI was enabled.
See commit c12aba5aa0e6 ("drm/i915: stop using GMBUS IRQs on Gen4
chips") and commit 4e6b788c3f23 ("drm/i915: Disable dp aux irq on
g4x") for more details.
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jiri Kosina <jkosina@suse.cz>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 8 +++++---
drivers/gpu/drm/i915/i915_pci.c | 6 ------
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5b70bb9089fe..06ed02e383b9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -759,7 +759,6 @@ struct intel_csr {
func(has_fpga_dbg); \
func(has_full_ppgtt); \
func(has_full_48bit_ppgtt); \
- func(has_gmbus_irq); \
func(has_gmch_display); \
func(has_guc); \
func(has_guc_ct); \
@@ -3032,9 +3031,12 @@ intel_info(const struct drm_i915_private *dev_priv)
* even when in MSI mode. This results in spurious interrupt warnings if the
* legacy irq no. is shared with another device. The kernel then disables that
* interrupt source and so prevents the other device from working properly.
+ *
+ * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
+ * interrupts.
*/
-#define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
-#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
+#define HAS_AUX_IRQ(dev_priv) true
+#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming.
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 09d97e0990b7..77ef1450c48f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -195,7 +195,6 @@ static const struct intel_device_info intel_gm45_info = {
#define GEN5_FEATURES \
.gen = 5, .num_pipes = 2, \
.has_hotplug = 1, \
- .has_gmbus_irq = 1, \
.ring_mask = RENDER_RING | BSD_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
@@ -219,7 +218,6 @@ static const struct intel_device_info intel_ironlake_m_info = {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
- .has_gmbus_irq = 1, \
.has_aliasing_ppgtt = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
@@ -243,7 +241,6 @@ static const struct intel_device_info intel_sandybridge_m_info = {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
- .has_gmbus_irq = 1, \
.has_aliasing_ppgtt = 1, \
.has_full_ppgtt = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -277,7 +274,6 @@ static const struct intel_device_info intel_valleyview_info = {
.has_psr = 1,
.has_runtime_pm = 1,
.has_rc6 = 1,
- .has_gmbus_irq = 1,
.has_gmch_display = 1,
.has_hotplug = 1,
.has_aliasing_ppgtt = 1,
@@ -338,7 +334,6 @@ static const struct intel_device_info intel_cherryview_info = {
.has_runtime_pm = 1,
.has_resource_streamer = 1,
.has_rc6 = 1,
- .has_gmbus_irq = 1,
.has_logical_ring_contexts = 1,
.has_gmch_display = 1,
.has_aliasing_ppgtt = 1,
@@ -383,7 +378,6 @@ static const struct intel_device_info intel_skylake_gt3_info = {
.has_resource_streamer = 1, \
.has_rc6 = 1, \
.has_dp_mst = 1, \
- .has_gmbus_irq = 1, \
.has_logical_ring_contexts = 1, \
.has_guc = 1, \
.has_aliasing_ppgtt = 1, \
--
2.13.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH 16/16] drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4x
2017-08-18 18:37 ` [PATCH 16/16] drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4x ville.syrjala
@ 2017-08-18 18:44 ` Jiri Kosina
0 siblings, 0 replies; 35+ messages in thread
From: Jiri Kosina @ 2017-08-18 18:44 UTC (permalink / raw)
To: ville.syrjala; +Cc: Daniel Vetter, intel-gfx
On Fri, 18 Aug 2017, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that we're not using MSI anymore on gen4 we can start
> using GMBUS and AUX interrupts again. These were disable on
> account of them causing the hardware to somehow generate
> legacy interrupts even when MSI was enabled.
>
> See commit c12aba5aa0e6 ("drm/i915: stop using GMBUS IRQs on Gen4
> chips") and commit 4e6b788c3f23 ("drm/i915: Disable dp aux irq on
> g4x") for more details.
I unfortunately don't have the HW where I used to reproduce the spurious
IRQs any more. It was thinkpad x200s, 7470-BN2 model.
--
Jiri Kosina
SUSE Labs
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Redo old gmch irq handling (rev2)
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (15 preceding siblings ...)
2017-08-18 18:37 ` [PATCH 16/16] drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4x ville.syrjala
@ 2017-08-18 19:41 ` Patchwork
2017-08-18 20:19 ` Chris Wilson
2017-09-01 10:06 ` Patchwork
` (4 subsequent siblings)
21 siblings, 1 reply; 35+ messages in thread
From: Patchwork @ 2017-08-18 19:41 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Redo old gmch irq handling (rev2)
URL : https://patchwork.freedesktop.org/series/26215/
State : success
== Summary ==
Series 26215v2 drm/i915: Redo old gmch irq handling
https://patchwork.freedesktop.org/api/1.0/series/26215/revisions/2/mbox/
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
fail -> PASS (fi-snb-2600) fdo#100007
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip -> PASS (fi-skl-x1585l) fdo#101781
fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:456s
fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:439s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:365s
fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:554s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:520s
fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:523s
fi-byt-n2820 total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:518s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:611s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:446s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:426s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:419s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:509s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:477s
fi-kbl-7260u total:279 pass:267 dwarn:2 dfail:0 fail:0 skip:10 time:493s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:474s
fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:599s
fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:598s
fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:527s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:471s
fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:478s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:489s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:443s
fi-skl-x1585l total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:499s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:544s
fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:413s
ad6ab9f96437f0cb1f4d8a7840fd9eeb894eb12e drm-tip: 2017y-08m-18d-18h-21m-46s UTC integration manifest
11b36b1eac83 drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4x
62742e8d9926 drm/i915: Remove duplicated irq_preinstall/uninstall hooks
428b53f306cd drm/i915: Clean up the HWSTAM mess
9e3ffc8e1787 drm/i915: Gen3 HWSTAM is actually 32 bits
c58f1ff308e3 drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode
b1dbca95cb82 drm/i915: Rewrite GMCH irq handlers to avoid loops
3d0a10117632 drm/i915: Extract PIPESTAT irq handling into separate functions
28eed1659115 drm/i915: Remove NULL dev_priv checks from irq_uninstall
d07546a1d105 drm/i915: Unify the appearance of gen3/4 irq_postistall hooks
831adf952e06 drm/i915: Eliminate PORT_HOTPLUG_EN setup from gen3/4 irq_postinstall
8644c84de6a8 drm/i915: Setup EMR first on all gen2-4
97b562a93e03 drm/i915: Introduce GEN2_IRQ_RESET/INIT
5c10eb373e8e drm/i915: Use GEN3_IRQ_RESET/INIT on gen3/4
7484a68fd117 drm/i915: s/GEN5/GEN3/
0c735fdfe040 drm/i915: Clear pipestat consistently
d866fffe6166 drm/i915: Don't enable/unmask flip interrupts
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5446/
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: ✓ Fi.CI.BAT: success for drm/i915: Redo old gmch irq handling (rev2)
2017-08-18 19:41 ` ✓ Fi.CI.BAT: success for drm/i915: Redo old gmch irq handling (rev2) Patchwork
@ 2017-08-18 20:19 ` Chris Wilson
2017-08-21 12:09 ` Ville Syrjälä
0 siblings, 1 reply; 35+ messages in thread
From: Chris Wilson @ 2017-08-18 20:19 UTC (permalink / raw)
To: Patchwork, ville.syrjala; +Cc: intel-gfx
Quoting Patchwork (2017-08-18 20:41:45)
> == Series Details ==
>
> Series: drm/i915: Redo old gmch irq handling (rev2)
> URL : https://patchwork.freedesktop.org/series/26215/
> State : success
>
> == Summary ==
>
> Series 26215v2 drm/i915: Redo old gmch irq handling
> https://patchwork.freedesktop.org/api/1.0/series/26215/revisions/2/mbox/
>
> Test gem_exec_flush:
> Subgroup basic-batch-kernel-default-uc:
> fail -> PASS (fi-snb-2600) fdo#100007
> Test kms_flip:
> Subgroup basic-flip-vs-modeset:
> skip -> PASS (fi-skl-x1585l) fdo#101781
>
> fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
> fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
>
> fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:365s
> fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:419s
> fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:527s
That's a reasonably intensive workout of the interrupt handler. Ironlake
in particular is pretty bad at seqno coherency. Would like to have had
the gdg and elk/ctg results, what happened to those?
-Chris
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^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: ✓ Fi.CI.BAT: success for drm/i915: Redo old gmch irq handling (rev2)
2017-08-18 20:19 ` Chris Wilson
@ 2017-08-21 12:09 ` Ville Syrjälä
2017-08-21 12:15 ` Tomi Sarvela
0 siblings, 1 reply; 35+ messages in thread
From: Ville Syrjälä @ 2017-08-21 12:09 UTC (permalink / raw)
To: Chris Wilson; +Cc: Sarvela, Tomi P, intel-gfx
On Fri, Aug 18, 2017 at 09:19:23PM +0100, Chris Wilson wrote:
> Quoting Patchwork (2017-08-18 20:41:45)
> > == Series Details ==
> >
> > Series: drm/i915: Redo old gmch irq handling (rev2)
> > URL : https://patchwork.freedesktop.org/series/26215/
> > State : success
> >
> > == Summary ==
> >
> > Series 26215v2 drm/i915: Redo old gmch irq handling
> > https://patchwork.freedesktop.org/api/1.0/series/26215/revisions/2/mbox/
> >
> > Test gem_exec_flush:
> > Subgroup basic-batch-kernel-default-uc:
> > fail -> PASS (fi-snb-2600) fdo#100007
> > Test kms_flip:
> > Subgroup basic-flip-vs-modeset:
> > skip -> PASS (fi-skl-x1585l) fdo#101781
> >
> > fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
> > fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
> >
> > fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:365s
> > fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:419s
> > fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:527s
>
> That's a reasonably intensive workout of the interrupt handler. Ironlake
> in particular is pretty bad at seqno coherency. Would like to have had
> the gdg and elk/ctg results, what happened to those?
That's a good question. bwr seems to be missing as well. Tomi?
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: ✓ Fi.CI.BAT: success for drm/i915: Redo old gmch irq handling (rev2)
2017-08-21 12:09 ` Ville Syrjälä
@ 2017-08-21 12:15 ` Tomi Sarvela
2017-08-30 17:13 ` Ville Syrjälä
0 siblings, 1 reply; 35+ messages in thread
From: Tomi Sarvela @ 2017-08-21 12:15 UTC (permalink / raw)
To: Ville Syrjälä, Chris Wilson; +Cc: intel-gfx
On 21/08/17 15:09, Ville Syrjälä wrote:
> On Fri, Aug 18, 2017 at 09:19:23PM +0100, Chris Wilson wrote:
>> Quoting Patchwork (2017-08-18 20:41:45)
>>> == Series Details ==
>>>
>>> Series: drm/i915: Redo old gmch irq handling (rev2)
>>> URL : https://patchwork.freedesktop.org/series/26215/
>>> State : success
>>>
>>> == Summary ==
>>>
>>> Series 26215v2 drm/i915: Redo old gmch irq handling
>>> https://patchwork.freedesktop.org/api/1.0/series/26215/revisions/2/mbox/
>>>
>>> Test gem_exec_flush:
>>> Subgroup basic-batch-kernel-default-uc:
>>> fail -> PASS (fi-snb-2600) fdo#100007
>>> Test kms_flip:
>>> Subgroup basic-flip-vs-modeset:
>>> skip -> PASS (fi-skl-x1585l) fdo#101781
>>>
>>> fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
>>> fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
>>>
>>> fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:365s
>>> fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:419s
>>> fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:527s
>>
>> That's a reasonably intensive workout of the interrupt handler. Ironlake
>> in particular is pretty bad at seqno coherency. Would like to have had
>> the gdg and elk/ctg results, what happened to those?
>
> That's a good question. bwr seems to be missing as well. Tomi?
For hang reasons, BWR and ELK haven't been part of the Patchwork runs.
Added tag to both of them now when the issue is fixed.
CTG is a laptop, and occasionally stops answering to AC boot. Causes
noise, so this hasn't been participating Trybot/Patchwork runs.
GDG is usually (=always) hanging to igt@drv_hangman@error-state-basic
which is one of the first tests run. There hasn't been a reason to keep
it in Patchwork/Trybot.
I can re-run the tests through Patchwork if you want, and you'll get
results to at least BWR and ELK.
Tomi
--
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
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^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: ✓ Fi.CI.BAT: success for drm/i915: Redo old gmch irq handling (rev2)
2017-08-21 12:15 ` Tomi Sarvela
@ 2017-08-30 17:13 ` Ville Syrjälä
0 siblings, 0 replies; 35+ messages in thread
From: Ville Syrjälä @ 2017-08-30 17:13 UTC (permalink / raw)
To: Tomi Sarvela; +Cc: intel-gfx
On Mon, Aug 21, 2017 at 03:15:39PM +0300, Tomi Sarvela wrote:
> On 21/08/17 15:09, Ville Syrjälä wrote:
> > On Fri, Aug 18, 2017 at 09:19:23PM +0100, Chris Wilson wrote:
> >> Quoting Patchwork (2017-08-18 20:41:45)
> >>> == Series Details ==
> >>>
> >>> Series: drm/i915: Redo old gmch irq handling (rev2)
> >>> URL : https://patchwork.freedesktop.org/series/26215/
> >>> State : success
> >>>
> >>> == Summary ==
> >>>
> >>> Series 26215v2 drm/i915: Redo old gmch irq handling
> >>> https://patchwork.freedesktop.org/api/1.0/series/26215/revisions/2/mbox/
> >>>
> >>> Test gem_exec_flush:
> >>> Subgroup basic-batch-kernel-default-uc:
> >>> fail -> PASS (fi-snb-2600) fdo#100007
> >>> Test kms_flip:
> >>> Subgroup basic-flip-vs-modeset:
> >>> skip -> PASS (fi-skl-x1585l) fdo#101781
> >>>
> >>> fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
> >>> fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
> >>>
> >>> fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:365s
> >>> fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:419s
> >>> fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:527s
> >>
> >> That's a reasonably intensive workout of the interrupt handler. Ironlake
> >> in particular is pretty bad at seqno coherency. Would like to have had
> >> the gdg and elk/ctg results, what happened to those?
> >
> > That's a good question. bwr seems to be missing as well. Tomi?
>
> For hang reasons, BWR and ELK haven't been part of the Patchwork runs.
> Added tag to both of them now when the issue is fixed.
>
> CTG is a laptop, and occasionally stops answering to AC boot. Causes
> noise, so this hasn't been participating Trybot/Patchwork runs.
>
> GDG is usually (=always) hanging to igt@drv_hangman@error-state-basic
> which is one of the first tests run. There hasn't been a reason to keep
> it in Patchwork/Trybot.
>
> I can re-run the tests through Patchwork if you want, and you'll get
> results to at least BWR and ELK.
Please do. More results on affected machines wouldn't hurt.
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 35+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Redo old gmch irq handling (rev2)
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (16 preceding siblings ...)
2017-08-18 19:41 ` ✓ Fi.CI.BAT: success for drm/i915: Redo old gmch irq handling (rev2) Patchwork
@ 2017-09-01 10:06 ` Patchwork
2017-09-01 10:23 ` Patchwork
` (3 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2017-09-01 10:06 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Redo old gmch irq handling (rev2)
URL : https://patchwork.freedesktop.org/series/26215/
State : success
== Summary ==
Series 26215v2 drm/i915: Redo old gmch irq handling
https://patchwork.freedesktop.org/api/1.0/series/26215/revisions/2/mbox/
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass -> FAIL (fi-snb-2600) fdo#100215 +1
Subgroup basic-flip-after-cursor-varying-size:
fail -> PASS (fi-hsw-4770) fdo#102402 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip -> PASS (fi-skl-x1585l) fdo#101781
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fi-bdw-5557u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:454s
fi-bdw-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:443s
fi-blb-e6850 total:288 pass:224 dwarn:1 dfail:0 fail:0 skip:63 time:362s
fi-bsw-n3050 total:288 pass:243 dwarn:0 dfail:0 fail:0 skip:45 time:560s
fi-bwr-2160 total:288 pass:184 dwarn:0 dfail:0 fail:0 skip:104 time:255s
fi-bxt-j4205 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:518s
fi-byt-j1900 total:288 pass:254 dwarn:1 dfail:0 fail:0 skip:33 time:521s
fi-byt-n2820 total:288 pass:250 dwarn:1 dfail:0 fail:0 skip:37 time:510s
fi-elk-e7500 total:288 pass:230 dwarn:0 dfail:0 fail:0 skip:58 time:410s
fi-glk-2a total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:611s
fi-hsw-4770 total:288 pass:263 dwarn:0 dfail:0 fail:0 skip:25 time:446s
fi-hsw-4770r total:288 pass:263 dwarn:0 dfail:0 fail:0 skip:25 time:426s
fi-ilk-650 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:418s
fi-ivb-3520m total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:497s
fi-ivb-3770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:476s
fi-kbl-7500u total:288 pass:264 dwarn:1 dfail:0 fail:0 skip:23 time:517s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:598s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:600s
fi-pnv-d510 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:532s
fi-skl-6260u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:485s
fi-skl-6700k total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:534s
fi-skl-6770hq total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:483s
fi-skl-gvtdvm total:288 pass:266 dwarn:0 dfail:0 fail:0 skip:22 time:443s
fi-skl-x1585l total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:511s
fi-snb-2520m total:288 pass:251 dwarn:0 dfail:0 fail:0 skip:37 time:562s
fi-snb-2600 total:288 pass:249 dwarn:0 dfail:0 fail:1 skip:38 time:409s
ccf4ca2d93383fe1a234aba83df9c21400216433 drm-tip: 2017y-08m-31d-18h-37m-46s UTC integration manifest
900e3261566a drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4x
1bfdfcfcfb0f drm/i915: Remove duplicated irq_preinstall/uninstall hooks
2d07cdc5a8a1 drm/i915: Clean up the HWSTAM mess
e1aeb8eb4c36 drm/i915: Gen3 HWSTAM is actually 32 bits
a4303668d4d6 drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode
cd4a709a362f drm/i915: Rewrite GMCH irq handlers to avoid loops
60ecabaeec1e drm/i915: Extract PIPESTAT irq handling into separate functions
accf7e056d5b drm/i915: Remove NULL dev_priv checks from irq_uninstall
e31ffbe0171a drm/i915: Unify the appearance of gen3/4 irq_postistall hooks
201e566ae4a4 drm/i915: Eliminate PORT_HOTPLUG_EN setup from gen3/4 irq_postinstall
06cbe05a9c60 drm/i915: Setup EMR first on all gen2-4
08169c3bbba8 drm/i915: Introduce GEN2_IRQ_RESET/INIT
4c5f8c3982a8 drm/i915: Use GEN3_IRQ_RESET/INIT on gen3/4
4cf1aaa7cbc1 drm/i915: s/GEN5/GEN3/
263994659718 drm/i915: Clear pipestat consistently
f2dab4cd6282 drm/i915: Don't enable/unmask flip interrupts
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5559/
_______________________________________________
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^ permalink raw reply [flat|nested] 35+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: Redo old gmch irq handling (rev2)
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (17 preceding siblings ...)
2017-09-01 10:06 ` Patchwork
@ 2017-09-01 10:23 ` Patchwork
2017-09-01 11:13 ` ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2017-09-01 10:23 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Redo old gmch irq handling (rev2)
URL : https://patchwork.freedesktop.org/series/26215/
State : success
== Summary ==
Series 26215v2 drm/i915: Redo old gmch irq handling
https://patchwork.freedesktop.org/api/1.0/series/26215/revisions/2/mbox/
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass -> FAIL (fi-ivb-3770) fdo#100215
Subgroup basic-flip-after-cursor-varying-size:
fail -> PASS (fi-hsw-4770) fdo#102402 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip -> PASS (fi-skl-x1585l) fdo#101781
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fi-bdw-5557u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:460s
fi-bdw-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:446s
fi-blb-e6850 total:288 pass:224 dwarn:1 dfail:0 fail:0 skip:63 time:368s
fi-bsw-n3050 total:288 pass:243 dwarn:0 dfail:0 fail:0 skip:45 time:556s
fi-bwr-2160 total:288 pass:184 dwarn:0 dfail:0 fail:0 skip:104 time:253s
fi-bxt-j4205 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:520s
fi-byt-j1900 total:288 pass:254 dwarn:1 dfail:0 fail:0 skip:33 time:521s
fi-byt-n2820 total:288 pass:250 dwarn:1 dfail:0 fail:0 skip:37 time:518s
fi-elk-e7500 total:288 pass:230 dwarn:0 dfail:0 fail:0 skip:58 time:414s
fi-glk-2a total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:612s
fi-hsw-4770 total:288 pass:263 dwarn:0 dfail:0 fail:0 skip:25 time:454s
fi-hsw-4770r total:288 pass:263 dwarn:0 dfail:0 fail:0 skip:25 time:424s
fi-ilk-650 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:420s
fi-ivb-3520m total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:500s
fi-ivb-3770 total:288 pass:260 dwarn:0 dfail:0 fail:1 skip:27 time:475s
fi-kbl-7500u total:288 pass:264 dwarn:1 dfail:0 fail:0 skip:23 time:518s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:598s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:601s
fi-pnv-d510 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:529s
fi-skl-6260u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:478s
fi-skl-6700k total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:540s
fi-skl-6770hq total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:495s
fi-skl-gvtdvm total:288 pass:266 dwarn:0 dfail:0 fail:0 skip:22 time:438s
fi-skl-x1585l total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:511s
fi-snb-2520m total:288 pass:251 dwarn:0 dfail:0 fail:0 skip:37 time:552s
fi-snb-2600 total:288 pass:249 dwarn:0 dfail:0 fail:1 skip:38 time:410s
ccf4ca2d93383fe1a234aba83df9c21400216433 drm-tip: 2017y-08m-31d-18h-37m-46s UTC integration manifest
fe0354b4df87 drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4x
af8563535b96 drm/i915: Remove duplicated irq_preinstall/uninstall hooks
2bdfd7b635fe drm/i915: Clean up the HWSTAM mess
26363d561742 drm/i915: Gen3 HWSTAM is actually 32 bits
593f6bd308c6 drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode
57308cfa1909 drm/i915: Rewrite GMCH irq handlers to avoid loops
2dc717448415 drm/i915: Extract PIPESTAT irq handling into separate functions
e55fbed10ee6 drm/i915: Remove NULL dev_priv checks from irq_uninstall
5bacbb34d3cd drm/i915: Unify the appearance of gen3/4 irq_postistall hooks
4413cf09ee7d drm/i915: Eliminate PORT_HOTPLUG_EN setup from gen3/4 irq_postinstall
c5019846a5bd drm/i915: Setup EMR first on all gen2-4
7fc296528fa1 drm/i915: Introduce GEN2_IRQ_RESET/INIT
e7e80ec1318e drm/i915: Use GEN3_IRQ_RESET/INIT on gen3/4
8dfe0f88cea7 drm/i915: s/GEN5/GEN3/
5f5cc9f5bbe5 drm/i915: Clear pipestat consistently
214163008889 drm/i915: Don't enable/unmask flip interrupts
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5560/
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: Redo old gmch irq handling (rev2)
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (18 preceding siblings ...)
2017-09-01 10:23 ` Patchwork
@ 2017-09-01 11:13 ` Patchwork
2017-09-01 12:03 ` Patchwork
2017-09-14 14:50 ` [PATCH v2 00/16] drm/i915: Redo old gmch irq handling Ville Syrjälä
21 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2017-09-01 11:13 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Redo old gmch irq handling (rev2)
URL : https://patchwork.freedesktop.org/series/26215/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
shard-hsw total:2265 pass:1233 dwarn:0 dfail:0 fail:16 skip:1016 time:9587s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5559/shards.html
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^ permalink raw reply [flat|nested] 35+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: Redo old gmch irq handling (rev2)
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (19 preceding siblings ...)
2017-09-01 11:13 ` ✓ Fi.CI.IGT: " Patchwork
@ 2017-09-01 12:03 ` Patchwork
2017-09-14 14:50 ` [PATCH v2 00/16] drm/i915: Redo old gmch irq handling Ville Syrjälä
21 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2017-09-01 12:03 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Redo old gmch irq handling (rev2)
URL : https://patchwork.freedesktop.org/series/26215/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
shard-hsw total:2265 pass:1233 dwarn:0 dfail:0 fail:16 skip:1016 time:9621s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5560/shards.html
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH v2 00/16] drm/i915: Redo old gmch irq handling
2017-08-18 18:36 [PATCH v2 00/16] drm/i915: Redo old gmch irq handling ville.syrjala
` (20 preceding siblings ...)
2017-09-01 12:03 ` Patchwork
@ 2017-09-14 14:50 ` Ville Syrjälä
2017-09-14 14:54 ` Chris Wilson
21 siblings, 1 reply; 35+ messages in thread
From: Ville Syrjälä @ 2017-09-14 14:50 UTC (permalink / raw)
To: intel-gfx
On Fri, Aug 18, 2017 at 09:36:49PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reposted GMCH irq rework series. A few patches fell out completely
> since the flip interrupt handling was nuked in the meantime. I also
> added a patch to remove some more flip irq leftover, and I tossed in
> a patch to reinstate GMBUS/AUX irqs on gen4/g4x since we no longer
> use MSI there. I also reordered things a bit to move the HWSTAM stuff
> towards the end of the series.
>
> Entire series available here:
> git://github.com/vsyrjala/linux.git gmch_irq_redo_3
>
> Ville Syrjälä (16):
> drm/i915: Don't enable/unmask flip interrupts
> drm/i915: Clear pipestat consistently
> drm/i915: s/GEN5/GEN3/
> drm/i915: Use GEN3_IRQ_RESET/INIT on gen3/4
> drm/i915: Introduce GEN2_IRQ_RESET/INIT
> drm/i915: Setup EMR first on all gen2-4
> drm/i915: Eliminate PORT_HOTPLUG_EN setup from gen3/4 irq_postinstall
> drm/i915: Unify the appearance of gen3/4 irq_postistall hooks
> drm/i915: Remove NULL dev_priv checks from irq_uninstall
> drm/i915: Extract PIPESTAT irq handling into separate functions
> drm/i915: Rewrite GMCH irq handlers to avoid loops
> drm/i915: Gen3 HWSTAM is actually 32 bits
Above patches above pushed to dinq. Thanks for the reviews.
> drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode
> drm/i915: Clean up the HWSTAM mess
> drm/i915: Remove duplicated irq_preinstall/uninstall hooks
> drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4x
And these remain to be reviewed. Also I have one more PIPESTAT related
fix I need to send out.
>
> drivers/gpu/drm/i915/i915_drv.h | 8 +-
> drivers/gpu/drm/i915/i915_irq.c | 729 ++++++++++++--------------------
> drivers/gpu/drm/i915/i915_pci.c | 6 -
> drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +
> 4 files changed, 284 insertions(+), 462 deletions(-)
>
> --
> 2.13.0
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH v2 00/16] drm/i915: Redo old gmch irq handling
2017-09-14 14:50 ` [PATCH v2 00/16] drm/i915: Redo old gmch irq handling Ville Syrjälä
@ 2017-09-14 14:54 ` Chris Wilson
2017-09-14 14:55 ` Chris Wilson
0 siblings, 1 reply; 35+ messages in thread
From: Chris Wilson @ 2017-09-14 14:54 UTC (permalink / raw)
To: Ville Syrjälä, intel-gfx
Quoting Ville Syrjälä (2017-09-14 15:50:14)
> On Fri, Aug 18, 2017 at 09:36:49PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Reposted GMCH irq rework series. A few patches fell out completely
> > since the flip interrupt handling was nuked in the meantime. I also
> > added a patch to remove some more flip irq leftover, and I tossed in
> > a patch to reinstate GMBUS/AUX irqs on gen4/g4x since we no longer
> > use MSI there. I also reordered things a bit to move the HWSTAM stuff
> > towards the end of the series.
> >
> > Entire series available here:
> > git://github.com/vsyrjala/linux.git gmch_irq_redo_3
> >
> > Ville Syrjälä (16):
> > drm/i915: Don't enable/unmask flip interrupts
> > drm/i915: Clear pipestat consistently
> > drm/i915: s/GEN5/GEN3/
> > drm/i915: Use GEN3_IRQ_RESET/INIT on gen3/4
> > drm/i915: Introduce GEN2_IRQ_RESET/INIT
> > drm/i915: Setup EMR first on all gen2-4
> > drm/i915: Eliminate PORT_HOTPLUG_EN setup from gen3/4 irq_postinstall
> > drm/i915: Unify the appearance of gen3/4 irq_postistall hooks
> > drm/i915: Remove NULL dev_priv checks from irq_uninstall
> > drm/i915: Extract PIPESTAT irq handling into separate functions
> > drm/i915: Rewrite GMCH irq handlers to avoid loops
> > drm/i915: Gen3 HWSTAM is actually 32 bits
>
> Above patches above pushed to dinq. Thanks for the reviews.
>
> > drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode
Enough runs through CI to have picked up anything by now,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> > drm/i915: Clean up the HWSTAM mess
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> > drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4x
Hmm.
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
problem being the disappearance of the reporter to easily verify that we
haven't missed something.
Leaving
> > drm/i915: Remove duplicated irq_preinstall/uninstall hooks
which I can't remember enough and will need to read again.
-Chris
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^ permalink raw reply [flat|nested] 35+ messages in thread