* [PATCH 1/2] drm/i915/cnp: Don't touch other PCH clock gating bits.
@ 2017-09-08 23:45 Rodrigo Vivi
2017-09-08 23:45 ` [PATCH 2/2] drm/i915/cnp: Wa 1179 Rodrigo Vivi
` (5 more replies)
0 siblings, 6 replies; 15+ messages in thread
From: Rodrigo Vivi @ 2017-09-08 23:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
Don't touch other bits. My bad.
I haven't seen any case where those other bits appeard to be
set before we touch it, but it is safe to avoid touching
other bits we weren't told to touch.
Fixes: 0a46ddd57c9e ("drm/i915/cnp: Wa 1181: Fix Backlight issue")
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fa9055a4f790..09ecc8e3b2d3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8370,7 +8370,8 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
return;
/* Wa #1181 */
- I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
+ CNP_PWM_CGE_GATING_DISABLE);
}
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.13.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/2] drm/i915/cnp: Wa 1179
2017-09-08 23:45 [PATCH 1/2] drm/i915/cnp: Don't touch other PCH clock gating bits Rodrigo Vivi
@ 2017-09-08 23:45 ` Rodrigo Vivi
2017-09-09 0:33 ` Pandiyan, Dhinakaran
2017-09-09 0:05 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnp: Don't touch other PCH clock gating bits Patchwork
` (4 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: Rodrigo Vivi @ 2017-09-08 23:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Ben Widawsky, Dhinakaran Pandiyan, Rodrigo Vivi
"CNL PCH chance of hang when software accesses south display
registers after hotplug is enabled.
Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling
south display hotplug detection."
"Workaround only needs to be applied to pre-production steppings
used in graphics capable SKUs, but it is easier to apply to
everything, and does not hurt."
Suggested-by: Ben Widawsky <ben@bwidawsk.net>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0b03260a3967..532c9c7bdc51 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7474,6 +7474,8 @@ enum {
#define SOUTH_CHICKEN2 _MMIO(0xc2004)
#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
+#define CHASSIS_CLK_REQ_DURATION_MASK (0xf<<8)
+#define CHASSIS_CLK_REQ_DURATION(x) ((x)<<8)
#define LPT_PWM_GRANULARITY (1<<5)
#define DPLS_EDP_PPS_FIX_DIS (1<<0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 09ecc8e3b2d3..e49682a5ab0e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8366,12 +8366,18 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
{
+ u32 val;
if (!HAS_PCH_CNP(dev_priv))
return;
/* Wa #1181 */
I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
CNP_PWM_CGE_GATING_DISABLE);
+
+ /* Wa #1179 */
+ val = I915_READ(SOUTH_CHICKEN1) & ~CHASSIS_CLK_REQ_DURATION_MASK;
+ val |= CHASSIS_CLK_REQ_DURATION(0xf);
+ I915_WRITE(SOUTH_CHICKEN1, val);
}
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.13.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnp: Don't touch other PCH clock gating bits.
2017-09-08 23:45 [PATCH 1/2] drm/i915/cnp: Don't touch other PCH clock gating bits Rodrigo Vivi
2017-09-08 23:45 ` [PATCH 2/2] drm/i915/cnp: Wa 1179 Rodrigo Vivi
@ 2017-09-09 0:05 ` Patchwork
2017-09-09 0:10 ` [PATCH 1/2] " Pandiyan, Dhinakaran
` (3 subsequent siblings)
5 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2017-09-09 0:05 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/cnp: Don't touch other PCH clock gating bits.
URL : https://patchwork.freedesktop.org/series/30067/
State : success
== Summary ==
Series 30067v1 series starting with [1/2] drm/i915/cnp: Don't touch other PCH clock gating bits.
https://patchwork.freedesktop.org/api/1.0/series/30067/revisions/1/mbox/
Test gem_exec_store:
Subgroup basic-default:
incomplete -> PASS (fi-byt-j1900)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail -> PASS (fi-snb-2600) fdo#100215 +1
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (fi-byt-n2820) fdo#101705
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:449s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:444s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:375s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:522s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:268s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:504s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:500s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:491s
fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 time:447s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:447s
fi-glk-2a total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:597s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:428s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:408s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:434s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:481s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:466s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:484s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:575s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:586s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:554s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:452s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:518s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:504s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:458s
fi-skl-x1585l total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:473s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:568s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:427s
b7ca0db5dc374e1f58839cfdc3803d4f4fb47eaf drm-tip: 2017y-09m-08d-20h-12m-37s UTC integration manifest
e78956cd9fbc drm/i915/cnp: Wa 1179
0e29609857c2 drm/i915/cnp: Don't touch other PCH clock gating bits.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5624/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] drm/i915/cnp: Don't touch other PCH clock gating bits.
2017-09-08 23:45 [PATCH 1/2] drm/i915/cnp: Don't touch other PCH clock gating bits Rodrigo Vivi
2017-09-08 23:45 ` [PATCH 2/2] drm/i915/cnp: Wa 1179 Rodrigo Vivi
2017-09-09 0:05 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnp: Don't touch other PCH clock gating bits Patchwork
@ 2017-09-09 0:10 ` Pandiyan, Dhinakaran
2017-09-18 23:25 ` Rodrigo Vivi
2017-09-09 1:11 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
` (2 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: Pandiyan, Dhinakaran @ 2017-09-09 0:10 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx@lists.freedesktop.org
On Fri, 2017-09-08 at 16:45 -0700, Rodrigo Vivi wrote:
> Don't touch other bits. My bad.
>
> I haven't seen any case where those other bits appeard to be
> set before we touch it, but it is safe to avoid touching
> other bits we weren't told to touch.
>
Well, I did notice the earlier patch cleared rest of the bits, but we do
the same in ibx_init_clock_gating() and cpt_init_clock_gating() too. So,
I assume it's okay either way and since these bits are for workarounds,
I thought we might as well start by clearing the bits other than those
we know are required. But, since you feel this version is a safer
option,
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Fixes: 0a46ddd57c9e ("drm/i915/cnp: Wa 1181: Fix Backlight issue")
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fa9055a4f790..09ecc8e3b2d3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8370,7 +8370,8 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
> return;
>
> /* Wa #1181 */
> - I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
> + I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
> + CNP_PWM_CGE_GATING_DISABLE);
> }
>
> static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] drm/i915/cnp: Wa 1179
2017-09-08 23:45 ` [PATCH 2/2] drm/i915/cnp: Wa 1179 Rodrigo Vivi
@ 2017-09-09 0:33 ` Pandiyan, Dhinakaran
2017-09-09 0:38 ` Vivi, Rodrigo
0 siblings, 1 reply; 15+ messages in thread
From: Pandiyan, Dhinakaran @ 2017-09-09 0:33 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: ben@bwidawsk.net, intel-gfx@lists.freedesktop.org
On Fri, 2017-09-08 at 16:45 -0700, Rodrigo Vivi wrote:
> "CNL PCH chance of hang when software accesses south display
> registers after hotplug is enabled.
> Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling
> south display hotplug detection."
I see that intel_finish_reset() enables hotplug interrupts through
intel_runtime_pm_enable_interrupts() before _init_clock_gating() gets
called. However, the hotplug interrupts remain masked. I wonder if that
is a problem to apply this workaround.
>
> "Workaround only needs to be applied to pre-production steppings
> used in graphics capable SKUs, but it is easier to apply to
> everything, and does not hurt."
>
> Suggested-by: Ben Widawsky <ben@bwidawsk.net>
> Cc: Ben Widawsky <ben@bwidawsk.net>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0b03260a3967..532c9c7bdc51 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7474,6 +7474,8 @@ enum {
> #define SOUTH_CHICKEN2 _MMIO(0xc2004)
> #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
> #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
> +#define CHASSIS_CLK_REQ_DURATION_MASK (0xf<<8)
> +#define CHASSIS_CLK_REQ_DURATION(x) ((x)<<8)
> #define LPT_PWM_GRANULARITY (1<<5)
> #define DPLS_EDP_PPS_FIX_DIS (1<<0)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 09ecc8e3b2d3..e49682a5ab0e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8366,12 +8366,18 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
>
> static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> + u32 val;
> if (!HAS_PCH_CNP(dev_priv))
> return;
>
> /* Wa #1181 */
> I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
> CNP_PWM_CGE_GATING_DISABLE);
> +
> + /* Wa #1179 */
> + val = I915_READ(SOUTH_CHICKEN1) & ~CHASSIS_CLK_REQ_DURATION_MASK;
> + val |= CHASSIS_CLK_REQ_DURATION(0xf);
> + I915_WRITE(SOUTH_CHICKEN1, val);
> }
>
> static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] drm/i915/cnp: Wa 1179
2017-09-09 0:33 ` Pandiyan, Dhinakaran
@ 2017-09-09 0:38 ` Vivi, Rodrigo
2017-09-09 1:55 ` Runyan, Arthur J
0 siblings, 1 reply; 15+ messages in thread
From: Vivi, Rodrigo @ 2017-09-09 0:38 UTC (permalink / raw)
To: Pandiyan, Dhinakaran, Runyan, Arthur J
Cc: ben@bwidawsk.net, intel-gfx@lists.freedesktop.org
+Art...
> On Sep 8, 2017, at 5:33 PM, Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com> wrote:
>
>> On Fri, 2017-09-08 at 16:45 -0700, Rodrigo Vivi wrote:
>> "CNL PCH chance of hang when software accesses south display
>> registers after hotplug is enabled.
>> Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling
>> south display hotplug detection."
>
>
> I see that intel_finish_reset() enables hotplug interrupts through
> intel_runtime_pm_enable_interrupts() before _init_clock_gating() gets
> called. However, the hotplug interrupts remain masked. I wonder if that
> is a problem to apply this workaround.
I believe we need to move that early too..
Art, any recommendation?!
>
>>
>> "Workaround only needs to be applied to pre-production steppings
>> used in graphics capable SKUs, but it is easier to apply to
>> everything, and does not hurt."
>>
>> Suggested-by: Ben Widawsky <ben@bwidawsk.net>
>> Cc: Ben Widawsky <ben@bwidawsk.net>
>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>> 2 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 0b03260a3967..532c9c7bdc51 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7474,6 +7474,8 @@ enum {
>> #define SOUTH_CHICKEN2 _MMIO(0xc2004)
>> #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
>> #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
>> +#define CHASSIS_CLK_REQ_DURATION_MASK (0xf<<8)
>> +#define CHASSIS_CLK_REQ_DURATION(x) ((x)<<8)
>> #define LPT_PWM_GRANULARITY (1<<5)
>> #define DPLS_EDP_PPS_FIX_DIS (1<<0)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 09ecc8e3b2d3..e49682a5ab0e 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -8366,12 +8366,18 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
>>
>> static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
>> {
>> + u32 val;
>> if (!HAS_PCH_CNP(dev_priv))
>> return;
>>
>> /* Wa #1181 */
>> I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
>> CNP_PWM_CGE_GATING_DISABLE);
>> +
>> + /* Wa #1179 */
>> + val = I915_READ(SOUTH_CHICKEN1) & ~CHASSIS_CLK_REQ_DURATION_MASK;
>> + val |= CHASSIS_CLK_REQ_DURATION(0xf);
>> + I915_WRITE(SOUTH_CHICKEN1, val);
>> }
>>
>> static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/cnp: Don't touch other PCH clock gating bits.
2017-09-08 23:45 [PATCH 1/2] drm/i915/cnp: Don't touch other PCH clock gating bits Rodrigo Vivi
` (2 preceding siblings ...)
2017-09-09 0:10 ` [PATCH 1/2] " Pandiyan, Dhinakaran
@ 2017-09-09 1:11 ` Patchwork
2017-09-19 13:25 ` ✗ Fi.CI.BAT: warning for series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev2) Patchwork
2017-09-19 20:28 ` ✗ Fi.CI.BAT: failure for series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev3) Patchwork
5 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2017-09-09 1:11 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/cnp: Don't touch other PCH clock gating bits.
URL : https://patchwork.freedesktop.org/series/30067/
State : success
== Summary ==
Test gem_flink_race:
Subgroup flink_close:
fail -> PASS (shard-hsw)
Test gem_eio:
Subgroup in-flight:
fail -> PASS (shard-hsw) fdo#102616
Test gem_pwrite_pread:
Subgroup display-copy-correctness:
fail -> PASS (shard-hsw)
Test gem_exec_reloc:
Subgroup basic-write-gtt-active:
skip -> PASS (shard-hsw)
Test kms_flip:
Subgroup blt-wf_vblank-vs-modeset:
skip -> PASS (shard-hsw)
fdo#102616 https://bugs.freedesktop.org/show_bug.cgi?id=102616
shard-hsw total:2302 pass:1236 dwarn:0 dfail:0 fail:14 skip:1052 time:9431s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5624/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] drm/i915/cnp: Wa 1179
2017-09-09 0:38 ` Vivi, Rodrigo
@ 2017-09-09 1:55 ` Runyan, Arthur J
2017-09-18 23:56 ` [PATCH] drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug Rodrigo Vivi
0 siblings, 1 reply; 15+ messages in thread
From: Runyan, Arthur J @ 2017-09-09 1:55 UTC (permalink / raw)
To: Vivi, Rodrigo, Pandiyan, Dhinakaran
Cc: ben@bwidawsk.net, intel-gfx@lists.freedesktop.org
The workaround needs to come before you enable the detection in SHOTPLUG_CTL.
-----Original Message-----
From: Vivi, Rodrigo
Sent: Friday, 8 September, 2017 5:38 PM
To: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>; Runyan, Arthur J <arthur.j.runyan@intel.com>
Cc: ben@bwidawsk.net; intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/i915/cnp: Wa 1179
+Art...
> On Sep 8, 2017, at 5:33 PM, Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com> wrote:
>
>> On Fri, 2017-09-08 at 16:45 -0700, Rodrigo Vivi wrote:
>> "CNL PCH chance of hang when software accesses south display
>> registers after hotplug is enabled.
>> Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling
>> south display hotplug detection."
>
>
> I see that intel_finish_reset() enables hotplug interrupts through
> intel_runtime_pm_enable_interrupts() before _init_clock_gating() gets
> called. However, the hotplug interrupts remain masked. I wonder if that
> is a problem to apply this workaround.
I believe we need to move that early too..
Art, any recommendation?!
>
>>
>> "Workaround only needs to be applied to pre-production steppings
>> used in graphics capable SKUs, but it is easier to apply to
>> everything, and does not hurt."
>>
>> Suggested-by: Ben Widawsky <ben@bwidawsk.net>
>> Cc: Ben Widawsky <ben@bwidawsk.net>
>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>> 2 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 0b03260a3967..532c9c7bdc51 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7474,6 +7474,8 @@ enum {
>> #define SOUTH_CHICKEN2 _MMIO(0xc2004)
>> #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
>> #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
>> +#define CHASSIS_CLK_REQ_DURATION_MASK (0xf<<8)
>> +#define CHASSIS_CLK_REQ_DURATION(x) ((x)<<8)
>> #define LPT_PWM_GRANULARITY (1<<5)
>> #define DPLS_EDP_PPS_FIX_DIS (1<<0)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 09ecc8e3b2d3..e49682a5ab0e 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -8366,12 +8366,18 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
>>
>> static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
>> {
>> + u32 val;
>> if (!HAS_PCH_CNP(dev_priv))
>> return;
>>
>> /* Wa #1181 */
>> I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
>> CNP_PWM_CGE_GATING_DISABLE);
>> +
>> + /* Wa #1179 */
>> + val = I915_READ(SOUTH_CHICKEN1) & ~CHASSIS_CLK_REQ_DURATION_MASK;
>> + val |= CHASSIS_CLK_REQ_DURATION(0xf);
>> + I915_WRITE(SOUTH_CHICKEN1, val);
>> }
>>
>> static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] drm/i915/cnp: Don't touch other PCH clock gating bits.
2017-09-09 0:10 ` [PATCH 1/2] " Pandiyan, Dhinakaran
@ 2017-09-18 23:25 ` Rodrigo Vivi
0 siblings, 0 replies; 15+ messages in thread
From: Rodrigo Vivi @ 2017-09-18 23:25 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx@lists.freedesktop.org
On Sat, Sep 09, 2017 at 12:10:04AM +0000, Pandiyan, Dhinakaran wrote:
> On Fri, 2017-09-08 at 16:45 -0700, Rodrigo Vivi wrote:
> > Don't touch other bits. My bad.
> >
> > I haven't seen any case where those other bits appeard to be
> > set before we touch it, but it is safe to avoid touching
> > other bits we weren't told to touch.
> >
>
> Well, I did notice the earlier patch cleared rest of the bits, but we do
> the same in ibx_init_clock_gating() and cpt_init_clock_gating() too. So,
> I assume it's okay either way and since these bits are for workarounds,
yep, I believe the old ones were the ones that made me write the initial
version without rmw... but nowadayes we have more components and firmware
with access to register and maybe other chicken bits maybe modified by
other components. so better to start moving to rmw whenever we touch
things like this.
> I thought we might as well start by clearing the bits other than those
> we know are required. But, since you feel this version is a safer
> option,
>
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
merged to dinq, thanks for the review.
>
>
> > Fixes: 0a46ddd57c9e ("drm/i915/cnp: Wa 1181: Fix Backlight issue")
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index fa9055a4f790..09ecc8e3b2d3 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -8370,7 +8370,8 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
> > return;
> >
> > /* Wa #1181 */
> > - I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
> > + I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
> > + CNP_PWM_CGE_GATING_DISABLE);
> > }
> >
> > static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH] drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug
2017-09-09 1:55 ` Runyan, Arthur J
@ 2017-09-18 23:56 ` Rodrigo Vivi
2017-09-19 0:31 ` Pandiyan, Dhinakaran
0 siblings, 1 reply; 15+ messages in thread
From: Rodrigo Vivi @ 2017-09-18 23:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Ben Widawsky, Dhinakaran Pandiyan, Rodrigo Vivi
"CNL PCH chance of hang when software accesses south display
registers after hotplug is enabled.
Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling
south display hotplug detection."
"Workaround only needs to be applied to pre-production steppings
used in graphics capable SKUs, but it is easier to apply to
everything, and does not hurt."
v2: Moving from clock gating to right before enabling
SHOTPLUG_CTL as it should be.
Suggested-by: Ben Widawsky <ben@bwidawsk.net>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 9 ++++++++-
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4d0e8f76ed1a..901832a01d52 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3218,7 +3218,14 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
- u32 hotplug;
+ u32 val, hotplug;
+
+ /* Display WA #1179 WaHardHangonHotPlug: cnp */
+ if (HAS_PCH_CNP(dev_priv)) {
+ val = I915_READ(SOUTH_CHICKEN1) & ~CHASSIS_CLK_REQ_DURATION_MASK;
+ val |= CHASSIS_CLK_REQ_DURATION(0xf);
+ I915_WRITE(SOUTH_CHICKEN1, val);
+ }
/* Enable digital hotplug on the PCH */
hotplug = I915_READ(PCH_PORT_HOTPLUG);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a8cb9c17e6df..2e1cdc099f14 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7483,6 +7483,8 @@ enum {
#define SOUTH_CHICKEN2 _MMIO(0xc2004)
#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
+#define CHASSIS_CLK_REQ_DURATION_MASK (0xf<<8)
+#define CHASSIS_CLK_REQ_DURATION(x) ((x)<<8)
#define LPT_PWM_GRANULARITY (1<<5)
#define DPLS_EDP_PPS_FIX_DIS (1<<0)
--
2.13.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug
2017-09-18 23:56 ` [PATCH] drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug Rodrigo Vivi
@ 2017-09-19 0:31 ` Pandiyan, Dhinakaran
2017-09-19 17:28 ` Rodrigo Vivi
0 siblings, 1 reply; 15+ messages in thread
From: Pandiyan, Dhinakaran @ 2017-09-19 0:31 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: ben@bwidawsk.net, intel-gfx@lists.freedesktop.org
On Mon, 2017-09-18 at 16:56 -0700, Rodrigo Vivi wrote:
> "CNL PCH chance of hang when software accesses south display
> registers after hotplug is enabled.
> Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling
> south display hotplug detection."
>
> "Workaround only needs to be applied to pre-production steppings
> used in graphics capable SKUs, but it is easier to apply to
> everything, and does not hurt."
>
> v2: Moving from clock gating to right before enabling
> SHOTPLUG_CTL as it should be.
>
> Suggested-by: Ben Widawsky <ben@bwidawsk.net>
> Cc: Ben Widawsky <ben@bwidawsk.net>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 9 ++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 4d0e8f76ed1a..901832a01d52 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3218,7 +3218,14 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
>
> static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> - u32 hotplug;
> + u32 val, hotplug;
> +
> + /* Display WA #1179 WaHardHangonHotPlug: cnp */
> + if (HAS_PCH_CNP(dev_priv)) {
> + val = I915_READ(SOUTH_CHICKEN1) & ~CHASSIS_CLK_REQ_DURATION_MASK;
> + val |= CHASSIS_CLK_REQ_DURATION(0xf);
> + I915_WRITE(SOUTH_CHICKEN1, val);
> + }
>
> /* Enable digital hotplug on the PCH */
> hotplug = I915_READ(PCH_PORT_HOTPLUG);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a8cb9c17e6df..2e1cdc099f14 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7483,6 +7483,8 @@ enum {
> #define SOUTH_CHICKEN2 _MMIO(0xc2004)
> #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
> #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
> +#define CHASSIS_CLK_REQ_DURATION_MASK (0xf<<8)
> +#define CHASSIS_CLK_REQ_DURATION(x) ((x)<<8)
These bit defs should be under *SOUTH_CHICKEN1*. Matches the spec
otherwise, with the definitions moved -
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> #define LPT_PWM_GRANULARITY (1<<5)
> #define DPLS_EDP_PPS_FIX_DIS (1<<0)
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✗ Fi.CI.BAT: warning for series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev2)
2017-09-08 23:45 [PATCH 1/2] drm/i915/cnp: Don't touch other PCH clock gating bits Rodrigo Vivi
` (3 preceding siblings ...)
2017-09-09 1:11 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
@ 2017-09-19 13:25 ` Patchwork
2017-09-19 20:28 ` ✗ Fi.CI.BAT: failure for series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev3) Patchwork
5 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2017-09-19 13:25 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev2)
URL : https://patchwork.freedesktop.org/series/30067/
State : warning
== Summary ==
Series 30067v2 series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug
https://patchwork.freedesktop.org/api/1.0/series/30067/revisions/2/mbox/
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail -> PASS (fi-snb-2600) fdo#100215
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-WARN (fi-snb-2600)
Test pm_rpm:
Subgroup basic-rte:
dmesg-warn -> PASS (fi-cfl-s) fdo#102294
Test drv_module_reload:
Subgroup basic-no-display:
pass -> DMESG-WARN (fi-glk-1)
Subgroup basic-reload-inject:
dmesg-warn -> PASS (fi-glk-1)
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:449s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:472s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:426s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:516s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:278s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:497s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:494s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:494s
fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:538s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:421s
fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:563s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:428s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:410s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:427s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:490s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:462s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:473s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:581s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:552s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:452s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:756s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:499s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:482s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:561s
fi-snb-2600 total:289 pass:248 dwarn:1 dfail:0 fail:1 skip:39 time:415s
5061f6a05b703b00a832db3e53fe7a2deb15e408 drm-tip: 2017y-09m-19d-12h-08m-07s UTC integration manifest
62c5eeca8f69 drm/i915/cnp: Wa 1179
cd3fe3451aed drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5744/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH] drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug
2017-09-19 0:31 ` Pandiyan, Dhinakaran
@ 2017-09-19 17:28 ` Rodrigo Vivi
0 siblings, 0 replies; 15+ messages in thread
From: Rodrigo Vivi @ 2017-09-19 17:28 UTC (permalink / raw)
To: intel-gfx; +Cc: Ben Widawsky, Dhinakaran Pandiyan, Rodrigo Vivi
"CNL PCH chance of hang when software accesses south display
registers after hotplug is enabled.
Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling
south display hotplug detection."
"Workaround only needs to be applied to pre-production steppings
used in graphics capable SKUs, but it is easier to apply to
everything, and does not hurt."
v2: Moving from clock gating to right before enabling
SHOTPLUG_CTL as it should be.
v3: Align with SOUTH_CHICKEN1 (DK) and consequently use proper
spaces on bits definition since other bits around already use
new style. And now that checkpatch is not noise anymore I also
fixed the reg read mask to avoid going over 80 chars.
Suggested-by: Ben Widawsky <ben@bwidawsk.net>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 10 +++++++++-
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4d0e8f76ed1a..c23efc4394ce 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3218,7 +3218,15 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
- u32 hotplug;
+ u32 val, hotplug;
+
+ /* Display WA #1179 WaHardHangonHotPlug: cnp */
+ if (HAS_PCH_CNP(dev_priv)) {
+ val = I915_READ(SOUTH_CHICKEN1);
+ val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
+ val |= CHASSIS_CLK_REQ_DURATION(0xf);
+ I915_WRITE(SOUTH_CHICKEN1, val);
+ }
/* Enable digital hotplug on the PCH */
hotplug = I915_READ(PCH_PORT_HOTPLUG);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a8cb9c17e6df..832f38125240 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7479,6 +7479,8 @@ enum {
#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
#define FDI_BC_BIFURCATION_SELECT (1 << 12)
+#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
+#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
#define SPT_PWM_GRANULARITY (1<<0)
#define SOUTH_CHICKEN2 _MMIO(0xc2004)
#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
--
2.13.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev3)
2017-09-08 23:45 [PATCH 1/2] drm/i915/cnp: Don't touch other PCH clock gating bits Rodrigo Vivi
` (4 preceding siblings ...)
2017-09-19 13:25 ` ✗ Fi.CI.BAT: warning for series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev2) Patchwork
@ 2017-09-19 20:28 ` Patchwork
2017-09-19 21:50 ` Rodrigo Vivi
5 siblings, 1 reply; 15+ messages in thread
From: Patchwork @ 2017-09-19 20:28 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev3)
URL : https://patchwork.freedesktop.org/series/30067/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CHK include/generated/bounds.h
CHK include/generated/timeconst.h
CHK include/generated/asm-offsets.h
CALL scripts/checksyscalls.sh
CHK scripts/mod/devicetable-offsets.h
CHK include/generated/compile.h
CHK kernel/config_data.h
CC [M] drivers/gpu/drm/i915/i915_drv.o
In file included from drivers/gpu/drm/i915/i915_drv.h:55:0,
from drivers/gpu/drm/i915/i915_drv.c:49:
drivers/gpu/drm/i915/i915_reg.h:7480:0: error: "CHASSIS_CLK_REQ_DURATION_MASK" redefined [-Werror]
#define CHASSIS_CLK_REQ_DURATION_MASK (0xf<<8)
drivers/gpu/drm/i915/i915_reg.h:7474:0: note: this is the location of the previous definition
#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
drivers/gpu/drm/i915/i915_reg.h:7481:0: error: "CHASSIS_CLK_REQ_DURATION" redefined [-Werror]
#define CHASSIS_CLK_REQ_DURATION(x) ((x)<<8)
drivers/gpu/drm/i915/i915_reg.h:7475:0: note: this is the location of the previous definition
#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
cc1: all warnings being treated as errors
scripts/Makefile.build:311: recipe for target 'drivers/gpu/drm/i915/i915_drv.o' failed
make[4]: *** [drivers/gpu/drm/i915/i915_drv.o] Error 1
scripts/Makefile.build:570: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:570: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:570: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1019: recipe for target 'drivers' failed
make: *** [drivers] Error 2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev3)
2017-09-19 20:28 ` ✗ Fi.CI.BAT: failure for series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev3) Patchwork
@ 2017-09-19 21:50 ` Rodrigo Vivi
0 siblings, 0 replies; 15+ messages in thread
From: Rodrigo Vivi @ 2017-09-19 21:50 UTC (permalink / raw)
To: intel-gfx
On Tue, Sep 19, 2017 at 08:28:16PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev3)
> URL : https://patchwork.freedesktop.org/series/30067/
> State : failure
>
> == Summary ==
>
> CHK include/config/kernel.release
> CHK include/generated/uapi/linux/version.h
> CHK include/generated/utsrelease.h
> CHK include/generated/bounds.h
> CHK include/generated/timeconst.h
> CHK include/generated/asm-offsets.h
> CALL scripts/checksyscalls.sh
> CHK scripts/mod/devicetable-offsets.h
> CHK include/generated/compile.h
> CHK kernel/config_data.h
> CC [M] drivers/gpu/drm/i915/i915_drv.o
> In file included from drivers/gpu/drm/i915/i915_drv.h:55:0,
> from drivers/gpu/drm/i915/i915_drv.c:49:
> drivers/gpu/drm/i915/i915_reg.h:7480:0: error: "CHASSIS_CLK_REQ_DURATION_MASK" redefined [-Werror]
> #define CHASSIS_CLK_REQ_DURATION_MASK (0xf<<8)
>
> drivers/gpu/drm/i915/i915_reg.h:7474:0: note: this is the location of the previous definition
> #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
>
> drivers/gpu/drm/i915/i915_reg.h:7481:0: error: "CHASSIS_CLK_REQ_DURATION" redefined [-Werror]
> #define CHASSIS_CLK_REQ_DURATION(x) ((x)<<8)
>
> drivers/gpu/drm/i915/i915_reg.h:7475:0: note: this is the location of the previous definition
> #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
It seems CI is not removing the previous version properly before applying this new version...
or something else similarly odd happening...
>
> cc1: all warnings being treated as errors
> scripts/Makefile.build:311: recipe for target 'drivers/gpu/drm/i915/i915_drv.o' failed
> make[4]: *** [drivers/gpu/drm/i915/i915_drv.o] Error 1
> scripts/Makefile.build:570: recipe for target 'drivers/gpu/drm/i915' failed
> make[3]: *** [drivers/gpu/drm/i915] Error 2
> scripts/Makefile.build:570: recipe for target 'drivers/gpu/drm' failed
> make[2]: *** [drivers/gpu/drm] Error 2
> scripts/Makefile.build:570: recipe for target 'drivers/gpu' failed
> make[1]: *** [drivers/gpu] Error 2
> Makefile:1019: recipe for target 'drivers' failed
> make: *** [drivers] Error 2
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2017-09-19 21:50 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-09-08 23:45 [PATCH 1/2] drm/i915/cnp: Don't touch other PCH clock gating bits Rodrigo Vivi
2017-09-08 23:45 ` [PATCH 2/2] drm/i915/cnp: Wa 1179 Rodrigo Vivi
2017-09-09 0:33 ` Pandiyan, Dhinakaran
2017-09-09 0:38 ` Vivi, Rodrigo
2017-09-09 1:55 ` Runyan, Arthur J
2017-09-18 23:56 ` [PATCH] drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug Rodrigo Vivi
2017-09-19 0:31 ` Pandiyan, Dhinakaran
2017-09-19 17:28 ` Rodrigo Vivi
2017-09-09 0:05 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnp: Don't touch other PCH clock gating bits Patchwork
2017-09-09 0:10 ` [PATCH 1/2] " Pandiyan, Dhinakaran
2017-09-18 23:25 ` Rodrigo Vivi
2017-09-09 1:11 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
2017-09-19 13:25 ` ✗ Fi.CI.BAT: warning for series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev2) Patchwork
2017-09-19 20:28 ` ✗ Fi.CI.BAT: failure for series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev3) Patchwork
2017-09-19 21:50 ` Rodrigo Vivi
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox