* [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs
@ 2017-09-20 18:35 Rodrigo Vivi
2017-09-20 18:35 ` [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status Rodrigo Vivi
` (4 more replies)
0 siblings, 5 replies; 21+ messages in thread
From: Rodrigo Vivi @ 2017-09-20 18:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Ben Widawsky, Rodrigo Vivi
From: Ben Widawsky <ben@bwidawsk.net>
Cannonlake Slice and Subslice information has changed.
This patch initially provided by Ben adds the proper sseu
initialization.
v2: This v2 done by Rodrigo includes:
- Fix on Total slices count by avoiding [1][2] and [2][2].
- Inclusion of EU Per Subslice.
- Commit message.
v3: This v3 done by Rodrigo includes:
- Handle all possible bits and extra fuse register.
- Use INTEL_GEN macro.
- Fully assume uniform distribution so remove union
with eu_per_subslice and add proper the comment.
v4: This v4 done by Rodrigo includes:
- Consider all bits available: 6 bits for slices [27:22]
and 4 for subslices [21:18].
v5: This v5 done by Rodrigo includes:
- sseu->subslice_mask = (1 << 4) - 1 - missed on previous
versions and noticed by Oscar.
Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 +++++++
drivers/gpu/drm/i915/intel_device_info.c | 37 +++++++++++++++++++++++++++++++-
2 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 82f36dd0cd94..1c257797c583 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2730,6 +2730,11 @@ enum i915_power_well_id {
#define GEN9_F2_SS_DIS_SHIFT 20
#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
+#define GEN10_F2_S_ENA_SHIFT 22
+#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
+#define GEN10_F2_SS_DIS_SHIFT 18
+#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
+
#define GEN8_EU_DISABLE0 _MMIO(0x9134)
#define GEN8_EU_DIS0_S0_MASK 0xffffff
#define GEN8_EU_DIS0_S1_SHIFT 24
@@ -2745,6 +2750,9 @@ enum i915_power_well_id {
#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
+#define GEN10_EU_DISABLE3 _MMIO(0x9140)
+#define GEN10_EU_DIS_SS_MASK 0xff
+
#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 43831b09b47a..d2e7ae61775d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv)
#undef PRINT_FLAG
}
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+ struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+ const u32 fuse2 = I915_READ(GEN8_FUSE2);
+
+ sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
+ GEN10_F2_S_ENA_SHIFT;
+ sseu->subslice_mask = (1 << 4) - 1;
+ sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+ GEN10_F2_SS_DIS_SHIFT);
+
+ sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
+ sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
+ sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
+ sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
+ GEN10_EU_DIS_SS_MASK));
+
+ /*
+ * CNL is expected to always have a uniform distribution
+ * of EU across subslices with the exception that any one
+ * EU in any one subslice may be fused off for die
+ * recovery.
+ */
+ sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
+ DIV_ROUND_UP(sseu->eu_total,
+ sseu_subslice_total(sseu)) : 0;
+
+ /* No restrictions on Power Gating */
+ sseu->has_slice_pg = 1;
+ sseu->has_subslice_pg = 1;
+ sseu->has_eu_pg = 1;
+}
+
static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
cherryview_sseu_info_init(dev_priv);
else if (IS_BROADWELL(dev_priv))
broadwell_sseu_info_init(dev_priv);
- else if (INTEL_INFO(dev_priv)->gen >= 9)
+ else if (INTEL_GEN(dev_priv) == 9)
gen9_sseu_info_init(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 10)
+ gen10_sseu_info_init(dev_priv);
DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
--
2.13.5
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^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.
2017-09-20 18:35 [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs Rodrigo Vivi
@ 2017-09-20 18:35 ` Rodrigo Vivi
2017-09-20 19:49 ` Oscar Mateo
2017-09-20 19:08 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs Patchwork
` (3 subsequent siblings)
4 siblings, 1 reply; 21+ messages in thread
From: Rodrigo Vivi @ 2017-09-20 18:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the die instead of other slices or anything like that.
Also if subslice is disabled the information of eu ack for that
is garbage, so let's skip checks for eu if subslice is disabled
as we skip the subslice if slice is disabled.
The rest is pretty much like gen9.
v2: Remove IS_CANNONLAKE from gen9 status function.
v3: Consider s_max = 6 and ss_max=4 to run over all possible
slices and subslices possible by spec. Although no real
hardware will have that many slices/subslices.
To match with sseu info init.
Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 54 +++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 6 +++++
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d122c6..e197e5d99277 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
}
}
+static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
+ struct sseu_dev_info *sseu)
+{
+ const struct intel_device_info *info = INTEL_INFO(dev_priv);
+ int s_max = 6, ss_max = 4;
+ int s, ss;
+ u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+
+ for (s = 0; s < s_max; s++) {
+ s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
+ eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
+ eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
+ }
+
+ eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+ GEN9_PGCTL_SSA_EU19_ACK |
+ GEN9_PGCTL_SSA_EU210_ACK |
+ GEN9_PGCTL_SSA_EU311_ACK;
+ eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+ GEN9_PGCTL_SSB_EU19_ACK |
+ GEN9_PGCTL_SSB_EU210_ACK |
+ GEN9_PGCTL_SSB_EU311_ACK;
+
+ for (s = 0; s < s_max; s++) {
+ if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+ /* skip disabled slice */
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+ sseu->subslice_mask = info->sseu.subslice_mask;
+
+ for (ss = 0; ss < ss_max; ss++) {
+ unsigned int eu_cnt;
+
+ if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
+ /* skip disabled subslice */
+ continue;
+
+ eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
+ eu_mask[ss % 2]);
+ sseu->eu_total += eu_cnt;
+ sseu->eu_per_subslice = max_t(unsigned int,
+ sseu->eu_per_subslice,
+ eu_cnt);
+ }
+ }
+}
+
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
@@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
- if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
+ if (IS_GEN9_BC(dev_priv))
sseu->subslice_mask =
INTEL_INFO(dev_priv)->sseu.subslice_mask;
@@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
cherryview_sseu_device_status(dev_priv, &sseu);
} else if (IS_BROADWELL(dev_priv)) {
broadwell_sseu_device_status(dev_priv, &sseu);
- } else if (INTEL_GEN(dev_priv) >= 9) {
+ } else if (IS_GEN9(dev_priv)) {
gen9_sseu_device_status(dev_priv, &sseu);
+ } else if (INTEL_GEN(dev_priv) >= 10) {
+ gen10_sseu_device_status(dev_priv, &sseu);
}
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c257797c583..ac5c8e08878d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8020,11 +8020,17 @@ enum {
#define CHV_EU311_PG_ENABLE (1<<1)
#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
+#define GEN10_SLICE_PGCTL_ACK(slice) ((slice) == 3 ? _MMIO(0x8080) : \
+ GEN9_SLICE_PGCTL_ACK((slice)))
#define GEN9_PGCTL_SLICE_ACK (1 << 0)
#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
+#define GEN10_SS01_EU_PGCTL_ACK(slice) ((slice) == 3 ? _MMIO(0x808c) : \
+ GEN9_SS01_EU_PGCTL_ACK((slice)))
#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
+#define GEN10_SS23_EU_PGCTL_ACK(slice) ((slice) == 3 ? _MMIO(0x8090) : \
+ GEN9_SS23_EU_PGCTL_ACK((slice)))
#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
--
2.13.5
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.
2017-09-20 18:35 ` [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status Rodrigo Vivi
@ 2017-09-20 19:49 ` Oscar Mateo
2017-09-22 13:15 ` [PATCH] " Rodrigo Vivi
0 siblings, 1 reply; 21+ messages in thread
From: Oscar Mateo @ 2017-09-20 19:49 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx
On 09/20/2017 11:35 AM, Rodrigo Vivi wrote:
> CNL adds an extra register for slice/subslice information.
> Although no SKU is planed with an extra slice let's already
> handle this extra piece of information so we don't have the
> risk in future of getting a part that might have chosen this
> part of the die instead of other slices or anything like that.
>
> Also if subslice is disabled the information of eu ack for that
> is garbage, so let's skip checks for eu if subslice is disabled
> as we skip the subslice if slice is disabled.
>
> The rest is pretty much like gen9.
>
> v2: Remove IS_CANNONLAKE from gen9 status function.
>
> v3: Consider s_max = 6 and ss_max=4 to run over all possible
> slices and subslices possible by spec. Although no real
> hardware will have that many slices/subslices.
> To match with sseu info init.
Even better :)
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 54 +++++++++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 6 +++++
> 2 files changed, 58 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index ca6fa6d122c6..e197e5d99277 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
> }
> }
>
> +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> + struct sseu_dev_info *sseu)
> +{
> + const struct intel_device_info *info = INTEL_INFO(dev_priv);
> + int s_max = 6, ss_max = 4;
> + int s, ss;
> + u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
> +
> + for (s = 0; s < s_max; s++) {
> + s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
> + eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> + eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> + }
> +
> + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> + GEN9_PGCTL_SSA_EU19_ACK |
> + GEN9_PGCTL_SSA_EU210_ACK |
> + GEN9_PGCTL_SSA_EU311_ACK;
> + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> + GEN9_PGCTL_SSB_EU19_ACK |
> + GEN9_PGCTL_SSB_EU210_ACK |
> + GEN9_PGCTL_SSB_EU311_ACK;
> +
> + for (s = 0; s < s_max; s++) {
> + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> + /* skip disabled slice */
> + continue;
> +
> + sseu->slice_mask |= BIT(s);
> + sseu->subslice_mask = info->sseu.subslice_mask;
> +
> + for (ss = 0; ss < ss_max; ss++) {
> + unsigned int eu_cnt;
> +
> + if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> + /* skip disabled subslice */
> + continue;
> +
> + eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> + eu_mask[ss % 2]);
> + sseu->eu_total += eu_cnt;
> + sseu->eu_per_subslice = max_t(unsigned int,
> + sseu->eu_per_subslice,
> + eu_cnt);
> + }
> + }
> +}
> +
> static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> struct sseu_dev_info *sseu)
> {
> @@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>
> sseu->slice_mask |= BIT(s);
>
> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> + if (IS_GEN9_BC(dev_priv))
> sseu->subslice_mask =
> INTEL_INFO(dev_priv)->sseu.subslice_mask;
>
> @@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
> cherryview_sseu_device_status(dev_priv, &sseu);
> } else if (IS_BROADWELL(dev_priv)) {
> broadwell_sseu_device_status(dev_priv, &sseu);
> - } else if (INTEL_GEN(dev_priv) >= 9) {
> + } else if (IS_GEN9(dev_priv)) {
> gen9_sseu_device_status(dev_priv, &sseu);
> + } else if (INTEL_GEN(dev_priv) >= 10) {
> + gen10_sseu_device_status(dev_priv, &sseu);
> }
>
> intel_runtime_pm_put(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1c257797c583..ac5c8e08878d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8020,11 +8020,17 @@ enum {
> #define CHV_EU311_PG_ENABLE (1<<1)
>
I'm afraid the following now requires extra defines for slice = 4 and 5:
> #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
> +#define GEN10_SLICE_PGCTL_ACK(slice) ((slice) == 3 ? _MMIO(0x8080) : \
> + GEN9_SLICE_PGCTL_ACK((slice)))
0x8080 + (slice)*0x4
> #define GEN9_PGCTL_SLICE_ACK (1 << 0)
> #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
>
> #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
> +#define GEN10_SS01_EU_PGCTL_ACK(slice) ((slice) == 3 ? _MMIO(0x808c) : \
> + GEN9_SS01_EU_PGCTL_ACK((slice)))
0x808c + (slice)*0x8
> #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
> +#define GEN10_SS23_EU_PGCTL_ACK(slice) ((slice) == 3 ? _MMIO(0x8090) : \
> + GEN9_SS23_EU_PGCTL_ACK((slice)))
0x8090 + (slice)*0x8
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^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH] drm/i915/cnl: Fix SSEU Device Status.
2017-09-20 19:49 ` Oscar Mateo
@ 2017-09-22 13:15 ` Rodrigo Vivi
2017-09-22 16:44 ` Oscar Mateo
0 siblings, 1 reply; 21+ messages in thread
From: Rodrigo Vivi @ 2017-09-22 13:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the die instead of other slices or anything like that.
Also if subslice is disabled the information of eu ack for that
is garbage, so let's skip checks for eu if subslice is disabled
as we skip the subslice if slice is disabled.
The rest is pretty much like gen9.
v2: Remove IS_CANNONLAKE from gen9 status function.
v3: Consider s_max = 6 and ss_max=4 to run over all possible
slices and subslices possible by spec. Although no real
hardware will have that many slices/subslices.
To match with sseu info init.
v4: Fix offset calculation for slices 4 and 5.
Removed Oscar's rv-b since this change also needs review.
Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 54 +++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 6 +++++
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d122c6..e197e5d99277 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
}
}
+static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
+ struct sseu_dev_info *sseu)
+{
+ const struct intel_device_info *info = INTEL_INFO(dev_priv);
+ int s_max = 6, ss_max = 4;
+ int s, ss;
+ u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+
+ for (s = 0; s < s_max; s++) {
+ s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
+ eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
+ eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
+ }
+
+ eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+ GEN9_PGCTL_SSA_EU19_ACK |
+ GEN9_PGCTL_SSA_EU210_ACK |
+ GEN9_PGCTL_SSA_EU311_ACK;
+ eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+ GEN9_PGCTL_SSB_EU19_ACK |
+ GEN9_PGCTL_SSB_EU210_ACK |
+ GEN9_PGCTL_SSB_EU311_ACK;
+
+ for (s = 0; s < s_max; s++) {
+ if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+ /* skip disabled slice */
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+ sseu->subslice_mask = info->sseu.subslice_mask;
+
+ for (ss = 0; ss < ss_max; ss++) {
+ unsigned int eu_cnt;
+
+ if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
+ /* skip disabled subslice */
+ continue;
+
+ eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
+ eu_mask[ss % 2]);
+ sseu->eu_total += eu_cnt;
+ sseu->eu_per_subslice = max_t(unsigned int,
+ sseu->eu_per_subslice,
+ eu_cnt);
+ }
+ }
+}
+
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
@@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
- if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
+ if (IS_GEN9_BC(dev_priv))
sseu->subslice_mask =
INTEL_INFO(dev_priv)->sseu.subslice_mask;
@@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
cherryview_sseu_device_status(dev_priv, &sseu);
} else if (IS_BROADWELL(dev_priv)) {
broadwell_sseu_device_status(dev_priv, &sseu);
- } else if (INTEL_GEN(dev_priv) >= 9) {
+ } else if (IS_GEN9(dev_priv)) {
gen9_sseu_device_status(dev_priv, &sseu);
+ } else if (INTEL_GEN(dev_priv) >= 10) {
+ gen10_sseu_device_status(dev_priv, &sseu);
}
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c257797c583..9729145e6c03 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8020,11 +8020,17 @@ enum {
#define CHV_EU311_PG_ENABLE (1<<1)
#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
+#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
+ ((slice) % 3) * 0x4)
#define GEN9_PGCTL_SLICE_ACK (1 << 0)
#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
+#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
+ ((slice) % 3) * 0x8)
#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
+#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
+ ((slice) % 3) * 0x8)
#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
--
2.13.5
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^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH] drm/i915/cnl: Fix SSEU Device Status.
2017-09-22 13:15 ` [PATCH] " Rodrigo Vivi
@ 2017-09-22 16:44 ` Oscar Mateo
2017-09-22 18:32 ` Rodrigo Vivi
0 siblings, 1 reply; 21+ messages in thread
From: Oscar Mateo @ 2017-09-22 16:44 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx
On 09/22/2017 06:15 AM, Rodrigo Vivi wrote:
> CNL adds an extra register for slice/subslice information.
> Although no SKU is planed with an extra slice let's already
> handle this extra piece of information so we don't have the
> risk in future of getting a part that might have chosen this
> part of the die instead of other slices or anything like that.
>
> Also if subslice is disabled the information of eu ack for that
> is garbage, so let's skip checks for eu if subslice is disabled
> as we skip the subslice if slice is disabled.
>
> The rest is pretty much like gen9.
>
> v2: Remove IS_CANNONLAKE from gen9 status function.
>
> v3: Consider s_max = 6 and ss_max=4 to run over all possible
> slices and subslices possible by spec. Although no real
> hardware will have that many slices/subslices.
> To match with sseu info init.
> v4: Fix offset calculation for slices 4 and 5.
> Removed Oscar's rv-b since this change also needs review.
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 54 +++++++++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 6 +++++
> 2 files changed, 58 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index ca6fa6d122c6..e197e5d99277 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
> }
> }
>
> +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> + struct sseu_dev_info *sseu)
> +{
> + const struct intel_device_info *info = INTEL_INFO(dev_priv);
> + int s_max = 6, ss_max = 4;
> + int s, ss;
> + u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
> +
> + for (s = 0; s < s_max; s++) {
> + s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
> + eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> + eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> + }
> +
> + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> + GEN9_PGCTL_SSA_EU19_ACK |
> + GEN9_PGCTL_SSA_EU210_ACK |
> + GEN9_PGCTL_SSA_EU311_ACK;
> + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> + GEN9_PGCTL_SSB_EU19_ACK |
> + GEN9_PGCTL_SSB_EU210_ACK |
> + GEN9_PGCTL_SSB_EU311_ACK;
> +
> + for (s = 0; s < s_max; s++) {
> + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> + /* skip disabled slice */
> + continue;
> +
> + sseu->slice_mask |= BIT(s);
> + sseu->subslice_mask = info->sseu.subslice_mask;
> +
> + for (ss = 0; ss < ss_max; ss++) {
> + unsigned int eu_cnt;
> +
> + if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> + /* skip disabled subslice */
> + continue;
You are going to hate me, but I found something else:
SLICE0_PGCTL_ACK has powergate acknowledge bits for subslices 0, 1 & 2,
but not for subslice 3
SLICEn_PGCTL_ACK (where n = 1-5) has powergate acknowledge bits for
subslices 0 & 1, but not for subslices 2 & 3
I have no idea where the missing bits went (maybe the BSpec is wrong?).
> +
> + eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> + eu_mask[ss % 2]);
> + sseu->eu_total += eu_cnt;
> + sseu->eu_per_subslice = max_t(unsigned int,
> + sseu->eu_per_subslice,
> + eu_cnt);
> + }
> + }
> +}
> +
> static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> struct sseu_dev_info *sseu)
> {
> @@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>
> sseu->slice_mask |= BIT(s);
>
> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> + if (IS_GEN9_BC(dev_priv))
> sseu->subslice_mask =
> INTEL_INFO(dev_priv)->sseu.subslice_mask;
>
> @@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
> cherryview_sseu_device_status(dev_priv, &sseu);
> } else if (IS_BROADWELL(dev_priv)) {
> broadwell_sseu_device_status(dev_priv, &sseu);
> - } else if (INTEL_GEN(dev_priv) >= 9) {
> + } else if (IS_GEN9(dev_priv)) {
> gen9_sseu_device_status(dev_priv, &sseu);
> + } else if (INTEL_GEN(dev_priv) >= 10) {
> + gen10_sseu_device_status(dev_priv, &sseu);
> }
>
> intel_runtime_pm_put(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1c257797c583..9729145e6c03 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8020,11 +8020,17 @@ enum {
> #define CHV_EU311_PG_ENABLE (1<<1)
>
> #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
> +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> + ((slice) % 3) * 0x4)
> #define GEN9_PGCTL_SLICE_ACK (1 << 0)
> #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
>
> #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
> +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
> + ((slice) % 3) * 0x8)
> #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
> +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
> + ((slice) % 3) * 0x8)
> #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
> #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
> #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
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^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH] drm/i915/cnl: Fix SSEU Device Status.
2017-09-22 16:44 ` Oscar Mateo
@ 2017-09-22 18:32 ` Rodrigo Vivi
2017-09-26 20:06 ` Rodrigo Vivi
0 siblings, 1 reply; 21+ messages in thread
From: Rodrigo Vivi @ 2017-09-22 18:32 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
On Fri, Sep 22, 2017 at 04:44:38PM +0000, Oscar Mateo wrote:
>
>
> On 09/22/2017 06:15 AM, Rodrigo Vivi wrote:
> > CNL adds an extra register for slice/subslice information.
> > Although no SKU is planed with an extra slice let's already
> > handle this extra piece of information so we don't have the
> > risk in future of getting a part that might have chosen this
> > part of the die instead of other slices or anything like that.
> >
> > Also if subslice is disabled the information of eu ack for that
> > is garbage, so let's skip checks for eu if subslice is disabled
> > as we skip the subslice if slice is disabled.
> >
> > The rest is pretty much like gen9.
> >
> > v2: Remove IS_CANNONLAKE from gen9 status function.
> >
> > v3: Consider s_max = 6 and ss_max=4 to run over all possible
> > slices and subslices possible by spec. Although no real
> > hardware will have that many slices/subslices.
> > To match with sseu info init.
> > v4: Fix offset calculation for slices 4 and 5.
> > Removed Oscar's rv-b since this change also needs review.
> >
> > Cc: Oscar Mateo <oscar.mateo@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 54 +++++++++++++++++++++++++++++++++++--
> > drivers/gpu/drm/i915/i915_reg.h | 6 +++++
> > 2 files changed, 58 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index ca6fa6d122c6..e197e5d99277 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
> > }
> > }
> > +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> > + struct sseu_dev_info *sseu)
> > +{
> > + const struct intel_device_info *info = INTEL_INFO(dev_priv);
> > + int s_max = 6, ss_max = 4;
> > + int s, ss;
> > + u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
> > +
> > + for (s = 0; s < s_max; s++) {
> > + s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
> > + eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> > + eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> > + }
> > +
> > + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> > + GEN9_PGCTL_SSA_EU19_ACK |
> > + GEN9_PGCTL_SSA_EU210_ACK |
> > + GEN9_PGCTL_SSA_EU311_ACK;
> > + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> > + GEN9_PGCTL_SSB_EU19_ACK |
> > + GEN9_PGCTL_SSB_EU210_ACK |
> > + GEN9_PGCTL_SSB_EU311_ACK;
> > +
> > + for (s = 0; s < s_max; s++) {
> > + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> > + /* skip disabled slice */
> > + continue;
> > +
> > + sseu->slice_mask |= BIT(s);
> > + sseu->subslice_mask = info->sseu.subslice_mask;
> > +
> > + for (ss = 0; ss < ss_max; ss++) {
> > + unsigned int eu_cnt;
> > +
> > + if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> > + /* skip disabled subslice */
> > + continue;
>
> You are going to hate me, but I found something else:
Should I hate you for being a good reviewer? ;)
You should hate me for not noticing that before...
Thanks a lot for the patience
>
> SLICE0_PGCTL_ACK has powergate acknowledge bits for subslices 0, 1 & 2, but
> not for subslice 3
> SLICEn_PGCTL_ACK (where n = 1-5) has powergate acknowledge bits for
> subslices 0 & 1, but not for subslices 2 & 3
hmmm... :(
I will check...
>
> I have no idea where the missing bits went (maybe the BSpec is wrong?).
Do you know anyone at your end that could help us to clarify that?
Thanks,
Rodrigo.
>
> > +
> > + eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> > + eu_mask[ss % 2]);
> > + sseu->eu_total += eu_cnt;
> > + sseu->eu_per_subslice = max_t(unsigned int,
> > + sseu->eu_per_subslice,
> > + eu_cnt);
> > + }
> > + }
> > +}
> > +
> > static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > struct sseu_dev_info *sseu)
> > {
> > @@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > sseu->slice_mask |= BIT(s);
> > - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> > + if (IS_GEN9_BC(dev_priv))
> > sseu->subslice_mask =
> > INTEL_INFO(dev_priv)->sseu.subslice_mask;
> > @@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
> > cherryview_sseu_device_status(dev_priv, &sseu);
> > } else if (IS_BROADWELL(dev_priv)) {
> > broadwell_sseu_device_status(dev_priv, &sseu);
> > - } else if (INTEL_GEN(dev_priv) >= 9) {
> > + } else if (IS_GEN9(dev_priv)) {
> > gen9_sseu_device_status(dev_priv, &sseu);
> > + } else if (INTEL_GEN(dev_priv) >= 10) {
> > + gen10_sseu_device_status(dev_priv, &sseu);
> > }
> > intel_runtime_pm_put(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 1c257797c583..9729145e6c03 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8020,11 +8020,17 @@ enum {
> > #define CHV_EU311_PG_ENABLE (1<<1)
> > #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
> > +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> > + ((slice) % 3) * 0x4)
> > #define GEN9_PGCTL_SLICE_ACK (1 << 0)
> > #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
> > #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
> > +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
> > + ((slice) % 3) * 0x8)
> > #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
> > +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
> > + ((slice) % 3) * 0x8)
> > #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
> > #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
> > #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
>
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^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH] drm/i915/cnl: Fix SSEU Device Status.
2017-09-22 18:32 ` Rodrigo Vivi
@ 2017-09-26 20:06 ` Rodrigo Vivi
2017-09-27 12:16 ` Daniel Vetter
0 siblings, 1 reply; 21+ messages in thread
From: Rodrigo Vivi @ 2017-09-26 20:06 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
On Fri, Sep 22, 2017 at 06:32:04PM +0000, Rodrigo Vivi wrote:
> On Fri, Sep 22, 2017 at 04:44:38PM +0000, Oscar Mateo wrote:
> >
> >
> > On 09/22/2017 06:15 AM, Rodrigo Vivi wrote:
> > > CNL adds an extra register for slice/subslice information.
> > > Although no SKU is planed with an extra slice let's already
> > > handle this extra piece of information so we don't have the
> > > risk in future of getting a part that might have chosen this
> > > part of the die instead of other slices or anything like that.
> > >
> > > Also if subslice is disabled the information of eu ack for that
> > > is garbage, so let's skip checks for eu if subslice is disabled
> > > as we skip the subslice if slice is disabled.
> > >
> > > The rest is pretty much like gen9.
> > >
> > > v2: Remove IS_CANNONLAKE from gen9 status function.
> > >
> > > v3: Consider s_max = 6 and ss_max=4 to run over all possible
> > > slices and subslices possible by spec. Although no real
> > > hardware will have that many slices/subslices.
> > > To match with sseu info init.
> > > v4: Fix offset calculation for slices 4 and 5.
> > > Removed Oscar's rv-b since this change also needs review.
> > >
> > > Cc: Oscar Mateo <oscar.mateo@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_debugfs.c | 54 +++++++++++++++++++++++++++++++++++--
> > > drivers/gpu/drm/i915/i915_reg.h | 6 +++++
> > > 2 files changed, 58 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index ca6fa6d122c6..e197e5d99277 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
> > > }
> > > }
> > > +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> > > + struct sseu_dev_info *sseu)
> > > +{
> > > + const struct intel_device_info *info = INTEL_INFO(dev_priv);
> > > + int s_max = 6, ss_max = 4;
> > > + int s, ss;
> > > + u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
> > > +
> > > + for (s = 0; s < s_max; s++) {
> > > + s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
> > > + eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> > > + eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> > > + }
> > > +
> > > + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> > > + GEN9_PGCTL_SSA_EU19_ACK |
> > > + GEN9_PGCTL_SSA_EU210_ACK |
> > > + GEN9_PGCTL_SSA_EU311_ACK;
> > > + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> > > + GEN9_PGCTL_SSB_EU19_ACK |
> > > + GEN9_PGCTL_SSB_EU210_ACK |
> > > + GEN9_PGCTL_SSB_EU311_ACK;
> > > +
> > > + for (s = 0; s < s_max; s++) {
> > > + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> > > + /* skip disabled slice */
> > > + continue;
> > > +
> > > + sseu->slice_mask |= BIT(s);
> > > + sseu->subslice_mask = info->sseu.subslice_mask;
> > > +
> > > + for (ss = 0; ss < ss_max; ss++) {
> > > + unsigned int eu_cnt;
> > > +
> > > + if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> > > + /* skip disabled subslice */
> > > + continue;
> >
> > You are going to hate me, but I found something else:
>
> Should I hate you for being a good reviewer? ;)
> You should hate me for not noticing that before...
> Thanks a lot for the patience
>
> >
> > SLICE0_PGCTL_ACK has powergate acknowledge bits for subslices 0, 1 & 2, but
> > not for subslice 3
> > SLICEn_PGCTL_ACK (where n = 1-5) has powergate acknowledge bits for
> > subslices 0 & 1, but not for subslices 2 & 3
>
> hmmm... :(
> I will check...
>
> >
> > I have no idea where the missing bits went (maybe the BSpec is wrong?).
>
> Do you know anyone at your end that could help us to clarify that?
Based on the emails it seems that it is a spec bug. But we are
not going to merge this patch 2/2 while we don't get the official confirmation.
Meanwhile we need the first patch for userspace, so
I merged the first patch on dinq while we solve this mistery.
Thanks for all the reviews.
>
> Thanks,
> Rodrigo.
>
> >
> > > +
> > > + eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> > > + eu_mask[ss % 2]);
> > > + sseu->eu_total += eu_cnt;
> > > + sseu->eu_per_subslice = max_t(unsigned int,
> > > + sseu->eu_per_subslice,
> > > + eu_cnt);
> > > + }
> > > + }
> > > +}
> > > +
> > > static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > > struct sseu_dev_info *sseu)
> > > {
> > > @@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > > sseu->slice_mask |= BIT(s);
> > > - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> > > + if (IS_GEN9_BC(dev_priv))
> > > sseu->subslice_mask =
> > > INTEL_INFO(dev_priv)->sseu.subslice_mask;
> > > @@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
> > > cherryview_sseu_device_status(dev_priv, &sseu);
> > > } else if (IS_BROADWELL(dev_priv)) {
> > > broadwell_sseu_device_status(dev_priv, &sseu);
> > > - } else if (INTEL_GEN(dev_priv) >= 9) {
> > > + } else if (IS_GEN9(dev_priv)) {
> > > gen9_sseu_device_status(dev_priv, &sseu);
> > > + } else if (INTEL_GEN(dev_priv) >= 10) {
> > > + gen10_sseu_device_status(dev_priv, &sseu);
> > > }
> > > intel_runtime_pm_put(dev_priv);
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 1c257797c583..9729145e6c03 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -8020,11 +8020,17 @@ enum {
> > > #define CHV_EU311_PG_ENABLE (1<<1)
> > > #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
> > > +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> > > + ((slice) % 3) * 0x4)
> > > #define GEN9_PGCTL_SLICE_ACK (1 << 0)
> > > #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
> > > #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
> > > +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
> > > + ((slice) % 3) * 0x8)
> > > #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
> > > +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
> > > + ((slice) % 3) * 0x8)
> > > #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
> > > #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
> > > #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH] drm/i915/cnl: Fix SSEU Device Status.
2017-09-26 20:06 ` Rodrigo Vivi
@ 2017-09-27 12:16 ` Daniel Vetter
2017-09-27 14:28 ` Rodrigo Vivi
0 siblings, 1 reply; 21+ messages in thread
From: Daniel Vetter @ 2017-09-27 12:16 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Sep 26, 2017 at 01:06:22PM -0700, Rodrigo Vivi wrote:
> On Fri, Sep 22, 2017 at 06:32:04PM +0000, Rodrigo Vivi wrote:
> > On Fri, Sep 22, 2017 at 04:44:38PM +0000, Oscar Mateo wrote:
> > >
> > >
> > > On 09/22/2017 06:15 AM, Rodrigo Vivi wrote:
> > > > CNL adds an extra register for slice/subslice information.
> > > > Although no SKU is planed with an extra slice let's already
> > > > handle this extra piece of information so we don't have the
> > > > risk in future of getting a part that might have chosen this
> > > > part of the die instead of other slices or anything like that.
> > > >
> > > > Also if subslice is disabled the information of eu ack for that
> > > > is garbage, so let's skip checks for eu if subslice is disabled
> > > > as we skip the subslice if slice is disabled.
> > > >
> > > > The rest is pretty much like gen9.
> > > >
> > > > v2: Remove IS_CANNONLAKE from gen9 status function.
> > > >
> > > > v3: Consider s_max = 6 and ss_max=4 to run over all possible
> > > > slices and subslices possible by spec. Although no real
> > > > hardware will have that many slices/subslices.
> > > > To match with sseu info init.
> > > > v4: Fix offset calculation for slices 4 and 5.
> > > > Removed Oscar's rv-b since this change also needs review.
> > > >
> > > > Cc: Oscar Mateo <oscar.mateo@intel.com>
> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/i915_debugfs.c | 54 +++++++++++++++++++++++++++++++++++--
> > > > drivers/gpu/drm/i915/i915_reg.h | 6 +++++
> > > > 2 files changed, 58 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > index ca6fa6d122c6..e197e5d99277 100644
> > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > @@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
> > > > }
> > > > }
> > > > +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> > > > + struct sseu_dev_info *sseu)
> > > > +{
> > > > + const struct intel_device_info *info = INTEL_INFO(dev_priv);
> > > > + int s_max = 6, ss_max = 4;
> > > > + int s, ss;
> > > > + u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
> > > > +
> > > > + for (s = 0; s < s_max; s++) {
> > > > + s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
> > > > + eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> > > > + eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> > > > + }
> > > > +
> > > > + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> > > > + GEN9_PGCTL_SSA_EU19_ACK |
> > > > + GEN9_PGCTL_SSA_EU210_ACK |
> > > > + GEN9_PGCTL_SSA_EU311_ACK;
> > > > + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> > > > + GEN9_PGCTL_SSB_EU19_ACK |
> > > > + GEN9_PGCTL_SSB_EU210_ACK |
> > > > + GEN9_PGCTL_SSB_EU311_ACK;
> > > > +
> > > > + for (s = 0; s < s_max; s++) {
> > > > + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> > > > + /* skip disabled slice */
> > > > + continue;
> > > > +
> > > > + sseu->slice_mask |= BIT(s);
> > > > + sseu->subslice_mask = info->sseu.subslice_mask;
> > > > +
> > > > + for (ss = 0; ss < ss_max; ss++) {
> > > > + unsigned int eu_cnt;
> > > > +
> > > > + if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> > > > + /* skip disabled subslice */
> > > > + continue;
> > >
> > > You are going to hate me, but I found something else:
> >
> > Should I hate you for being a good reviewer? ;)
> > You should hate me for not noticing that before...
> > Thanks a lot for the patience
> >
> > >
> > > SLICE0_PGCTL_ACK has powergate acknowledge bits for subslices 0, 1 & 2, but
> > > not for subslice 3
> > > SLICEn_PGCTL_ACK (where n = 1-5) has powergate acknowledge bits for
> > > subslices 0 & 1, but not for subslices 2 & 3
> >
> > hmmm... :(
> > I will check...
> >
> > >
> > > I have no idea where the missing bits went (maybe the BSpec is wrong?).
> >
> > Do you know anyone at your end that could help us to clarify that?
>
> Based on the emails it seems that it is a spec bug. But we are
> not going to merge this patch 2/2 while we don't get the official confirmation.
>
> Meanwhile we need the first patch for userspace, so
> I merged the first patch on dinq while we solve this mistery.
Not sure I remember correctly, but iirc the userspace for this was
media/compute. If that's correct, do we have this open-sourced? Otherwise
we need to add this to the list of things we might need to revert :-/
-Daniel
>
> Thanks for all the reviews.
>
> >
> > Thanks,
> > Rodrigo.
> >
> > >
> > > > +
> > > > + eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> > > > + eu_mask[ss % 2]);
> > > > + sseu->eu_total += eu_cnt;
> > > > + sseu->eu_per_subslice = max_t(unsigned int,
> > > > + sseu->eu_per_subslice,
> > > > + eu_cnt);
> > > > + }
> > > > + }
> > > > +}
> > > > +
> > > > static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > > > struct sseu_dev_info *sseu)
> > > > {
> > > > @@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > > > sseu->slice_mask |= BIT(s);
> > > > - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> > > > + if (IS_GEN9_BC(dev_priv))
> > > > sseu->subslice_mask =
> > > > INTEL_INFO(dev_priv)->sseu.subslice_mask;
> > > > @@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
> > > > cherryview_sseu_device_status(dev_priv, &sseu);
> > > > } else if (IS_BROADWELL(dev_priv)) {
> > > > broadwell_sseu_device_status(dev_priv, &sseu);
> > > > - } else if (INTEL_GEN(dev_priv) >= 9) {
> > > > + } else if (IS_GEN9(dev_priv)) {
> > > > gen9_sseu_device_status(dev_priv, &sseu);
> > > > + } else if (INTEL_GEN(dev_priv) >= 10) {
> > > > + gen10_sseu_device_status(dev_priv, &sseu);
> > > > }
> > > > intel_runtime_pm_put(dev_priv);
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 1c257797c583..9729145e6c03 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -8020,11 +8020,17 @@ enum {
> > > > #define CHV_EU311_PG_ENABLE (1<<1)
> > > > #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
> > > > +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> > > > + ((slice) % 3) * 0x4)
> > > > #define GEN9_PGCTL_SLICE_ACK (1 << 0)
> > > > #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
> > > > #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
> > > > +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
> > > > + ((slice) % 3) * 0x8)
> > > > #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
> > > > +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
> > > > + ((slice) % 3) * 0x8)
> > > > #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
> > > > #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
> > > > #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
> > >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH] drm/i915/cnl: Fix SSEU Device Status.
2017-09-27 12:16 ` Daniel Vetter
@ 2017-09-27 14:28 ` Rodrigo Vivi
0 siblings, 0 replies; 21+ messages in thread
From: Rodrigo Vivi @ 2017-09-27 14:28 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Wed, Sep 27, 2017 at 12:16:20PM +0000, Daniel Vetter wrote:
> On Tue, Sep 26, 2017 at 01:06:22PM -0700, Rodrigo Vivi wrote:
> > On Fri, Sep 22, 2017 at 06:32:04PM +0000, Rodrigo Vivi wrote:
> > > On Fri, Sep 22, 2017 at 04:44:38PM +0000, Oscar Mateo wrote:
> > > >
> > > >
> > > > On 09/22/2017 06:15 AM, Rodrigo Vivi wrote:
> > > > > CNL adds an extra register for slice/subslice information.
> > > > > Although no SKU is planed with an extra slice let's already
> > > > > handle this extra piece of information so we don't have the
> > > > > risk in future of getting a part that might have chosen this
> > > > > part of the die instead of other slices or anything like that.
> > > > >
> > > > > Also if subslice is disabled the information of eu ack for that
> > > > > is garbage, so let's skip checks for eu if subslice is disabled
> > > > > as we skip the subslice if slice is disabled.
> > > > >
> > > > > The rest is pretty much like gen9.
> > > > >
> > > > > v2: Remove IS_CANNONLAKE from gen9 status function.
> > > > >
> > > > > v3: Consider s_max = 6 and ss_max=4 to run over all possible
> > > > > slices and subslices possible by spec. Although no real
> > > > > hardware will have that many slices/subslices.
> > > > > To match with sseu info init.
> > > > > v4: Fix offset calculation for slices 4 and 5.
> > > > > Removed Oscar's rv-b since this change also needs review.
> > > > >
> > > > > Cc: Oscar Mateo <oscar.mateo@intel.com>
> > > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/i915_debugfs.c | 54 +++++++++++++++++++++++++++++++++++--
> > > > > drivers/gpu/drm/i915/i915_reg.h | 6 +++++
> > > > > 2 files changed, 58 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > index ca6fa6d122c6..e197e5d99277 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > @@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
> > > > > }
> > > > > }
> > > > > +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> > > > > + struct sseu_dev_info *sseu)
> > > > > +{
> > > > > + const struct intel_device_info *info = INTEL_INFO(dev_priv);
> > > > > + int s_max = 6, ss_max = 4;
> > > > > + int s, ss;
> > > > > + u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
> > > > > +
> > > > > + for (s = 0; s < s_max; s++) {
> > > > > + s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
> > > > > + eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> > > > > + eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> > > > > + }
> > > > > +
> > > > > + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> > > > > + GEN9_PGCTL_SSA_EU19_ACK |
> > > > > + GEN9_PGCTL_SSA_EU210_ACK |
> > > > > + GEN9_PGCTL_SSA_EU311_ACK;
> > > > > + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> > > > > + GEN9_PGCTL_SSB_EU19_ACK |
> > > > > + GEN9_PGCTL_SSB_EU210_ACK |
> > > > > + GEN9_PGCTL_SSB_EU311_ACK;
> > > > > +
> > > > > + for (s = 0; s < s_max; s++) {
> > > > > + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> > > > > + /* skip disabled slice */
> > > > > + continue;
> > > > > +
> > > > > + sseu->slice_mask |= BIT(s);
> > > > > + sseu->subslice_mask = info->sseu.subslice_mask;
> > > > > +
> > > > > + for (ss = 0; ss < ss_max; ss++) {
> > > > > + unsigned int eu_cnt;
> > > > > +
> > > > > + if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> > > > > + /* skip disabled subslice */
> > > > > + continue;
> > > >
> > > > You are going to hate me, but I found something else:
> > >
> > > Should I hate you for being a good reviewer? ;)
> > > You should hate me for not noticing that before...
> > > Thanks a lot for the patience
> > >
> > > >
> > > > SLICE0_PGCTL_ACK has powergate acknowledge bits for subslices 0, 1 & 2, but
> > > > not for subslice 3
> > > > SLICEn_PGCTL_ACK (where n = 1-5) has powergate acknowledge bits for
> > > > subslices 0 & 1, but not for subslices 2 & 3
> > >
> > > hmmm... :(
> > > I will check...
> > >
> > > >
> > > > I have no idea where the missing bits went (maybe the BSpec is wrong?).
> > >
> > > Do you know anyone at your end that could help us to clarify that?
> >
> > Based on the emails it seems that it is a spec bug. But we are
> > not going to merge this patch 2/2 while we don't get the official confirmation.
> >
> > Meanwhile we need the first patch for userspace, so
> > I merged the first patch on dinq while we solve this mistery.
>
> Not sure I remember correctly, but iirc the userspace for this was
> media/compute. If that's correct, do we have this open-sourced? Otherwise
> we need to add this to the list of things we might need to revert :-/
I think initially was only media, but nowadays Mesa is using it.
This was the last think blocking them to fully move from the
internal to drm-tip.
Thanks,
Rodrigo.
> -Daniel
>
> >
> > Thanks for all the reviews.
> >
> > >
> > > Thanks,
> > > Rodrigo.
> > >
> > > >
> > > > > +
> > > > > + eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> > > > > + eu_mask[ss % 2]);
> > > > > + sseu->eu_total += eu_cnt;
> > > > > + sseu->eu_per_subslice = max_t(unsigned int,
> > > > > + sseu->eu_per_subslice,
> > > > > + eu_cnt);
> > > > > + }
> > > > > + }
> > > > > +}
> > > > > +
> > > > > static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > > > > struct sseu_dev_info *sseu)
> > > > > {
> > > > > @@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > > > > sseu->slice_mask |= BIT(s);
> > > > > - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> > > > > + if (IS_GEN9_BC(dev_priv))
> > > > > sseu->subslice_mask =
> > > > > INTEL_INFO(dev_priv)->sseu.subslice_mask;
> > > > > @@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
> > > > > cherryview_sseu_device_status(dev_priv, &sseu);
> > > > > } else if (IS_BROADWELL(dev_priv)) {
> > > > > broadwell_sseu_device_status(dev_priv, &sseu);
> > > > > - } else if (INTEL_GEN(dev_priv) >= 9) {
> > > > > + } else if (IS_GEN9(dev_priv)) {
> > > > > gen9_sseu_device_status(dev_priv, &sseu);
> > > > > + } else if (INTEL_GEN(dev_priv) >= 10) {
> > > > > + gen10_sseu_device_status(dev_priv, &sseu);
> > > > > }
> > > > > intel_runtime_pm_put(dev_priv);
> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > > index 1c257797c583..9729145e6c03 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > @@ -8020,11 +8020,17 @@ enum {
> > > > > #define CHV_EU311_PG_ENABLE (1<<1)
> > > > > #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
> > > > > +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> > > > > + ((slice) % 3) * 0x4)
> > > > > #define GEN9_PGCTL_SLICE_ACK (1 << 0)
> > > > > #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
> > > > > #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
> > > > > +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
> > > > > + ((slice) % 3) * 0x8)
> > > > > #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
> > > > > +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
> > > > > + ((slice) % 3) * 0x8)
> > > > > #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
> > > > > #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
> > > > > #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
> > > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs
2017-09-20 18:35 [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs Rodrigo Vivi
2017-09-20 18:35 ` [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status Rodrigo Vivi
@ 2017-09-20 19:08 ` Patchwork
2017-09-20 21:44 ` ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2017-09-20 19:08 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs
URL : https://patchwork.freedesktop.org/series/30669/
State : success
== Summary ==
Series 30669v1 series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs
https://patchwork.freedesktop.org/api/1.0/series/30669/revisions/1/mbox/
Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600
Test gem_sync:
Subgroup basic-each:
dmesg-warn -> PASS (fi-kbl-7500u)
Test kms_addfb_basic:
Subgroup bad-pitch-256:
dmesg-warn -> PASS (fi-kbl-7500u)
Subgroup invalid-get-prop-any:
dmesg-warn -> PASS (fi-kbl-7500u)
Subgroup unused-offsets:
dmesg-warn -> PASS (fi-kbl-7500u)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail -> PASS (fi-snb-2600) fdo#100215
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS (fi-bdw-5557u) fdo#102473
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS (fi-kbl-7500u) fdo#102850
fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473
fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:436s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:474s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:421s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:512s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:501s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:493s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:488s
fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:539s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:419s
fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:564s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:409s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:432s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:487s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:467s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:471s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:576s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:586s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:543s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:447s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:748s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:491s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:478s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:563s
fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:412s
fi-hsw-4770 failed to connect after reboot
939fdb0533e7b2cb97a192864fc18005072f6739 drm-tip: 2017y-09m-20d-17h-36m-21s UTC integration manifest
9889139163ec drm/i915/cnl: Fix SSEU Device Status.
0ef12da59396 drm/i915/cnl: Add support slice/subslice/eu configs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5771/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread* ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs
2017-09-20 18:35 [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs Rodrigo Vivi
2017-09-20 18:35 ` [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status Rodrigo Vivi
2017-09-20 19:08 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs Patchwork
@ 2017-09-20 21:44 ` Patchwork
2017-09-22 14:47 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs (rev2) Patchwork
2017-09-22 18:53 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2017-09-20 21:44 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs
URL : https://patchwork.freedesktop.org/series/30669/
State : failure
== Summary ==
Test kms_flip:
Subgroup modeset-vs-vblank-race:
pass -> FAIL (shard-hsw)
Test kms_busy:
Subgroup extended-modeset-hang-oldfb-with-reset-render-B:
pass -> SKIP (shard-hsw) fdo#102249
Test kms_universal_plane:
Subgroup universal-plane-pipe-A-sanity:
pass -> SKIP (shard-hsw)
fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249
shard-hsw total:2317 pass:1245 dwarn:2 dfail:0 fail:11 skip:1059 time:9578s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5771/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs (rev2)
2017-09-20 18:35 [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs Rodrigo Vivi
` (2 preceding siblings ...)
2017-09-20 21:44 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2017-09-22 14:47 ` Patchwork
2017-09-22 18:53 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2017-09-22 14:47 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs (rev2)
URL : https://patchwork.freedesktop.org/series/30669/
State : success
== Summary ==
Series 30669v2 series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs
https://patchwork.freedesktop.org/api/1.0/series/30669/revisions/2/mbox/
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail -> PASS (fi-snb-2600) fdo#100215
Test pm_rpm:
Subgroup basic-rte:
pass -> DMESG-WARN (fi-cfl-s) fdo#102294
Test drv_module_reload:
Subgroup basic-no-display:
dmesg-warn -> PASS (fi-glk-1) fdo#102777 +1
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:440s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:468s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:418s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:527s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:276s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:497s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:491s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:497s
fi-cfl-s total:289 pass:222 dwarn:35 dfail:0 fail:0 skip:32 time:537s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:423s
fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:565s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:426s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:404s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:429s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:489s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:461s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:474s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:577s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:590s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:542s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:450s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:745s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:489s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:470s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:563s
fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:419s
e0e308721fd283e1c5777657a5941f178f0d49e6 drm-tip: 2017y-09m-22d-13h-31m-38s UTC integration manifest
ddbc734357a9 drm/i915/cnl: Fix SSEU Device Status.
1e3256153139 drm/i915/cnl: Add support slice/subslice/eu configs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5793/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs (rev2)
2017-09-20 18:35 [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs Rodrigo Vivi
` (3 preceding siblings ...)
2017-09-22 14:47 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs (rev2) Patchwork
@ 2017-09-22 18:53 ` Patchwork
4 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2017-09-22 18:53 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs (rev2)
URL : https://patchwork.freedesktop.org/series/30669/
State : success
== Summary ==
Test perf:
Subgroup blocking:
pass -> FAIL (shard-hsw) fdo#102252 +1
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-indfb-draw-blt:
skip -> PASS (shard-hsw)
Test gem_flink_race:
Subgroup flink_close:
fail -> PASS (shard-hsw) fdo#102655
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
shard-hsw total:2429 pass:1333 dwarn:1 dfail:0 fail:12 skip:1083 time:9808s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5793/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH] drm/i915/cnl: Fix SSEU Device Status.
@ 2017-10-26 0:15 Rodrigo Vivi
2017-10-26 14:31 ` Lionel Landwerlin
2017-10-27 22:05 ` Oscar Mateo
0 siblings, 2 replies; 21+ messages in thread
From: Rodrigo Vivi @ 2017-10-26 0:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the die instead of other slices or anything like that.
Also if subslice is disabled the information of eu ack for that
is garbage, so let's skip checks for eu if subslice is disabled
as we skip the subslice if slice is disabled.
The rest is pretty much like gen9.
v2: Remove IS_CANNONLAKE from gen9 status function.
v3: Consider s_max = 6 and ss_max=4 to run over all possible
slices and subslices possible by spec. Although no real
hardware will have that many slices/subslices.
To match with sseu info init.
v4: Fix offset calculation for slices 4 and 5.
Removed Oscar's rv-b since this change also needs review.
v5: Let's consider only valid bits for SLICE*_PGCTL_ACK.
This looks like wrong in Spec, but seems to be enough
for now. Whenever Spec gets updated and fixed we come
back and properly update the masks. Also add a FIXME,
so we can revisit this later when we find some strange
info on debugfs or when we noitce spec got updated.
Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 61 +++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 7 +++++
2 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c65e381b85f3..61c466ff87e0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4448,6 +4448,61 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
}
}
+static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
+ struct sseu_dev_info *sseu)
+{
+ const struct intel_device_info *info = INTEL_INFO(dev_priv);
+ int s_max = 6, ss_max = 4;
+ int s, ss;
+ u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+
+ for (s = 0; s < s_max; s++) {
+ /*
+ * FIXME: Valid SS Mask respects the spec and read
+ * only valid bits for those registers, excluding reserverd
+ * although this seems wrong becuase it would leave many
+ * subslices without ACK.
+ */
+ s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
+ GEN10_PGCTL_VALID_SS_MASK(s);
+ eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
+ eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
+ }
+
+ eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+ GEN9_PGCTL_SSA_EU19_ACK |
+ GEN9_PGCTL_SSA_EU210_ACK |
+ GEN9_PGCTL_SSA_EU311_ACK;
+ eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+ GEN9_PGCTL_SSB_EU19_ACK |
+ GEN9_PGCTL_SSB_EU210_ACK |
+ GEN9_PGCTL_SSB_EU311_ACK;
+
+ for (s = 0; s < s_max; s++) {
+ if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+ /* skip disabled slice */
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+ sseu->subslice_mask = info->sseu.subslice_mask;
+
+ for (ss = 0; ss < ss_max; ss++) {
+ unsigned int eu_cnt;
+
+ if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
+ /* skip disabled subslice */
+ continue;
+
+ eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
+ eu_mask[ss % 2]);
+ sseu->eu_total += eu_cnt;
+ sseu->eu_per_subslice = max_t(unsigned int,
+ sseu->eu_per_subslice,
+ eu_cnt);
+ }
+ }
+}
+
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
@@ -4483,7 +4538,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
- if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
+ if (IS_GEN9_BC(dev_priv))
sseu->subslice_mask =
INTEL_INFO(dev_priv)->sseu.subslice_mask;
@@ -4589,8 +4644,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
cherryview_sseu_device_status(dev_priv, &sseu);
} else if (IS_BROADWELL(dev_priv)) {
broadwell_sseu_device_status(dev_priv, &sseu);
- } else if (INTEL_GEN(dev_priv) >= 9) {
+ } else if (IS_GEN9(dev_priv)) {
gen9_sseu_device_status(dev_priv, &sseu);
+ } else if (INTEL_GEN(dev_priv) >= 10) {
+ gen10_sseu_device_status(dev_priv, &sseu);
}
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f138eae82bf0..8c775e96b4e4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8037,11 +8037,18 @@ enum {
#define CHV_EU311_PG_ENABLE (1<<1)
#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
+#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
+ ((slice) % 3) * 0x4)
#define GEN9_PGCTL_SLICE_ACK (1 << 0)
#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
+#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
+#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
+ ((slice) % 3) * 0x8)
#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
+#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
+ ((slice) % 3) * 0x8)
#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
--
2.13.6
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH] drm/i915/cnl: Fix SSEU Device Status.
2017-10-26 0:15 [PATCH] drm/i915/cnl: Fix SSEU Device Status Rodrigo Vivi
@ 2017-10-26 14:31 ` Lionel Landwerlin
2017-10-26 18:36 ` Rodrigo Vivi
2017-10-27 22:05 ` Oscar Mateo
1 sibling, 1 reply; 21+ messages in thread
From: Lionel Landwerlin @ 2017-10-26 14:31 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx
Since I've been looking at EU_DISABLE* in intel_device_info.c, your
patch caught my eye :)
Reading the documentation I couldn't find anything wrong.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
On 26/10/17 01:15, Rodrigo Vivi wrote:
> CNL adds an extra register for slice/subslice information.
> Although no SKU is planed with an extra slice let's already
> handle this extra piece of information so we don't have the
> risk in future of getting a part that might have chosen this
> part of the die instead of other slices or anything like that.
>
> Also if subslice is disabled the information of eu ack for that
> is garbage, so let's skip checks for eu if subslice is disabled
> as we skip the subslice if slice is disabled.
>
> The rest is pretty much like gen9.
>
> v2: Remove IS_CANNONLAKE from gen9 status function.
>
> v3: Consider s_max = 6 and ss_max=4 to run over all possible
> slices and subslices possible by spec. Although no real
> hardware will have that many slices/subslices.
> To match with sseu info init.
> v4: Fix offset calculation for slices 4 and 5.
> Removed Oscar's rv-b since this change also needs review.
> v5: Let's consider only valid bits for SLICE*_PGCTL_ACK.
> This looks like wrong in Spec, but seems to be enough
> for now. Whenever Spec gets updated and fixed we come
> back and properly update the masks. Also add a FIXME,
> so we can revisit this later when we find some strange
> info on debugfs or when we noitce spec got updated.
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 61 +++++++++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++
> 2 files changed, 66 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index c65e381b85f3..61c466ff87e0 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4448,6 +4448,61 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
> }
> }
>
> +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> + struct sseu_dev_info *sseu)
> +{
> + const struct intel_device_info *info = INTEL_INFO(dev_priv);
> + int s_max = 6, ss_max = 4;
> + int s, ss;
> + u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
> +
> + for (s = 0; s < s_max; s++) {
> + /*
> + * FIXME: Valid SS Mask respects the spec and read
> + * only valid bits for those registers, excluding reserverd
> + * although this seems wrong becuase it would leave many
> + * subslices without ACK.
> + */
> + s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
> + GEN10_PGCTL_VALID_SS_MASK(s);
> + eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> + eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> + }
> +
> + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> + GEN9_PGCTL_SSA_EU19_ACK |
> + GEN9_PGCTL_SSA_EU210_ACK |
> + GEN9_PGCTL_SSA_EU311_ACK;
> + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> + GEN9_PGCTL_SSB_EU19_ACK |
> + GEN9_PGCTL_SSB_EU210_ACK |
> + GEN9_PGCTL_SSB_EU311_ACK;
> +
> + for (s = 0; s < s_max; s++) {
> + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> + /* skip disabled slice */
> + continue;
> +
> + sseu->slice_mask |= BIT(s);
> + sseu->subslice_mask = info->sseu.subslice_mask;
> +
> + for (ss = 0; ss < ss_max; ss++) {
> + unsigned int eu_cnt;
> +
> + if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> + /* skip disabled subslice */
> + continue;
> +
> + eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> + eu_mask[ss % 2]);
> + sseu->eu_total += eu_cnt;
> + sseu->eu_per_subslice = max_t(unsigned int,
> + sseu->eu_per_subslice,
> + eu_cnt);
> + }
> + }
> +}
> +
> static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> struct sseu_dev_info *sseu)
> {
> @@ -4483,7 +4538,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>
> sseu->slice_mask |= BIT(s);
>
> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> + if (IS_GEN9_BC(dev_priv))
> sseu->subslice_mask =
> INTEL_INFO(dev_priv)->sseu.subslice_mask;
>
> @@ -4589,8 +4644,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
> cherryview_sseu_device_status(dev_priv, &sseu);
> } else if (IS_BROADWELL(dev_priv)) {
> broadwell_sseu_device_status(dev_priv, &sseu);
> - } else if (INTEL_GEN(dev_priv) >= 9) {
> + } else if (IS_GEN9(dev_priv)) {
> gen9_sseu_device_status(dev_priv, &sseu);
> + } else if (INTEL_GEN(dev_priv) >= 10) {
> + gen10_sseu_device_status(dev_priv, &sseu);
> }
>
> intel_runtime_pm_put(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f138eae82bf0..8c775e96b4e4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8037,11 +8037,18 @@ enum {
> #define CHV_EU311_PG_ENABLE (1<<1)
>
> #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
> +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> + ((slice) % 3) * 0x4)
> #define GEN9_PGCTL_SLICE_ACK (1 << 0)
> #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
> +#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
>
> #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
> +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
> + ((slice) % 3) * 0x8)
> #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
> +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
> + ((slice) % 3) * 0x8)
> #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
> #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
> #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
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^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH] drm/i915/cnl: Fix SSEU Device Status.
2017-10-26 14:31 ` Lionel Landwerlin
@ 2017-10-26 18:36 ` Rodrigo Vivi
2017-10-27 14:47 ` Lionel Landwerlin
0 siblings, 1 reply; 21+ messages in thread
From: Rodrigo Vivi @ 2017-10-26 18:36 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
On Thu, Oct 26, 2017 at 02:31:16PM +0000, Lionel Landwerlin wrote:
> Since I've been looking at EU_DISABLE* in intel_device_info.c, your patch
> caught my eye :)
> Reading the documentation I couldn't find anything wrong.
>
> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Thanks. Merged to dinq.
>
> On 26/10/17 01:15, Rodrigo Vivi wrote:
> > CNL adds an extra register for slice/subslice information.
> > Although no SKU is planed with an extra slice let's already
> > handle this extra piece of information so we don't have the
> > risk in future of getting a part that might have chosen this
> > part of the die instead of other slices or anything like that.
> >
> > Also if subslice is disabled the information of eu ack for that
> > is garbage, so let's skip checks for eu if subslice is disabled
> > as we skip the subslice if slice is disabled.
> >
> > The rest is pretty much like gen9.
> >
> > v2: Remove IS_CANNONLAKE from gen9 status function.
> >
> > v3: Consider s_max = 6 and ss_max=4 to run over all possible
> > slices and subslices possible by spec. Although no real
> > hardware will have that many slices/subslices.
> > To match with sseu info init.
> > v4: Fix offset calculation for slices 4 and 5.
> > Removed Oscar's rv-b since this change also needs review.
> > v5: Let's consider only valid bits for SLICE*_PGCTL_ACK.
> > This looks like wrong in Spec, but seems to be enough
> > for now. Whenever Spec gets updated and fixed we come
> > back and properly update the masks. Also add a FIXME,
> > so we can revisit this later when we find some strange
> > info on debugfs or when we noitce spec got updated.
> >
> > Cc: Oscar Mateo <oscar.mateo@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 61 +++++++++++++++++++++++++++++++++++--
> > drivers/gpu/drm/i915/i915_reg.h | 7 +++++
> > 2 files changed, 66 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index c65e381b85f3..61c466ff87e0 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -4448,6 +4448,61 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
> > }
> > }
> > +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> > + struct sseu_dev_info *sseu)
> > +{
> > + const struct intel_device_info *info = INTEL_INFO(dev_priv);
> > + int s_max = 6, ss_max = 4;
> > + int s, ss;
> > + u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
> > +
> > + for (s = 0; s < s_max; s++) {
> > + /*
> > + * FIXME: Valid SS Mask respects the spec and read
> > + * only valid bits for those registers, excluding reserverd
> > + * although this seems wrong becuase it would leave many
> > + * subslices without ACK.
> > + */
> > + s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
> > + GEN10_PGCTL_VALID_SS_MASK(s);
> > + eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> > + eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> > + }
> > +
> > + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> > + GEN9_PGCTL_SSA_EU19_ACK |
> > + GEN9_PGCTL_SSA_EU210_ACK |
> > + GEN9_PGCTL_SSA_EU311_ACK;
> > + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> > + GEN9_PGCTL_SSB_EU19_ACK |
> > + GEN9_PGCTL_SSB_EU210_ACK |
> > + GEN9_PGCTL_SSB_EU311_ACK;
> > +
> > + for (s = 0; s < s_max; s++) {
> > + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> > + /* skip disabled slice */
> > + continue;
> > +
> > + sseu->slice_mask |= BIT(s);
> > + sseu->subslice_mask = info->sseu.subslice_mask;
> > +
> > + for (ss = 0; ss < ss_max; ss++) {
> > + unsigned int eu_cnt;
> > +
> > + if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> > + /* skip disabled subslice */
> > + continue;
> > +
> > + eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> > + eu_mask[ss % 2]);
> > + sseu->eu_total += eu_cnt;
> > + sseu->eu_per_subslice = max_t(unsigned int,
> > + sseu->eu_per_subslice,
> > + eu_cnt);
> > + }
> > + }
> > +}
> > +
> > static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > struct sseu_dev_info *sseu)
> > {
> > @@ -4483,7 +4538,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > sseu->slice_mask |= BIT(s);
> > - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> > + if (IS_GEN9_BC(dev_priv))
> > sseu->subslice_mask =
> > INTEL_INFO(dev_priv)->sseu.subslice_mask;
> > @@ -4589,8 +4644,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
> > cherryview_sseu_device_status(dev_priv, &sseu);
> > } else if (IS_BROADWELL(dev_priv)) {
> > broadwell_sseu_device_status(dev_priv, &sseu);
> > - } else if (INTEL_GEN(dev_priv) >= 9) {
> > + } else if (IS_GEN9(dev_priv)) {
> > gen9_sseu_device_status(dev_priv, &sseu);
> > + } else if (INTEL_GEN(dev_priv) >= 10) {
> > + gen10_sseu_device_status(dev_priv, &sseu);
> > }
> > intel_runtime_pm_put(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f138eae82bf0..8c775e96b4e4 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8037,11 +8037,18 @@ enum {
> > #define CHV_EU311_PG_ENABLE (1<<1)
> > #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
> > +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> > + ((slice) % 3) * 0x4)
> > #define GEN9_PGCTL_SLICE_ACK (1 << 0)
> > #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
> > +#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
> > #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
> > +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
> > + ((slice) % 3) * 0x8)
> > #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
> > +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
> > + ((slice) % 3) * 0x8)
> > #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
> > #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
> > #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
>
>
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^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH] drm/i915/cnl: Fix SSEU Device Status.
2017-10-26 18:36 ` Rodrigo Vivi
@ 2017-10-27 14:47 ` Lionel Landwerlin
2017-10-27 17:10 ` Rodrigo Vivi
0 siblings, 1 reply; 21+ messages in thread
From: Lionel Landwerlin @ 2017-10-27 14:47 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
I don't know whether anyone noticed that sseu_status appears to be
broken on BXT :
cat /sys/kernel/debug/dri/0/i915_sseu_status
SSEU Device Info
Available Slice Mask: 0001
Available Slice Total: 1
Available Subslice Total: 2
Available Slice0 Subslice Mask: 0006
Available EU Total: 12
Available EU Per Subslice: 6
Has Pooled EU: no
Has Slice Power Gating: no
Has Subslice Power Gating: yes
Has EU Power Gating: yes
SSEU Device Status
Enabled Slice Mask: 0000
Enabled Slice Total: 0
Enabled Subslice Total: 0
Enabled EU Total: 0
Enabled EU Per Subslice: 0
GEN9_SLICE_PGCTL_ACK(0 -> 3) appears to be all set to 0
On 26/10/17 19:36, Rodrigo Vivi wrote:
> On Thu, Oct 26, 2017 at 02:31:16PM +0000, Lionel Landwerlin wrote:
>> Since I've been looking at EU_DISABLE* in intel_device_info.c, your patch
>> caught my eye :)
>> Reading the documentation I couldn't find anything wrong.
>>
>> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Thanks. Merged to dinq.
>
>> On 26/10/17 01:15, Rodrigo Vivi wrote:
>>> CNL adds an extra register for slice/subslice information.
>>> Although no SKU is planed with an extra slice let's already
>>> handle this extra piece of information so we don't have the
>>> risk in future of getting a part that might have chosen this
>>> part of the die instead of other slices or anything like that.
>>>
>>> Also if subslice is disabled the information of eu ack for that
>>> is garbage, so let's skip checks for eu if subslice is disabled
>>> as we skip the subslice if slice is disabled.
>>>
>>> The rest is pretty much like gen9.
>>>
>>> v2: Remove IS_CANNONLAKE from gen9 status function.
>>>
>>> v3: Consider s_max = 6 and ss_max=4 to run over all possible
>>> slices and subslices possible by spec. Although no real
>>> hardware will have that many slices/subslices.
>>> To match with sseu info init.
>>> v4: Fix offset calculation for slices 4 and 5.
>>> Removed Oscar's rv-b since this change also needs review.
>>> v5: Let's consider only valid bits for SLICE*_PGCTL_ACK.
>>> This looks like wrong in Spec, but seems to be enough
>>> for now. Whenever Spec gets updated and fixed we come
>>> back and properly update the masks. Also add a FIXME,
>>> so we can revisit this later when we find some strange
>>> info on debugfs or when we noitce spec got updated.
>>>
>>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_debugfs.c | 61 +++++++++++++++++++++++++++++++++++--
>>> drivers/gpu/drm/i915/i915_reg.h | 7 +++++
>>> 2 files changed, 66 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>>> index c65e381b85f3..61c466ff87e0 100644
>>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>>> @@ -4448,6 +4448,61 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
>>> }
>>> }
>>> +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
>>> + struct sseu_dev_info *sseu)
>>> +{
>>> + const struct intel_device_info *info = INTEL_INFO(dev_priv);
>>> + int s_max = 6, ss_max = 4;
>>> + int s, ss;
>>> + u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
>>> +
>>> + for (s = 0; s < s_max; s++) {
>>> + /*
>>> + * FIXME: Valid SS Mask respects the spec and read
>>> + * only valid bits for those registers, excluding reserverd
>>> + * although this seems wrong becuase it would leave many
>>> + * subslices without ACK.
>>> + */
>>> + s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
>>> + GEN10_PGCTL_VALID_SS_MASK(s);
>>> + eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
>>> + eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
>>> + }
>>> +
>>> + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
>>> + GEN9_PGCTL_SSA_EU19_ACK |
>>> + GEN9_PGCTL_SSA_EU210_ACK |
>>> + GEN9_PGCTL_SSA_EU311_ACK;
>>> + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
>>> + GEN9_PGCTL_SSB_EU19_ACK |
>>> + GEN9_PGCTL_SSB_EU210_ACK |
>>> + GEN9_PGCTL_SSB_EU311_ACK;
>>> +
>>> + for (s = 0; s < s_max; s++) {
>>> + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
>>> + /* skip disabled slice */
>>> + continue;
>>> +
>>> + sseu->slice_mask |= BIT(s);
>>> + sseu->subslice_mask = info->sseu.subslice_mask;
>>> +
>>> + for (ss = 0; ss < ss_max; ss++) {
>>> + unsigned int eu_cnt;
>>> +
>>> + if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
>>> + /* skip disabled subslice */
>>> + continue;
>>> +
>>> + eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
>>> + eu_mask[ss % 2]);
>>> + sseu->eu_total += eu_cnt;
>>> + sseu->eu_per_subslice = max_t(unsigned int,
>>> + sseu->eu_per_subslice,
>>> + eu_cnt);
>>> + }
>>> + }
>>> +}
>>> +
>>> static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>>> struct sseu_dev_info *sseu)
>>> {
>>> @@ -4483,7 +4538,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>>> sseu->slice_mask |= BIT(s);
>>> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
>>> + if (IS_GEN9_BC(dev_priv))
>>> sseu->subslice_mask =
>>> INTEL_INFO(dev_priv)->sseu.subslice_mask;
>>> @@ -4589,8 +4644,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>>> cherryview_sseu_device_status(dev_priv, &sseu);
>>> } else if (IS_BROADWELL(dev_priv)) {
>>> broadwell_sseu_device_status(dev_priv, &sseu);
>>> - } else if (INTEL_GEN(dev_priv) >= 9) {
>>> + } else if (IS_GEN9(dev_priv)) {
>>> gen9_sseu_device_status(dev_priv, &sseu);
>>> + } else if (INTEL_GEN(dev_priv) >= 10) {
>>> + gen10_sseu_device_status(dev_priv, &sseu);
>>> }
>>> intel_runtime_pm_put(dev_priv);
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index f138eae82bf0..8c775e96b4e4 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -8037,11 +8037,18 @@ enum {
>>> #define CHV_EU311_PG_ENABLE (1<<1)
>>> #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
>>> +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
>>> + ((slice) % 3) * 0x4)
>>> #define GEN9_PGCTL_SLICE_ACK (1 << 0)
>>> #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
>>> +#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
>>> #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
>>> +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
>>> + ((slice) % 3) * 0x8)
>>> #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
>>> +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
>>> + ((slice) % 3) * 0x8)
>>> #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
>>> #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
>>> #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
>>
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^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH] drm/i915/cnl: Fix SSEU Device Status.
2017-10-27 14:47 ` Lionel Landwerlin
@ 2017-10-27 17:10 ` Rodrigo Vivi
2017-10-27 18:22 ` Lionel Landwerlin
0 siblings, 1 reply; 21+ messages in thread
From: Rodrigo Vivi @ 2017-10-27 17:10 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
On Fri, Oct 27, 2017 at 02:47:24PM +0000, Lionel Landwerlin wrote:
> I don't know whether anyone noticed that sseu_status appears to be broken on
> BXT :
>
> cat /sys/kernel/debug/dri/0/i915_sseu_status
> SSEU Device Info
> Available Slice Mask: 0001
> Available Slice Total: 1
> Available Subslice Total: 2
> Available Slice0 Subslice Mask: 0006
> Available EU Total: 12
> Available EU Per Subslice: 6
> Has Pooled EU: no
> Has Slice Power Gating: no
> Has Subslice Power Gating: yes
> Has EU Power Gating: yes
> SSEU Device Status
> Enabled Slice Mask: 0000
> Enabled Slice Total: 0
> Enabled Subslice Total: 0
> Enabled EU Total: 0
> Enabled EU Per Subslice: 0
>
> GEN9_SLICE_PGCTL_ACK(0 -> 3) appears to be all set to 0
I have not looked to BXT, but I also see all 0 like this on CNL
when RC6 enters apparently the status is live.
So, could you please trigger some workload and see if
you see some difference?
Did you see something different on spec for BXT compared to SKL?
Thanks,
Rodrigo.
>
> On 26/10/17 19:36, Rodrigo Vivi wrote:
> > On Thu, Oct 26, 2017 at 02:31:16PM +0000, Lionel Landwerlin wrote:
> > > Since I've been looking at EU_DISABLE* in intel_device_info.c, your patch
> > > caught my eye :)
> > > Reading the documentation I couldn't find anything wrong.
> > >
> > > Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> > Thanks. Merged to dinq.
> >
> > > On 26/10/17 01:15, Rodrigo Vivi wrote:
> > > > CNL adds an extra register for slice/subslice information.
> > > > Although no SKU is planed with an extra slice let's already
> > > > handle this extra piece of information so we don't have the
> > > > risk in future of getting a part that might have chosen this
> > > > part of the die instead of other slices or anything like that.
> > > >
> > > > Also if subslice is disabled the information of eu ack for that
> > > > is garbage, so let's skip checks for eu if subslice is disabled
> > > > as we skip the subslice if slice is disabled.
> > > >
> > > > The rest is pretty much like gen9.
> > > >
> > > > v2: Remove IS_CANNONLAKE from gen9 status function.
> > > >
> > > > v3: Consider s_max = 6 and ss_max=4 to run over all possible
> > > > slices and subslices possible by spec. Although no real
> > > > hardware will have that many slices/subslices.
> > > > To match with sseu info init.
> > > > v4: Fix offset calculation for slices 4 and 5.
> > > > Removed Oscar's rv-b since this change also needs review.
> > > > v5: Let's consider only valid bits for SLICE*_PGCTL_ACK.
> > > > This looks like wrong in Spec, but seems to be enough
> > > > for now. Whenever Spec gets updated and fixed we come
> > > > back and properly update the masks. Also add a FIXME,
> > > > so we can revisit this later when we find some strange
> > > > info on debugfs or when we noitce spec got updated.
> > > >
> > > > Cc: Oscar Mateo <oscar.mateo@intel.com>
> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/i915_debugfs.c | 61 +++++++++++++++++++++++++++++++++++--
> > > > drivers/gpu/drm/i915/i915_reg.h | 7 +++++
> > > > 2 files changed, 66 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > index c65e381b85f3..61c466ff87e0 100644
> > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > @@ -4448,6 +4448,61 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
> > > > }
> > > > }
> > > > +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> > > > + struct sseu_dev_info *sseu)
> > > > +{
> > > > + const struct intel_device_info *info = INTEL_INFO(dev_priv);
> > > > + int s_max = 6, ss_max = 4;
> > > > + int s, ss;
> > > > + u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
> > > > +
> > > > + for (s = 0; s < s_max; s++) {
> > > > + /*
> > > > + * FIXME: Valid SS Mask respects the spec and read
> > > > + * only valid bits for those registers, excluding reserverd
> > > > + * although this seems wrong becuase it would leave many
> > > > + * subslices without ACK.
> > > > + */
> > > > + s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
> > > > + GEN10_PGCTL_VALID_SS_MASK(s);
> > > > + eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> > > > + eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> > > > + }
> > > > +
> > > > + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> > > > + GEN9_PGCTL_SSA_EU19_ACK |
> > > > + GEN9_PGCTL_SSA_EU210_ACK |
> > > > + GEN9_PGCTL_SSA_EU311_ACK;
> > > > + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> > > > + GEN9_PGCTL_SSB_EU19_ACK |
> > > > + GEN9_PGCTL_SSB_EU210_ACK |
> > > > + GEN9_PGCTL_SSB_EU311_ACK;
> > > > +
> > > > + for (s = 0; s < s_max; s++) {
> > > > + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> > > > + /* skip disabled slice */
> > > > + continue;
> > > > +
> > > > + sseu->slice_mask |= BIT(s);
> > > > + sseu->subslice_mask = info->sseu.subslice_mask;
> > > > +
> > > > + for (ss = 0; ss < ss_max; ss++) {
> > > > + unsigned int eu_cnt;
> > > > +
> > > > + if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> > > > + /* skip disabled subslice */
> > > > + continue;
> > > > +
> > > > + eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> > > > + eu_mask[ss % 2]);
> > > > + sseu->eu_total += eu_cnt;
> > > > + sseu->eu_per_subslice = max_t(unsigned int,
> > > > + sseu->eu_per_subslice,
> > > > + eu_cnt);
> > > > + }
> > > > + }
> > > > +}
> > > > +
> > > > static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > > > struct sseu_dev_info *sseu)
> > > > {
> > > > @@ -4483,7 +4538,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > > > sseu->slice_mask |= BIT(s);
> > > > - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> > > > + if (IS_GEN9_BC(dev_priv))
> > > > sseu->subslice_mask =
> > > > INTEL_INFO(dev_priv)->sseu.subslice_mask;
> > > > @@ -4589,8 +4644,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
> > > > cherryview_sseu_device_status(dev_priv, &sseu);
> > > > } else if (IS_BROADWELL(dev_priv)) {
> > > > broadwell_sseu_device_status(dev_priv, &sseu);
> > > > - } else if (INTEL_GEN(dev_priv) >= 9) {
> > > > + } else if (IS_GEN9(dev_priv)) {
> > > > gen9_sseu_device_status(dev_priv, &sseu);
> > > > + } else if (INTEL_GEN(dev_priv) >= 10) {
> > > > + gen10_sseu_device_status(dev_priv, &sseu);
> > > > }
> > > > intel_runtime_pm_put(dev_priv);
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index f138eae82bf0..8c775e96b4e4 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -8037,11 +8037,18 @@ enum {
> > > > #define CHV_EU311_PG_ENABLE (1<<1)
> > > > #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
> > > > +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> > > > + ((slice) % 3) * 0x4)
> > > > #define GEN9_PGCTL_SLICE_ACK (1 << 0)
> > > > #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
> > > > +#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
> > > > #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
> > > > +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
> > > > + ((slice) % 3) * 0x8)
> > > > #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
> > > > +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
> > > > + ((slice) % 3) * 0x8)
> > > > #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
> > > > #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
> > > > #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
> > >
>
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^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH] drm/i915/cnl: Fix SSEU Device Status.
2017-10-27 17:10 ` Rodrigo Vivi
@ 2017-10-27 18:22 ` Lionel Landwerlin
0 siblings, 0 replies; 21+ messages in thread
From: Lionel Landwerlin @ 2017-10-27 18:22 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On 27/10/17 18:10, Rodrigo Vivi wrote:
> On Fri, Oct 27, 2017 at 02:47:24PM +0000, Lionel Landwerlin wrote:
>> I don't know whether anyone noticed that sseu_status appears to be broken on
>> BXT :
>>
>> cat /sys/kernel/debug/dri/0/i915_sseu_status
>> SSEU Device Info
>> Available Slice Mask: 0001
>> Available Slice Total: 1
>> Available Subslice Total: 2
>> Available Slice0 Subslice Mask: 0006
>> Available EU Total: 12
>> Available EU Per Subslice: 6
>> Has Pooled EU: no
>> Has Slice Power Gating: no
>> Has Subslice Power Gating: yes
>> Has EU Power Gating: yes
>> SSEU Device Status
>> Enabled Slice Mask: 0000
>> Enabled Slice Total: 0
>> Enabled Subslice Total: 0
>> Enabled EU Total: 0
>> Enabled EU Per Subslice: 0
>>
>> GEN9_SLICE_PGCTL_ACK(0 -> 3) appears to be all set to 0
> I have not looked to BXT, but I also see all 0 like this on CNL
> when RC6 enters apparently the status is live.
>
> So, could you please trigger some workload and see if
> you see some difference?
>
> Did you see something different on spec for BXT compared to SKL?
I opened this bug : https://bugs.freedesktop.org/show_bug.cgi?id=103484
Chris has been kind enough to look into it.
>
> Thanks,
> Rodrigo.
>
>> On 26/10/17 19:36, Rodrigo Vivi wrote:
>>> On Thu, Oct 26, 2017 at 02:31:16PM +0000, Lionel Landwerlin wrote:
>>>> Since I've been looking at EU_DISABLE* in intel_device_info.c, your patch
>>>> caught my eye :)
>>>> Reading the documentation I couldn't find anything wrong.
>>>>
>>>> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>> Thanks. Merged to dinq.
>>>
>>>> On 26/10/17 01:15, Rodrigo Vivi wrote:
>>>>> CNL adds an extra register for slice/subslice information.
>>>>> Although no SKU is planed with an extra slice let's already
>>>>> handle this extra piece of information so we don't have the
>>>>> risk in future of getting a part that might have chosen this
>>>>> part of the die instead of other slices or anything like that.
>>>>>
>>>>> Also if subslice is disabled the information of eu ack for that
>>>>> is garbage, so let's skip checks for eu if subslice is disabled
>>>>> as we skip the subslice if slice is disabled.
>>>>>
>>>>> The rest is pretty much like gen9.
>>>>>
>>>>> v2: Remove IS_CANNONLAKE from gen9 status function.
>>>>>
>>>>> v3: Consider s_max = 6 and ss_max=4 to run over all possible
>>>>> slices and subslices possible by spec. Although no real
>>>>> hardware will have that many slices/subslices.
>>>>> To match with sseu info init.
>>>>> v4: Fix offset calculation for slices 4 and 5.
>>>>> Removed Oscar's rv-b since this change also needs review.
>>>>> v5: Let's consider only valid bits for SLICE*_PGCTL_ACK.
>>>>> This looks like wrong in Spec, but seems to be enough
>>>>> for now. Whenever Spec gets updated and fixed we come
>>>>> back and properly update the masks. Also add a FIXME,
>>>>> so we can revisit this later when we find some strange
>>>>> info on debugfs or when we noitce spec got updated.
>>>>>
>>>>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>>>>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/i915_debugfs.c | 61 +++++++++++++++++++++++++++++++++++--
>>>>> drivers/gpu/drm/i915/i915_reg.h | 7 +++++
>>>>> 2 files changed, 66 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>>>>> index c65e381b85f3..61c466ff87e0 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>>>>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>>>>> @@ -4448,6 +4448,61 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
>>>>> }
>>>>> }
>>>>> +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
>>>>> + struct sseu_dev_info *sseu)
>>>>> +{
>>>>> + const struct intel_device_info *info = INTEL_INFO(dev_priv);
>>>>> + int s_max = 6, ss_max = 4;
>>>>> + int s, ss;
>>>>> + u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
>>>>> +
>>>>> + for (s = 0; s < s_max; s++) {
>>>>> + /*
>>>>> + * FIXME: Valid SS Mask respects the spec and read
>>>>> + * only valid bits for those registers, excluding reserverd
>>>>> + * although this seems wrong becuase it would leave many
>>>>> + * subslices without ACK.
>>>>> + */
>>>>> + s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
>>>>> + GEN10_PGCTL_VALID_SS_MASK(s);
>>>>> + eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
>>>>> + eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
>>>>> + }
>>>>> +
>>>>> + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
>>>>> + GEN9_PGCTL_SSA_EU19_ACK |
>>>>> + GEN9_PGCTL_SSA_EU210_ACK |
>>>>> + GEN9_PGCTL_SSA_EU311_ACK;
>>>>> + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
>>>>> + GEN9_PGCTL_SSB_EU19_ACK |
>>>>> + GEN9_PGCTL_SSB_EU210_ACK |
>>>>> + GEN9_PGCTL_SSB_EU311_ACK;
>>>>> +
>>>>> + for (s = 0; s < s_max; s++) {
>>>>> + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
>>>>> + /* skip disabled slice */
>>>>> + continue;
>>>>> +
>>>>> + sseu->slice_mask |= BIT(s);
>>>>> + sseu->subslice_mask = info->sseu.subslice_mask;
>>>>> +
>>>>> + for (ss = 0; ss < ss_max; ss++) {
>>>>> + unsigned int eu_cnt;
>>>>> +
>>>>> + if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
>>>>> + /* skip disabled subslice */
>>>>> + continue;
>>>>> +
>>>>> + eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
>>>>> + eu_mask[ss % 2]);
>>>>> + sseu->eu_total += eu_cnt;
>>>>> + sseu->eu_per_subslice = max_t(unsigned int,
>>>>> + sseu->eu_per_subslice,
>>>>> + eu_cnt);
>>>>> + }
>>>>> + }
>>>>> +}
>>>>> +
>>>>> static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>>>>> struct sseu_dev_info *sseu)
>>>>> {
>>>>> @@ -4483,7 +4538,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>>>>> sseu->slice_mask |= BIT(s);
>>>>> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
>>>>> + if (IS_GEN9_BC(dev_priv))
>>>>> sseu->subslice_mask =
>>>>> INTEL_INFO(dev_priv)->sseu.subslice_mask;
>>>>> @@ -4589,8 +4644,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>>>>> cherryview_sseu_device_status(dev_priv, &sseu);
>>>>> } else if (IS_BROADWELL(dev_priv)) {
>>>>> broadwell_sseu_device_status(dev_priv, &sseu);
>>>>> - } else if (INTEL_GEN(dev_priv) >= 9) {
>>>>> + } else if (IS_GEN9(dev_priv)) {
>>>>> gen9_sseu_device_status(dev_priv, &sseu);
>>>>> + } else if (INTEL_GEN(dev_priv) >= 10) {
>>>>> + gen10_sseu_device_status(dev_priv, &sseu);
>>>>> }
>>>>> intel_runtime_pm_put(dev_priv);
>>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>>> index f138eae82bf0..8c775e96b4e4 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>>> @@ -8037,11 +8037,18 @@ enum {
>>>>> #define CHV_EU311_PG_ENABLE (1<<1)
>>>>> #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
>>>>> +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
>>>>> + ((slice) % 3) * 0x4)
>>>>> #define GEN9_PGCTL_SLICE_ACK (1 << 0)
>>>>> #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
>>>>> +#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
>>>>> #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
>>>>> +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
>>>>> + ((slice) % 3) * 0x8)
>>>>> #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
>>>>> +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
>>>>> + ((slice) % 3) * 0x8)
>>>>> #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
>>>>> #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
>>>>> #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH] drm/i915/cnl: Fix SSEU Device Status.
2017-10-26 0:15 [PATCH] drm/i915/cnl: Fix SSEU Device Status Rodrigo Vivi
2017-10-26 14:31 ` Lionel Landwerlin
@ 2017-10-27 22:05 ` Oscar Mateo
2017-10-30 13:11 ` David Weinehall
1 sibling, 1 reply; 21+ messages in thread
From: Oscar Mateo @ 2017-10-27 22:05 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5974 bytes --]
On 10/25/2017 05:15 PM, Rodrigo Vivi wrote:
> CNL adds an extra register for slice/subslice information.
> Although no SKU is planed with an extra slice let's already
> handle this extra piece of information so we don't have the
> risk in future of getting a part that might have chosen this
> part of the die instead of other slices or anything like that.
>
> Also if subslice is disabled the information of eu ack for that
> is garbage, so let's skip checks for eu if subslice is disabled
> as we skip the subslice if slice is disabled.
>
> The rest is pretty much like gen9.
>
> v2: Remove IS_CANNONLAKE from gen9 status function.
>
> v3: Consider s_max = 6 and ss_max=4 to run over all possible
> slices and subslices possible by spec. Although no real
> hardware will have that many slices/subslices.
> To match with sseu info init.
> v4: Fix offset calculation for slices 4 and 5.
> Removed Oscar's rv-b since this change also needs review.
> v5: Let's consider only valid bits for SLICE*_PGCTL_ACK.
> This looks like wrong in Spec, but seems to be enough
> for now. Whenever Spec gets updated and fixed we come
> back and properly update the masks. Also add a FIXME,
> so we can revisit this later when we find some strange
> info on debugfs or when we noitce spec got updated.
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 61 +++++++++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++
> 2 files changed, 66 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index c65e381b85f3..61c466ff87e0 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4448,6 +4448,61 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
> }
> }
>
> +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> + struct sseu_dev_info *sseu)
> +{
> + const struct intel_device_info *info = INTEL_INFO(dev_priv);
> + int s_max = 6, ss_max = 4;
> + int s, ss;
> + u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
> +
> + for (s = 0; s < s_max; s++) {
> + /*
> + * FIXME: Valid SS Mask respects the spec and read
> + * only valid bits for those registers, excluding reserverd
> + * although this seems wrong becuase it would leave many
s/becuase/because
Seems like a look compromise (a corrected BSpec would be better, but
¯\_(ツ)_/¯)
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
> + * subslices without ACK.
> + */
> + s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
> + GEN10_PGCTL_VALID_SS_MASK(s);
> + eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> + eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> + }
> +
> + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> + GEN9_PGCTL_SSA_EU19_ACK |
> + GEN9_PGCTL_SSA_EU210_ACK |
> + GEN9_PGCTL_SSA_EU311_ACK;
> + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> + GEN9_PGCTL_SSB_EU19_ACK |
> + GEN9_PGCTL_SSB_EU210_ACK |
> + GEN9_PGCTL_SSB_EU311_ACK;
> +
> + for (s = 0; s < s_max; s++) {
> + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> + /* skip disabled slice */
> + continue;
> +
> + sseu->slice_mask |= BIT(s);
> + sseu->subslice_mask = info->sseu.subslice_mask;
> +
> + for (ss = 0; ss < ss_max; ss++) {
> + unsigned int eu_cnt;
> +
> + if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> + /* skip disabled subslice */
> + continue;
> +
> + eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> + eu_mask[ss % 2]);
> + sseu->eu_total += eu_cnt;
> + sseu->eu_per_subslice = max_t(unsigned int,
> + sseu->eu_per_subslice,
> + eu_cnt);
> + }
> + }
> +}
> +
> static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> struct sseu_dev_info *sseu)
> {
> @@ -4483,7 +4538,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>
> sseu->slice_mask |= BIT(s);
>
> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> + if (IS_GEN9_BC(dev_priv))
> sseu->subslice_mask =
> INTEL_INFO(dev_priv)->sseu.subslice_mask;
>
> @@ -4589,8 +4644,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
> cherryview_sseu_device_status(dev_priv, &sseu);
> } else if (IS_BROADWELL(dev_priv)) {
> broadwell_sseu_device_status(dev_priv, &sseu);
> - } else if (INTEL_GEN(dev_priv) >= 9) {
> + } else if (IS_GEN9(dev_priv)) {
> gen9_sseu_device_status(dev_priv, &sseu);
> + } else if (INTEL_GEN(dev_priv) >= 10) {
> + gen10_sseu_device_status(dev_priv, &sseu);
> }
>
> intel_runtime_pm_put(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f138eae82bf0..8c775e96b4e4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8037,11 +8037,18 @@ enum {
> #define CHV_EU311_PG_ENABLE (1<<1)
>
> #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
> +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> + ((slice) % 3) * 0x4)
> #define GEN9_PGCTL_SLICE_ACK (1 << 0)
> #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
> +#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
>
> #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
> +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
> + ((slice) % 3) * 0x8)
> #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
> +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
> + ((slice) % 3) * 0x8)
> #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
> #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
> #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
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^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH] drm/i915/cnl: Fix SSEU Device Status.
2017-10-27 22:05 ` Oscar Mateo
@ 2017-10-30 13:11 ` David Weinehall
0 siblings, 0 replies; 21+ messages in thread
From: David Weinehall @ 2017-10-30 13:11 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx, Rodrigo Vivi
On Fri, Oct 27, 2017 at 03:05:58PM -0700, Oscar Mateo wrote:
>
>
> On 10/25/2017 05:15 PM, Rodrigo Vivi wrote:
> > CNL adds an extra register for slice/subslice information.
> > Although no SKU is planed with an extra slice let's already
> > handle this extra piece of information so we don't have the
> > risk in future of getting a part that might have chosen this
> > part of the die instead of other slices or anything like that.
> >
> > Also if subslice is disabled the information of eu ack for that
> > is garbage, so let's skip checks for eu if subslice is disabled
> > as we skip the subslice if slice is disabled.
> >
> > The rest is pretty much like gen9.
> >
> > v2: Remove IS_CANNONLAKE from gen9 status function.
> >
> > v3: Consider s_max = 6 and ss_max=4 to run over all possible
> > slices and subslices possible by spec. Although no real
> > hardware will have that many slices/subslices.
> > To match with sseu info init.
> > v4: Fix offset calculation for slices 4 and 5.
> > Removed Oscar's rv-b since this change also needs review.
> > v5: Let's consider only valid bits for SLICE*_PGCTL_ACK.
> > This looks like wrong in Spec, but seems to be enough
> > for now. Whenever Spec gets updated and fixed we come
> > back and properly update the masks. Also add a FIXME,
> > so we can revisit this later when we find some strange
> > info on debugfs or when we noitce spec got updated.
> >
> > Cc: Oscar Mateo <oscar.mateo@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 61 +++++++++++++++++++++++++++++++++++--
> > drivers/gpu/drm/i915/i915_reg.h | 7 +++++
> > 2 files changed, 66 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index c65e381b85f3..61c466ff87e0 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -4448,6 +4448,61 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
> > }
> > }
> > +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> > + struct sseu_dev_info *sseu)
> > +{
> > + const struct intel_device_info *info = INTEL_INFO(dev_priv);
> > + int s_max = 6, ss_max = 4;
> > + int s, ss;
> > + u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
> > +
> > + for (s = 0; s < s_max; s++) {
> > + /*
> > + * FIXME: Valid SS Mask respects the spec and read
> > + * only valid bits for those registers, excluding reserverd
> > + * although this seems wrong becuase it would leave many
>
> s/becuase/because
s/reserverd/reserved,/
> Seems like a look compromise (a corrected BSpec would be better, but
> ¯\_(ツ)_/¯)
>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
>
> > + * subslices without ACK.
> > + */
> > + s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
> > + GEN10_PGCTL_VALID_SS_MASK(s);
> > + eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> > + eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> > + }
> > +
> > + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> > + GEN9_PGCTL_SSA_EU19_ACK |
> > + GEN9_PGCTL_SSA_EU210_ACK |
> > + GEN9_PGCTL_SSA_EU311_ACK;
> > + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> > + GEN9_PGCTL_SSB_EU19_ACK |
> > + GEN9_PGCTL_SSB_EU210_ACK |
> > + GEN9_PGCTL_SSB_EU311_ACK;
> > +
> > + for (s = 0; s < s_max; s++) {
> > + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> > + /* skip disabled slice */
> > + continue;
> > +
> > + sseu->slice_mask |= BIT(s);
> > + sseu->subslice_mask = info->sseu.subslice_mask;
> > +
> > + for (ss = 0; ss < ss_max; ss++) {
> > + unsigned int eu_cnt;
> > +
> > + if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> > + /* skip disabled subslice */
> > + continue;
> > +
> > + eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> > + eu_mask[ss % 2]);
> > + sseu->eu_total += eu_cnt;
> > + sseu->eu_per_subslice = max_t(unsigned int,
> > + sseu->eu_per_subslice,
> > + eu_cnt);
> > + }
> > + }
> > +}
> > +
> > static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > struct sseu_dev_info *sseu)
> > {
> > @@ -4483,7 +4538,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > sseu->slice_mask |= BIT(s);
> > - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> > + if (IS_GEN9_BC(dev_priv))
> > sseu->subslice_mask =
> > INTEL_INFO(dev_priv)->sseu.subslice_mask;
> > @@ -4589,8 +4644,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
> > cherryview_sseu_device_status(dev_priv, &sseu);
> > } else if (IS_BROADWELL(dev_priv)) {
> > broadwell_sseu_device_status(dev_priv, &sseu);
> > - } else if (INTEL_GEN(dev_priv) >= 9) {
> > + } else if (IS_GEN9(dev_priv)) {
> > gen9_sseu_device_status(dev_priv, &sseu);
> > + } else if (INTEL_GEN(dev_priv) >= 10) {
> > + gen10_sseu_device_status(dev_priv, &sseu);
> > }
> > intel_runtime_pm_put(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f138eae82bf0..8c775e96b4e4 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8037,11 +8037,18 @@ enum {
> > #define CHV_EU311_PG_ENABLE (1<<1)
> > #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
> > +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> > + ((slice) % 3) * 0x4)
> > #define GEN9_PGCTL_SLICE_ACK (1 << 0)
> > #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
> > +#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
> > #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
> > +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
> > + ((slice) % 3) * 0x8)
> > #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
> > +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
> > + ((slice) % 3) * 0x8)
> > #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
> > #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
> > #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2017-10-30 13:12 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-09-20 18:35 [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs Rodrigo Vivi
2017-09-20 18:35 ` [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status Rodrigo Vivi
2017-09-20 19:49 ` Oscar Mateo
2017-09-22 13:15 ` [PATCH] " Rodrigo Vivi
2017-09-22 16:44 ` Oscar Mateo
2017-09-22 18:32 ` Rodrigo Vivi
2017-09-26 20:06 ` Rodrigo Vivi
2017-09-27 12:16 ` Daniel Vetter
2017-09-27 14:28 ` Rodrigo Vivi
2017-09-20 19:08 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs Patchwork
2017-09-20 21:44 ` ✗ Fi.CI.IGT: failure " Patchwork
2017-09-22 14:47 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs (rev2) Patchwork
2017-09-22 18:53 ` ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2017-10-26 0:15 [PATCH] drm/i915/cnl: Fix SSEU Device Status Rodrigo Vivi
2017-10-26 14:31 ` Lionel Landwerlin
2017-10-26 18:36 ` Rodrigo Vivi
2017-10-27 14:47 ` Lionel Landwerlin
2017-10-27 17:10 ` Rodrigo Vivi
2017-10-27 18:22 ` Lionel Landwerlin
2017-10-27 22:05 ` Oscar Mateo
2017-10-30 13:11 ` David Weinehall
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