[PATCH 1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume

[PATCH 1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume

[Imre Deak]

The DMC firmware program memory is lost after S3/S4 system suspend, so
we need to reprogram it during resume.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103070
Fixes: cebfcead63de ("drm/i915/DMC/CNL: Load DMC on CNL")
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 7933d1bc6a1c..3791c3f5f56d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2809,6 +2809,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
 
 	/* 6. Enable DBUF */
 	gen9_dbuf_enable(dev_priv);
+
+	if (resume && dev_priv->csr.dmc_payload)
+		intel_csr_load_program(dev_priv);
 }
 
 static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
-- 
2.13.2

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[PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation

[Imre Deak]

According to BSpec GLK like BXT needs to ignore the idle state of cores
before starting the DMC firmware's DC state handler.

Fixes: dbb28b5c3d3c ("drm/i915/DMC/GLK: Load DMC on GLK")
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index cdfb624eb82d..ea5d5c9645a4 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -216,7 +216,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 
 	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		mask |= DC_STATE_DEBUG_MASK_CORES;
 
 	/* The below bit doesn't need to be cleared ever afterwards */
-- 
2.13.2

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Re: [PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation

[Rodrigo Vivi]

On Tue, Oct 03, 2017 at 09:51:59AM +0000, Imre Deak wrote:
> According to BSpec GLK like BXT needs to ignore the idle state of cores
> before starting the DMC firmware's DC state handler.

no mention on CNL there?

Btw I just saw that CNL DMC seems much more like BXT than like SKL.
Our code probably needs deeper changes...

> 
> Fixes: dbb28b5c3d3c ("drm/i915/DMC/GLK: Load DMC on GLK")
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_csr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index cdfb624eb82d..ea5d5c9645a4 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -216,7 +216,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
>  
>  	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
>  
> -	if (IS_BROXTON(dev_priv))
> +	if (IS_GEN9_LP(dev_priv))
>  		mask |= DC_STATE_DEBUG_MASK_CORES;

I saw in spec for SKL+: "This field must be set to Mask prior to enabling DC5 or DC6"
So I believe this should be INTEL_GEN(dev_priv) >= 9... :/


>  
>  	/* The below bit doesn't need to be cleared ever afterwards */
> -- 
> 2.13.2
> 
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Re: [PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation

[Imre Deak]

On Tue, Oct 03, 2017 at 10:47:50AM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 03, 2017 at 09:51:59AM +0000, Imre Deak wrote:
> > According to BSpec GLK like BXT needs to ignore the idle state of cores
> > before starting the DMC firmware's DC state handler.
> 
> no mention on CNL there?

No, this is only needed for BXT and GLK.

> Btw I just saw that CNL DMC seems much more like BXT than like SKL.
> Our code probably needs deeper changes...
> 
> > 
> > Fixes: dbb28b5c3d3c ("drm/i915/DMC/GLK: Load DMC on GLK")
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_csr.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> > index cdfb624eb82d..ea5d5c9645a4 100644
> > --- a/drivers/gpu/drm/i915/intel_csr.c
> > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > @@ -216,7 +216,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> >  
> >  	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
> >  
> > -	if (IS_BROXTON(dev_priv))
> > +	if (IS_GEN9_LP(dev_priv))
> >  		mask |= DC_STATE_DEBUG_MASK_CORES;
> 
> I saw in spec for SKL+: "This field must be set to Mask prior to enabling DC5 or DC6"
> So I believe this should be INTEL_GEN(dev_priv) >= 9... :/

No, only needed for BXT, GLK, see under BSpec "Sequences for Display C5 and C6".

> >  
> >  	/* The below bit doesn't need to be cleared ever afterwards */
> > -- 
> > 2.13.2
> > 
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Re: [PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation

[Rodrigo Vivi]

On Tue, Oct 03, 2017 at 06:03:20PM +0000, Imre Deak wrote:
> On Tue, Oct 03, 2017 at 10:47:50AM -0700, Rodrigo Vivi wrote:
> > On Tue, Oct 03, 2017 at 09:51:59AM +0000, Imre Deak wrote:
> > > According to BSpec GLK like BXT needs to ignore the idle state of cores
> > > before starting the DMC firmware's DC state handler.
> > 
> > no mention on CNL there?
> 
> No, this is only needed for BXT and GLK.
> 
> > Btw I just saw that CNL DMC seems much more like BXT than like SKL.
> > Our code probably needs deeper changes...
> > 
> > > 
> > > Fixes: dbb28b5c3d3c ("drm/i915/DMC/GLK: Load DMC on GLK")
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_csr.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> > > index cdfb624eb82d..ea5d5c9645a4 100644
> > > --- a/drivers/gpu/drm/i915/intel_csr.c
> > > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > > @@ -216,7 +216,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> > >  
> > >  	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
> > >  
> > > -	if (IS_BROXTON(dev_priv))
> > > +	if (IS_GEN9_LP(dev_priv))
> > >  		mask |= DC_STATE_DEBUG_MASK_CORES;
> > 
> > I saw in spec for SKL+: "This field must be set to Mask prior to enabling DC5 or DC6"
> > So I believe this should be INTEL_GEN(dev_priv) >= 9... :/
> 
> No, only needed for BXT, GLK, see under BSpec "Sequences for Display C5 and C6".

Oh yes! It seems we can trust this part better. Really clear and complete.


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> 
> > >  
> > >  	/* The below bit doesn't need to be cleared ever afterwards */
> > > -- 
> > > 2.13.2
> > > 
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Re: [PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation

[Rodrigo Vivi]

On Tue, Oct 03, 2017 at 05:47:50PM +0000, Rodrigo Vivi wrote:
> On Tue, Oct 03, 2017 at 09:51:59AM +0000, Imre Deak wrote:
> > According to BSpec GLK like BXT needs to ignore the idle state of cores
> > before starting the DMC firmware's DC state handler.
> 
> no mention on CNL there?
> 
> Btw I just saw that CNL DMC seems much more like BXT than like SKL.
> Our code probably needs deeper changes...

nevermind. I was wrong about this.
The only difference I see on CNL compared with SKL now
is the bit 31 of DC_STATE_EN...

A bit that we should set during modeset and clear after. But there is
no mention about that bit on the main sequences page and also we
leave dc states disabled during modeset anyways besides that
clock gating wa... So I believe we are safe.

Imre, thoughts?

> 
> > 
> > Fixes: dbb28b5c3d3c ("drm/i915/DMC/GLK: Load DMC on GLK")
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_csr.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> > index cdfb624eb82d..ea5d5c9645a4 100644
> > --- a/drivers/gpu/drm/i915/intel_csr.c
> > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > @@ -216,7 +216,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> >  
> >  	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
> >  
> > -	if (IS_BROXTON(dev_priv))
> > +	if (IS_GEN9_LP(dev_priv))
> >  		mask |= DC_STATE_DEBUG_MASK_CORES;
> 
> I saw in spec for SKL+: "This field must be set to Mask prior to enabling DC5 or DC6"
> So I believe this should be INTEL_GEN(dev_priv) >= 9... :/
> 
> 
> >  
> >  	/* The below bit doesn't need to be cleared ever afterwards */
> > -- 
> > 2.13.2
> > 
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Re: [PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation

[Imre Deak]

On Tue, Oct 03, 2017 at 11:20:10AM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 03, 2017 at 05:47:50PM +0000, Rodrigo Vivi wrote:
> > On Tue, Oct 03, 2017 at 09:51:59AM +0000, Imre Deak wrote:
> > > According to BSpec GLK like BXT needs to ignore the idle state of cores
> > > before starting the DMC firmware's DC state handler.
> > 
> > no mention on CNL there?
> > 
> > Btw I just saw that CNL DMC seems much more like BXT than like SKL.
> > Our code probably needs deeper changes...
> 
> nevermind. I was wrong about this.
> The only difference I see on CNL compared with SKL now
> is the bit 31 of DC_STATE_EN...
> 
> A bit that we should set during modeset and clear after. But there is
> no mention about that bit on the main sequences page and also we
> leave dc states disabled during modeset anyways besides that
> clock gating wa... So I believe we are safe.
> 
> Imre, thoughts?

Yes, that bit would gate CSR_START which sounds redundant if we disable
DC states anyway around a mode set.

Art, could this be clarified under "Sequences for Display C5 and C6" or
the definition DC_STATE_EN?

Thanks,
Imre

> > > 
> > > Fixes: dbb28b5c3d3c ("drm/i915/DMC/GLK: Load DMC on GLK")
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_csr.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> > > index cdfb624eb82d..ea5d5c9645a4 100644
> > > --- a/drivers/gpu/drm/i915/intel_csr.c
> > > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > > @@ -216,7 +216,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> > >  
> > >  	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
> > >  
> > > -	if (IS_BROXTON(dev_priv))
> > > +	if (IS_GEN9_LP(dev_priv))
> > >  		mask |= DC_STATE_DEBUG_MASK_CORES;
> > 
> > I saw in spec for SKL+: "This field must be set to Mask prior to enabling DC5 or DC6"
> > So I believe this should be INTEL_GEN(dev_priv) >= 9... :/
> > 
> > 
> > >  
> > >  	/* The below bit doesn't need to be cleared ever afterwards */
> > > -- 
> > > 2.13.2
> > > 
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✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume
URL   : https://patchwork.freedesktop.org/series/31314/
State : failure

== Summary ==

Series 31314v1 series starting with [1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume
https://patchwork.freedesktop.org/api/1.0/series/31314/revisions/1/mbox/

Test chamelium:
        Subgroup dp-crc-fast:
                pass       -> DMESG-FAIL (fi-kbl-7500u) fdo#102514
Test gem_exec_suspend:
        Subgroup basic-s3:
                dmesg-warn -> PASS       (fi-cnl-y) fdo#103070
Test kms_busy:
        Subgroup basic-flip-a:
                pass       -> FAIL       (fi-bwr-2160)
Test kms_flip:
        Subgroup basic-flip-vs-dpms:
                incomplete -> PASS       (fi-cfl-s)
Test kms_force_connector_basic:
        Subgroup force-connector-state:
                skip       -> PASS       (fi-ivb-3520m)
        Subgroup force-edid:
                skip       -> PASS       (fi-ivb-3520m)
        Subgroup force-load-detect:
                skip       -> PASS       (fi-ivb-3520m)
        Subgroup prune-stale-modes:
                skip       -> PASS       (fi-ivb-3520m)

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#103070 https://bugs.freedesktop.org/show_bug.cgi?id=103070

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:453s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:478s
fi-blb-e6850     total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  time:393s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:567s
fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:1   skip:105 time:288s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:525s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:528s
fi-byt-j1900     total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  time:539s
fi-byt-n2820     total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  time:531s
fi-cfl-s         total:289  pass:256  dwarn:1   dfail:0   fail:0   skip:32  time:564s
fi-cnl-y         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:607s
fi-elk-e7500     total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  time:435s
fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:600s
fi-hsw-4770      total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:440s
fi-hsw-4770r     total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:422s
fi-ilk-650       total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:464s
fi-ivb-3520m     total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:509s
fi-ivb-3770      total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:473s
fi-kbl-7500u     total:289  pass:263  dwarn:1   dfail:1   fail:0   skip:24  time:496s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:575s
fi-kbl-7567u     total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  time:487s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:583s
fi-pnv-d510      total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:662s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:470s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:532s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:514s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:477s
fi-snb-2520m     total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  time:584s
fi-snb-2600      total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:431s

2c14f35a0bc1aaff2e36e4535d42919d2cd0b740 drm-tip: 2017y-10m-03d-09h-11m-26s UTC integration manifest
353755c5d9c1 drm/i915/glk: Fix DMC/DC state idleness calculation
f6a884457fc2 drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5877/
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Re: ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume

[Imre Deak]

On Tue, Oct 03, 2017 at 10:18:20AM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume
> URL   : https://patchwork.freedesktop.org/series/31314/
> State : failure
> 
> == Summary ==
> 
> Series 31314v1 series starting with [1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume
> https://patchwork.freedesktop.org/api/1.0/series/31314/revisions/1/mbox/
> 
> Test chamelium:
>         Subgroup dp-crc-fast:
>                 pass       -> DMESG-FAIL (fi-kbl-7500u) fdo#102514
> Test gem_exec_suspend:
>         Subgroup basic-s3:
>                 dmesg-warn -> PASS       (fi-cnl-y) fdo#103070

This is the only relevant change, the rest match the pre-existing fdo
bug, or are unrelated platforms.

Thanks for the review, I pushed both patches to -dinq.

> Test kms_busy:
>         Subgroup basic-flip-a:
>                 pass       -> FAIL       (fi-bwr-2160)
> Test kms_flip:
>         Subgroup basic-flip-vs-dpms:
>                 incomplete -> PASS       (fi-cfl-s)
> Test kms_force_connector_basic:
>         Subgroup force-connector-state:
>                 skip       -> PASS       (fi-ivb-3520m)
>         Subgroup force-edid:
>                 skip       -> PASS       (fi-ivb-3520m)
>         Subgroup force-load-detect:
>                 skip       -> PASS       (fi-ivb-3520m)
>         Subgroup prune-stale-modes:
>                 skip       -> PASS       (fi-ivb-3520m)
> 
> fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
> fdo#103070 https://bugs.freedesktop.org/show_bug.cgi?id=103070
> 
> fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:453s
> fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:478s
> fi-blb-e6850     total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  time:393s
> fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:567s
> fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:1   skip:105 time:288s
> fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:525s
> fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:528s
> fi-byt-j1900     total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  time:539s
> fi-byt-n2820     total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  time:531s
> fi-cfl-s         total:289  pass:256  dwarn:1   dfail:0   fail:0   skip:32  time:564s
> fi-cnl-y         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:607s
> fi-elk-e7500     total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  time:435s
> fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:600s
> fi-hsw-4770      total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:440s
> fi-hsw-4770r     total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:422s
> fi-ilk-650       total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:464s
> fi-ivb-3520m     total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:509s
> fi-ivb-3770      total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:473s
> fi-kbl-7500u     total:289  pass:263  dwarn:1   dfail:1   fail:0   skip:24  time:496s
> fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:575s
> fi-kbl-7567u     total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  time:487s
> fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:583s
> fi-pnv-d510      total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:662s
> fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:470s
> fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:532s
> fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:514s
> fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:477s
> fi-snb-2520m     total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  time:584s
> fi-snb-2600      total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:431s
> 
> 2c14f35a0bc1aaff2e36e4535d42919d2cd0b740 drm-tip: 2017y-10m-03d-09h-11m-26s UTC integration manifest
> 353755c5d9c1 drm/i915/glk: Fix DMC/DC state idleness calculation
> f6a884457fc2 drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5877/
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Re: [PATCH 1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume

[Rodrigo Vivi]

On Tue, Oct 03, 2017 at 09:51:58AM +0000, Imre Deak wrote:
> The DMC firmware program memory is lost after S3/S4 system suspend, so
> we need to reprogram it during resume.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103070
> Fixes: cebfcead63de ("drm/i915/DMC/CNL: Load DMC on CNL")
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 7933d1bc6a1c..3791c3f5f56d 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2809,6 +2809,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
>  
>  	/* 6. Enable DBUF */
>  	gen9_dbuf_enable(dev_priv);
> +
> +	if (resume && dev_priv->csr.dmc_payload)
> +		intel_csr_load_program(dev_priv);

If this is needed for all platforms, couldn't we move that to intel_power_domains_init_hw()?
so we don't forget future platforms?

>  }
>  
>  static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> -- 
> 2.13.2
> 
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Re: [PATCH 1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume

[Imre Deak]

On Tue, Oct 03, 2017 at 10:40:18AM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 03, 2017 at 09:51:58AM +0000, Imre Deak wrote:
> > The DMC firmware program memory is lost after S3/S4 system suspend, so
> > we need to reprogram it during resume.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103070
> > Fixes: cebfcead63de ("drm/i915/DMC/CNL: Load DMC on CNL")
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Cc: Animesh Manna <animesh.manna@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 7933d1bc6a1c..3791c3f5f56d 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -2809,6 +2809,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> >  
> >  	/* 6. Enable DBUF */
> >  	gen9_dbuf_enable(dev_priv);
> > +
> > +	if (resume && dev_priv->csr.dmc_payload)
> > +		intel_csr_load_program(dev_priv);
> 
> If this is needed for all platforms, couldn't we move that to intel_power_domains_init_hw()?
> so we don't forget future platforms?

For GEN9_LP we also need to run the init sequence separately during
runtime resume, so these functions seem to be still the proper place to
call intel_csr_load_program().

> 
> >  }
> >  
> >  static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> > -- 
> > 2.13.2
> > 
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Re: [PATCH 1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume

[Rodrigo Vivi]

On Tue, Oct 03, 2017 at 05:57:11PM +0000, Imre Deak wrote:
> On Tue, Oct 03, 2017 at 10:40:18AM -0700, Rodrigo Vivi wrote:
> > On Tue, Oct 03, 2017 at 09:51:58AM +0000, Imre Deak wrote:
> > > The DMC firmware program memory is lost after S3/S4 system suspend, so
> > > we need to reprogram it during resume.
> > > 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103070
> > > Fixes: cebfcead63de ("drm/i915/DMC/CNL: Load DMC on CNL")
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Cc: Animesh Manna <animesh.manna@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
> > >  1 file changed, 3 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 7933d1bc6a1c..3791c3f5f56d 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -2809,6 +2809,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> > >  
> > >  	/* 6. Enable DBUF */
> > >  	gen9_dbuf_enable(dev_priv);
> > > +
> > > +	if (resume && dev_priv->csr.dmc_payload)
> > > +		intel_csr_load_program(dev_priv);
> > 
> > If this is needed for all platforms, couldn't we move that to intel_power_domains_init_hw()?
> > so we don't forget future platforms?
> 
> For GEN9_LP we also need to run the init sequence separately during
> runtime resume, so these functions seem to be still the proper place to
> call intel_csr_load_program().

ohh true...


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> 
> > 
> > >  }
> > >  
> > >  static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> > > -- 
> > > 2.13.2
> > > 
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