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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume
Date: Tue, 3 Oct 2017 11:02:23 -0700	[thread overview]
Message-ID: <20171003180223.3rdwqzcv77wqg554@intel.com> (raw)
In-Reply-To: <20171003175711.g2zix47rbt77ligi@ideak-desk.fi.intel.com>

On Tue, Oct 03, 2017 at 05:57:11PM +0000, Imre Deak wrote:
> On Tue, Oct 03, 2017 at 10:40:18AM -0700, Rodrigo Vivi wrote:
> > On Tue, Oct 03, 2017 at 09:51:58AM +0000, Imre Deak wrote:
> > > The DMC firmware program memory is lost after S3/S4 system suspend, so
> > > we need to reprogram it during resume.
> > > 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103070
> > > Fixes: cebfcead63de ("drm/i915/DMC/CNL: Load DMC on CNL")
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Cc: Animesh Manna <animesh.manna@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
> > >  1 file changed, 3 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 7933d1bc6a1c..3791c3f5f56d 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -2809,6 +2809,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> > >  
> > >  	/* 6. Enable DBUF */
> > >  	gen9_dbuf_enable(dev_priv);
> > > +
> > > +	if (resume && dev_priv->csr.dmc_payload)
> > > +		intel_csr_load_program(dev_priv);
> > 
> > If this is needed for all platforms, couldn't we move that to intel_power_domains_init_hw()?
> > so we don't forget future platforms?
> 
> For GEN9_LP we also need to run the init sequence separately during
> runtime resume, so these functions seem to be still the proper place to
> call intel_csr_load_program().

ohh true...


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> 
> > 
> > >  }
> > >  
> > >  static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> > > -- 
> > > 2.13.2
> > > 
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      reply	other threads:[~2017-10-03 18:02 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-03  9:51 [PATCH 1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume Imre Deak
2017-10-03  9:51 ` [PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation Imre Deak
2017-10-03 17:47   ` Rodrigo Vivi
2017-10-03 18:03     ` Imre Deak
2017-10-03 18:12       ` Rodrigo Vivi
2017-10-03 18:20     ` Rodrigo Vivi
2017-10-04  8:13       ` Imre Deak
2017-10-03 10:18 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume Patchwork
2017-10-04  8:52   ` Imre Deak
2017-10-03 17:40 ` [PATCH 1/2] " Rodrigo Vivi
2017-10-03 17:57   ` Imre Deak
2017-10-03 18:02     ` Rodrigo Vivi [this message]

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