* [PATCH] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage
@ 2017-09-29 21:01 James Ausmus
2017-09-29 21:25 ` ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: James Ausmus @ 2017-09-29 21:01 UTC (permalink / raw)
To: intel-gfx
Per BSpec, 400us is "BDW+ Do not use this setting." Also rename 1600us to
MAX, as the value varies per platform - pre-CNL it means 1600us, and CNL is
3200us.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_dp.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ee0d4f14ac98..997a60bd6140 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5229,7 +5229,7 @@ enum {
#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
-#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
+#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 90e756c76f10..df301e00d9d9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1019,7 +1019,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
else
precharge = 5;
- if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
+ if (IS_BROADWELL(dev_priv))
timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
else
timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
@@ -1044,7 +1044,7 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
DP_AUX_CH_CTL_DONE |
(has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_TIME_OUT_1600us |
+ DP_AUX_CH_CTL_TIME_OUT_MAX |
DP_AUX_CH_CTL_RECEIVE_ERROR |
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
--
2.14.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage
2017-09-29 21:01 [PATCH] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage James Ausmus
@ 2017-09-29 21:25 ` Patchwork
2017-09-29 22:17 ` ✗ Fi.CI.IGT: warning " Patchwork
2017-10-04 20:09 ` [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming James Ausmus
2 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2017-09-29 21:25 UTC (permalink / raw)
To: James Ausmus; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage
URL : https://patchwork.freedesktop.org/series/31204/
State : success
== Summary ==
Series 31204v1 drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage
https://patchwork.freedesktop.org/api/1.0/series/31204/revisions/1/mbox/
Test chamelium:
Subgroup dp-crc-fast:
pass -> FAIL (fi-kbl-7500u) fdo#102514
Subgroup hdmi-crc-fast:
dmesg-warn -> PASS (fi-skl-6700k) fdo#103019
Test kms_busy:
Subgroup basic-flip-c:
incomplete -> PASS (fi-bxt-j4205) fdo#102035
Test drv_module_reload:
Subgroup basic-reload-inject:
dmesg-warn -> PASS (fi-glk-1) fdo#102777
fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#103019 https://bugs.freedesktop.org/show_bug.cgi?id=103019
fdo#102035 https://bugs.freedesktop.org/show_bug.cgi?id=102035
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:445s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:472s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:418s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:526s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:278s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:506s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:500s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:494s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:479s
fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:556s
fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:628s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:415s
fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:577s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:426s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:406s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:433s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:476s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:466s
fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:459s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:578s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:593s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:547s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:460s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:758s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:494s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:476s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:568s
fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:417s
e650b9cdaff616445f38986379b1c0c4b03a4282 drm-tip: 2017y-09m-29d-11h-52m-41s UTC integration manifest
0bf2524dc912 drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5864/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* ✗ Fi.CI.IGT: warning for drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage
2017-09-29 21:01 [PATCH] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage James Ausmus
2017-09-29 21:25 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-09-29 22:17 ` Patchwork
2017-10-04 20:09 ` [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming James Ausmus
2 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2017-09-29 22:17 UTC (permalink / raw)
To: James Ausmus; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage
URL : https://patchwork.freedesktop.org/series/31204/
State : warning
== Summary ==
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
pass -> SKIP (shard-hsw)
Subgroup fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
pass -> SKIP (shard-hsw)
Subgroup fbc-badstride:
pass -> SKIP (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test kms_plane_multiple:
Subgroup atomic-pipe-A-tiling-x:
pass -> SKIP (shard-hsw)
Test pm_rpm:
Subgroup modeset-stress-extra-wait:
pass -> SKIP (shard-hsw)
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
shard-hsw total:2429 pass:1328 dwarn:3 dfail:0 fail:10 skip:1088 time:9894s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5864/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming
2017-09-29 21:01 [PATCH] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage James Ausmus
2017-09-29 21:25 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-09-29 22:17 ` ✗ Fi.CI.IGT: warning " Patchwork
@ 2017-10-04 20:09 ` James Ausmus
2017-10-04 20:09 ` [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting James Ausmus
2017-10-04 20:28 ` [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming Rodrigo Vivi
2 siblings, 2 replies; 13+ messages in thread
From: James Ausmus @ 2017-10-04 20:09 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi
Rename DP_AUX_CH_CTL_TIME_OUT_1600us to DP_AUX_CH_CTL_TIME_OUT_MAX, as
the meaning of the (3 << 26) value varies per platform, but it's always the
maximum timeout for that platform. Pre-CNL it means 1600us, and for CNL
it means 3200us.
v2:
-Split in to two patches (Rodrigo)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_dp.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 39ad9327e2a0..0324e0ca7597 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5239,7 +5239,7 @@ enum {
#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
-#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
+#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 90e756c76f10..5b4c9484575b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1044,7 +1044,7 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
DP_AUX_CH_CTL_DONE |
(has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_TIME_OUT_1600us |
+ DP_AUX_CH_CTL_TIME_OUT_MAX |
DP_AUX_CH_CTL_RECEIVE_ERROR |
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
2017-10-04 20:09 ` [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming James Ausmus
@ 2017-10-04 20:09 ` James Ausmus
2017-10-04 20:24 ` Rodrigo Vivi
2017-10-04 20:28 ` [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming Rodrigo Vivi
1 sibling, 1 reply; 13+ messages in thread
From: James Ausmus @ 2017-10-04 20:09 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi
Per BSpec, 400us is "BDW+ Do not use this setting." - not just PORT_A.
Set BDW to 600us unconditionally.
v2:
-Split in to two patches (Rodrigo)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5b4c9484575b..df301e00d9d9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1019,7 +1019,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
else
precharge = 5;
- if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
+ if (IS_BROADWELL(dev_priv))
timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
else
timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
--
2.14.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
2017-10-04 20:09 ` [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting James Ausmus
@ 2017-10-04 20:24 ` Rodrigo Vivi
2017-10-04 22:54 ` Runyan, Arthur J
0 siblings, 1 reply; 13+ messages in thread
From: Rodrigo Vivi @ 2017-10-04 20:24 UTC (permalink / raw)
To: James Ausmus; +Cc: intel-gfx, arthur.j.runyan, ben
On Wed, Oct 04, 2017 at 08:09:22PM +0000, James Ausmus wrote:
> Per BSpec, 400us is "BDW+ Do not use this setting." - not just PORT_A.
> Set BDW to 600us unconditionally.
Besides that statement I also found on BSpec:
"
Workaround
Project
BDW, EXCLUDE(CHV)
Set the Timeout timer value to at least 600us before initiating a transaction.
"
Also I tracked this on the log and arrived to commit 'a81a507d487c
("drm/i915/bdw: Change dp aux timeout to 600us on DDIA")'
It seems during BDW enabling HW team found that need but only for port A
and later they might have extended it and we never noticed.
Ccin't Art and Ben here to see if they can comment on that.
But I believe we should add this so
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> v2:
> -Split in to two patches (Rodrigo)
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5b4c9484575b..df301e00d9d9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1019,7 +1019,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
> else
> precharge = 5;
>
> - if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
> + if (IS_BROADWELL(dev_priv))
> timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
> else
> timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> --
> 2.14.1
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
2017-10-04 20:24 ` Rodrigo Vivi
@ 2017-10-04 22:54 ` Runyan, Arthur J
2017-10-12 18:58 ` Ausmus, James
0 siblings, 1 reply; 13+ messages in thread
From: Runyan, Arthur J @ 2017-10-04 22:54 UTC (permalink / raw)
To: Vivi, Rodrigo, Ausmus, James
Cc: intel-gfx@lists.freedesktop.org, ben@bwidawsk.net
I think the failure was with one particularly slow eDP panel, but it is safer to apply this to all ports.
-----Original Message-----
From: Vivi, Rodrigo
Sent: Wednesday, 4 October, 2017 1:25 PM
To: Ausmus, James <james.ausmus@intel.com>
Cc: intel-gfx@lists.freedesktop.org; ville.syrjala@linux.intel.com; jani.nikula@linux.intel.com; Runyan, Arthur J <arthur.j.runyan@intel.com>; ben@bwidawsk.net
Subject: Re: [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
On Wed, Oct 04, 2017 at 08:09:22PM +0000, James Ausmus wrote:
> Per BSpec, 400us is "BDW+ Do not use this setting." - not just PORT_A.
> Set BDW to 600us unconditionally.
Besides that statement I also found on BSpec:
"
Workaround
Project
BDW, EXCLUDE(CHV)
Set the Timeout timer value to at least 600us before initiating a transaction.
"
Also I tracked this on the log and arrived to commit 'a81a507d487c
("drm/i915/bdw: Change dp aux timeout to 600us on DDIA")'
It seems during BDW enabling HW team found that need but only for port A
and later they might have extended it and we never noticed.
Ccin't Art and Ben here to see if they can comment on that.
But I believe we should add this so
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> v2:
> -Split in to two patches (Rodrigo)
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5b4c9484575b..df301e00d9d9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1019,7 +1019,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
> else
> precharge = 5;
>
> - if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
> + if (IS_BROADWELL(dev_priv))
> timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
> else
> timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> --
> 2.14.1
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
2017-10-04 22:54 ` Runyan, Arthur J
@ 2017-10-12 18:58 ` Ausmus, James
2017-10-12 20:59 ` Rodrigo Vivi
0 siblings, 1 reply; 13+ messages in thread
From: Ausmus, James @ 2017-10-12 18:58 UTC (permalink / raw)
To: Runyan, Arthur J
Cc: ben@bwidawsk.net, intel-gfx@lists.freedesktop.org, Vivi, Rodrigo
On Wed, Oct 4, 2017 at 3:54 PM, Runyan, Arthur J
<arthur.j.runyan@intel.com> wrote:
> I think the failure was with one particularly slow eDP panel, but it is safer to apply this to all ports.
>
Thanks Art. Anyone else have thoughts/comments on this, or should this
be good for merge now?
Thanks!
-James
> -----Original Message-----
> From: Vivi, Rodrigo
> Sent: Wednesday, 4 October, 2017 1:25 PM
> To: Ausmus, James <james.ausmus@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; ville.syrjala@linux.intel.com; jani.nikula@linux.intel.com; Runyan, Arthur J <arthur.j.runyan@intel.com>; ben@bwidawsk.net
> Subject: Re: [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
>
> On Wed, Oct 04, 2017 at 08:09:22PM +0000, James Ausmus wrote:
>> Per BSpec, 400us is "BDW+ Do not use this setting." - not just PORT_A.
>> Set BDW to 600us unconditionally.
>
> Besides that statement I also found on BSpec:
>
> "
> Workaround
> Project
> BDW, EXCLUDE(CHV)
> Set the Timeout timer value to at least 600us before initiating a transaction.
> "
>
> Also I tracked this on the log and arrived to commit 'a81a507d487c
> ("drm/i915/bdw: Change dp aux timeout to 600us on DDIA")'
>
> It seems during BDW enabling HW team found that need but only for port A
> and later they might have extended it and we never noticed.
>
> Ccin't Art and Ben here to see if they can comment on that.
>
> But I believe we should add this so
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
>>
>> v2:
>> -Split in to two patches (Rodrigo)
>>
>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: James Ausmus <james.ausmus@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 5b4c9484575b..df301e00d9d9 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1019,7 +1019,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
>> else
>> precharge = 5;
>>
>> - if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
>> + if (IS_BROADWELL(dev_priv))
>> timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
>> else
>> timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
>> --
>> 2.14.1
>>
--
James Ausmus
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
2017-10-12 18:58 ` Ausmus, James
@ 2017-10-12 20:59 ` Rodrigo Vivi
2017-10-12 21:33 ` Ausmus, James
0 siblings, 1 reply; 13+ messages in thread
From: Rodrigo Vivi @ 2017-10-12 20:59 UTC (permalink / raw)
To: Ausmus, James
Cc: intel-gfx@lists.freedesktop.org, Runyan, Arthur J,
ben@bwidawsk.net
On Thu, Oct 12, 2017 at 06:58:20PM +0000, Ausmus, James wrote:
> On Wed, Oct 4, 2017 at 3:54 PM, Runyan, Arthur J
> <arthur.j.runyan@intel.com> wrote:
> > I think the failure was with one particularly slow eDP panel, but it is safer to apply this to all ports.
> >
>
> Thanks Art. Anyone else have thoughts/comments on this, or should this
> be good for merge now?
There was a warning on CI. And v2 didn't get fully tested because CI got
confused about name changes on v2.
So, could you please resend as a new series. Without the "in-reply-to"
so we get the full CI run on it?
Thanks,
Rodrigo
>
> Thanks!
>
> -James
>
> > -----Original Message-----
> > From: Vivi, Rodrigo
> > Sent: Wednesday, 4 October, 2017 1:25 PM
> > To: Ausmus, James <james.ausmus@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; ville.syrjala@linux.intel.com; jani.nikula@linux.intel.com; Runyan, Arthur J <arthur.j.runyan@intel.com>; ben@bwidawsk.net
> > Subject: Re: [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
> >
> > On Wed, Oct 04, 2017 at 08:09:22PM +0000, James Ausmus wrote:
> >> Per BSpec, 400us is "BDW+ Do not use this setting." - not just PORT_A.
> >> Set BDW to 600us unconditionally.
> >
> > Besides that statement I also found on BSpec:
> >
> > "
> > Workaround
> > Project
> > BDW, EXCLUDE(CHV)
> > Set the Timeout timer value to at least 600us before initiating a transaction.
> > "
> >
> > Also I tracked this on the log and arrived to commit 'a81a507d487c
> > ("drm/i915/bdw: Change dp aux timeout to 600us on DDIA")'
> >
> > It seems during BDW enabling HW team found that need but only for port A
> > and later they might have extended it and we never noticed.
> >
> > Ccin't Art and Ben here to see if they can comment on that.
> >
> > But I believe we should add this so
> >
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >
> >>
> >> v2:
> >> -Split in to two patches (Rodrigo)
> >>
> >> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> >> index 5b4c9484575b..df301e00d9d9 100644
> >> --- a/drivers/gpu/drm/i915/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >> @@ -1019,7 +1019,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
> >> else
> >> precharge = 5;
> >>
> >> - if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
> >> + if (IS_BROADWELL(dev_priv))
> >> timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
> >> else
> >> timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> >> --
> >> 2.14.1
> >>
>
>
>
> --
>
>
> James Ausmus
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
2017-10-12 20:59 ` Rodrigo Vivi
@ 2017-10-12 21:33 ` Ausmus, James
0 siblings, 0 replies; 13+ messages in thread
From: Ausmus, James @ 2017-10-12 21:33 UTC (permalink / raw)
To: Rodrigo Vivi
Cc: intel-gfx@lists.freedesktop.org, Runyan, Arthur J,
ben@bwidawsk.net
On Thu, Oct 12, 2017 at 1:59 PM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Thu, Oct 12, 2017 at 06:58:20PM +0000, Ausmus, James wrote:
>> On Wed, Oct 4, 2017 at 3:54 PM, Runyan, Arthur J
>> <arthur.j.runyan@intel.com> wrote:
>> > I think the failure was with one particularly slow eDP panel, but it is safer to apply this to all ports.
>> >
>>
>> Thanks Art. Anyone else have thoughts/comments on this, or should this
>> be good for merge now?
>
> There was a warning on CI. And v2 didn't get fully tested because CI got
> confused about name changes on v2.
>
> So, could you please resend as a new series. Without the "in-reply-to"
> so we get the full CI run on it?
Done - thanks!
-James
>
> Thanks,
> Rodrigo
>
>>
>> Thanks!
>>
>> -James
>>
>> > -----Original Message-----
>> > From: Vivi, Rodrigo
>> > Sent: Wednesday, 4 October, 2017 1:25 PM
>> > To: Ausmus, James <james.ausmus@intel.com>
>> > Cc: intel-gfx@lists.freedesktop.org; ville.syrjala@linux.intel.com; jani.nikula@linux.intel.com; Runyan, Arthur J <arthur.j.runyan@intel.com>; ben@bwidawsk.net
>> > Subject: Re: [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
>> >
>> > On Wed, Oct 04, 2017 at 08:09:22PM +0000, James Ausmus wrote:
>> >> Per BSpec, 400us is "BDW+ Do not use this setting." - not just PORT_A.
>> >> Set BDW to 600us unconditionally.
>> >
>> > Besides that statement I also found on BSpec:
>> >
>> > "
>> > Workaround
>> > Project
>> > BDW, EXCLUDE(CHV)
>> > Set the Timeout timer value to at least 600us before initiating a transaction.
>> > "
>> >
>> > Also I tracked this on the log and arrived to commit 'a81a507d487c
>> > ("drm/i915/bdw: Change dp aux timeout to 600us on DDIA")'
>> >
>> > It seems during BDW enabling HW team found that need but only for port A
>> > and later they might have extended it and we never noticed.
>> >
>> > Ccin't Art and Ben here to see if they can comment on that.
>> >
>> > But I believe we should add this so
>> >
>> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> >
>> >>
>> >> v2:
>> >> -Split in to two patches (Rodrigo)
>> >>
>> >> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >> Signed-off-by: James Ausmus <james.ausmus@intel.com>
>> >> ---
>> >> drivers/gpu/drm/i915/intel_dp.c | 2 +-
>> >> 1 file changed, 1 insertion(+), 1 deletion(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> >> index 5b4c9484575b..df301e00d9d9 100644
>> >> --- a/drivers/gpu/drm/i915/intel_dp.c
>> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> >> @@ -1019,7 +1019,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
>> >> else
>> >> precharge = 5;
>> >>
>> >> - if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
>> >> + if (IS_BROADWELL(dev_priv))
>> >> timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
>> >> else
>> >> timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
>> >> --
>> >> 2.14.1
>> >>
>>
>>
>>
>> --
>>
>>
>> James Ausmus
--
James Ausmus
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming
2017-10-04 20:09 ` [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming James Ausmus
2017-10-04 20:09 ` [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting James Ausmus
@ 2017-10-04 20:28 ` Rodrigo Vivi
1 sibling, 0 replies; 13+ messages in thread
From: Rodrigo Vivi @ 2017-10-04 20:28 UTC (permalink / raw)
To: James Ausmus; +Cc: intel-gfx
On Wed, Oct 04, 2017 at 08:09:21PM +0000, James Ausmus wrote:
> Rename DP_AUX_CH_CTL_TIME_OUT_1600us to DP_AUX_CH_CTL_TIME_OUT_MAX, as
> the meaning of the (3 << 26) value varies per platform, but it's always the
> maximum timeout for that platform. Pre-CNL it means 1600us, and for CNL
> it means 3200us.
Yeap...
>
> v2:
> -Split in to two patches (Rodrigo)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 39ad9327e2a0..0324e0ca7597 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5239,7 +5239,7 @@ enum {
> #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
> #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
> #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
> -#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
> +#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
makes sense for me...
I was going to complain about the tab+spaces but I notice the whole block
there is already like this so nevermind ;)
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
> #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
> #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 90e756c76f10..5b4c9484575b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1044,7 +1044,7 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> DP_AUX_CH_CTL_DONE |
> (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
> DP_AUX_CH_CTL_TIME_OUT_ERROR |
> - DP_AUX_CH_CTL_TIME_OUT_1600us |
> + DP_AUX_CH_CTL_TIME_OUT_MAX |
> DP_AUX_CH_CTL_RECEIVE_ERROR |
> (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
> --
> 2.14.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming
@ 2017-10-12 21:30 James Ausmus
2017-10-12 21:30 ` [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting James Ausmus
0 siblings, 1 reply; 13+ messages in thread
From: James Ausmus @ 2017-10-12 21:30 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi
Rename DP_AUX_CH_CTL_TIME_OUT_1600us to DP_AUX_CH_CTL_TIME_OUT_MAX, as
the meaning of the (3 << 26) value varies per platform, but it's always the
maximum timeout for that platform. Pre-CNL it means 1600us, and for CNL
it means 3200us.
v2:
-Split in to two patches (Rodrigo)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_dp.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d2d0a83c09b6..5f99d4d6291b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5242,7 +5242,7 @@ enum {
#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
-#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
+#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 753404280a19..3f0d37fa833f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1032,7 +1032,7 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
DP_AUX_CH_CTL_DONE |
(has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_TIME_OUT_1600us |
+ DP_AUX_CH_CTL_TIME_OUT_MAX |
DP_AUX_CH_CTL_RECEIVE_ERROR |
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
2017-10-12 21:30 James Ausmus
@ 2017-10-12 21:30 ` James Ausmus
2017-10-12 21:52 ` Rodrigo Vivi
0 siblings, 1 reply; 13+ messages in thread
From: James Ausmus @ 2017-10-12 21:30 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi
Per BSpec, 400us is "BDW+ Do not use this setting." - not just PORT_A.
Set BDW to 600us unconditionally.
v2:
-Split in to two patches (Rodrigo)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3f0d37fa833f..4b65cf137f79 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1007,7 +1007,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
else
precharge = 5;
- if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
+ if (IS_BROADWELL(dev_priv))
timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
else
timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
2017-10-12 21:30 ` [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting James Ausmus
@ 2017-10-12 21:52 ` Rodrigo Vivi
0 siblings, 0 replies; 13+ messages in thread
From: Rodrigo Vivi @ 2017-10-12 21:52 UTC (permalink / raw)
To: James Ausmus; +Cc: intel-gfx
On Thu, Oct 12, 2017 at 09:30:37PM +0000, James Ausmus wrote:
> Per BSpec, 400us is "BDW+ Do not use this setting." - not just PORT_A.
> Set BDW to 600us unconditionally.
>
> v2:
> -Split in to two patches (Rodrigo)
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
same
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3f0d37fa833f..4b65cf137f79 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1007,7 +1007,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
> else
> precharge = 5;
>
> - if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
> + if (IS_BROADWELL(dev_priv))
> timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
> else
> timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> --
> 2.14.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2017-10-12 21:52 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-09-29 21:01 [PATCH] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming, BDW usage James Ausmus
2017-09-29 21:25 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-09-29 22:17 ` ✗ Fi.CI.IGT: warning " Patchwork
2017-10-04 20:09 ` [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming James Ausmus
2017-10-04 20:09 ` [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting James Ausmus
2017-10-04 20:24 ` Rodrigo Vivi
2017-10-04 22:54 ` Runyan, Arthur J
2017-10-12 18:58 ` Ausmus, James
2017-10-12 20:59 ` Rodrigo Vivi
2017-10-12 21:33 ` Ausmus, James
2017-10-04 20:28 ` [PATCH v2 1/2] drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT naming Rodrigo Vivi
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2017-10-12 21:30 James Ausmus
2017-10-12 21:30 ` [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting James Ausmus
2017-10-12 21:52 ` Rodrigo Vivi
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