Re: [PATCH 08/13] drm/i915/cnl: DVFS for PLL disabling

[Manasi Navare <manasi.d.navare@intel.com>]

On Tue, Oct 03, 2017 at 12:06:09AM -0700, Rodrigo Vivi wrote:
> From: "Kahola, Mika" <mika.kahola@intel.com>
> 
> Display Voltage and Frequency Switching (DVFS) is used to adjust the
> display voltage to match the display clock frequencies. To save power the
> voltage is set to minimum when disabling PLL.
> 
> The sequence before frequency change is the following and it requests
> the power controller to raise voltage to maximum
> 
> - Ensure any previous GT Driver Mailbox transaction is complete.
> - Write GT Driver Mailbox Data Low = 0x3.
> - Write GT Driver Mailbox Data High = 0x0.
> - Write GT Driver Mailbox Interface = 0x80000007.
> - Poll GT Driver Mailbox Interface for Run/Busy indication cleared (bit 31 = 0).
> - Read GT Driver Mailbox Data Low, if bit 0 is 0x1, continue, else restart the sequence.
>   Timeout after 3ms
> 
> The sequence after frequency change is the following and it requests
> the port controller to lower voltage to the minimum.
> 
> - Write GT Driver Mailbox Data Low = 0x0
> - Write GT Driver Mailbox Data High = 0x0.
> - Write GT Driver Mailbox Interface = 0x80000007.
> 
> v2: reuse Paulo's work on cdclk. This patch depends on Paulo's patch
>     [PATCH 02/12] drm/i915/cnl: extract cnl_dvfs_{pre,post}_change
> v3: (By Rodrigo): Fix typo on Paulo's name.
> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Kahola, Mika <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi
> ---
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 14 ++++++--------
>  1 file changed, 6 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 6030fbafa580..a71a6c396bbd 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2058,6 +2058,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
>  				struct intel_shared_dpll *pll)
>  {
>  	uint32_t val;
> +	int ret;
>  
>  	/*
>  	 * 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
> @@ -2067,11 +2068,9 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
>  	/*
>  	 * 2. If the frequency will result in a change to the voltage
>  	 * requirement, follow the Display Voltage Frequency Switching
> -	 * Sequence Before Frequency Change
> -	 *
> -	 * FIXME: (DVFS) is used to adjust the display voltage to match the
> -	 * display clock frequencies
> +	 * (DVFS) Sequence Before Frequency Change
>  	 */
> +	ret = cnl_dvfs_pre_change(dev_priv);
>  
>  	/* 3. Disable DPLL through DPLL_ENABLE. */
>  	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
> @@ -2089,11 +2088,10 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
>  	/*
>  	 * 5. If the frequency will result in a change to the voltage
>  	 * requirement, follow the Display Voltage Frequency Switching
> -	 * Sequence After Frequency Change
> -	 *
> -	 * FIXME: (DVFS) is used to adjust the display voltage to match the
> -	 * display clock frequencies
> +	 * (DVFS) Sequence After Frequency Change
>  	 */
> +	if (ret == 0)
> +		cnl_dvfs_post_change(dev_priv, 0);
>  
>  	/* 6. Disable DPLL power in DPLL_ENABLE. */
>  	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
> -- 
> 2.13.5
> 
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