From: Tvrtko Ursulin <tursulin@ursulin.net>
To: Intel-gfx@lists.freedesktop.org
Subject: [PATCH i-g-t 8/9] gem_wsim: Busy stats balancers
Date: Tue, 10 Oct 2017 10:30:07 +0100 [thread overview]
Message-ID: <20171010093008.22804-9-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20171010093008.22804-1-tvrtko.ursulin@linux.intel.com>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Add busy and busy-avg balancers which make balancing decisions by looking
at engine busyness via the i915 PMU.
And thus are able to make decisions on the actual instantaneous load of
the system, and not use metrics that lag behind by a batch or two. In
doing so, each client should be able to greedily maximise their own
usage of the system, leading to improved load balancing even in the face
of other uncooperative clients. On the other hand, we are only using the
instantaneous load without coupling in the predictive factor for dispatch
and execution length.
v2:
* Commit text. (Chris Wilson)
* Rename get_stats to get_pmu_stats. (Chris Wilson)
* Fix PMU readout in VCS remap mode.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
benchmarks/Makefile.am | 2 +-
benchmarks/gem_wsim.c | 142 +++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 143 insertions(+), 1 deletion(-)
diff --git a/benchmarks/Makefile.am b/benchmarks/Makefile.am
index d066112a32a2..a81a55e01697 100644
--- a/benchmarks/Makefile.am
+++ b/benchmarks/Makefile.am
@@ -21,7 +21,7 @@ gem_latency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_latency_LDADD = $(LDADD) -lpthread
gem_syslatency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_syslatency_LDADD = $(LDADD) -lpthread -lrt
-gem_wsim_LDADD = $(LDADD) -lpthread
+gem_wsim_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la -lpthread
EXTRA_DIST= \
README \
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 82fe6ba9ec5f..8b2cd90659a9 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -50,6 +50,7 @@
#include "intel_io.h"
#include "igt_aux.h"
#include "igt_rand.h"
+#include "igt_perf.h"
#include "sw_sync.h"
#include "ewma.h"
@@ -188,6 +189,16 @@ struct workload
uint32_t last[NUM_ENGINES];
} rt;
};
+
+ struct busy_balancer {
+ int fd;
+ bool first;
+ unsigned int num_engines;
+ unsigned int engine_map[5];
+ uint64_t t_prev;
+ uint64_t prev[5];
+ double busy[5];
+ } busy_balancer;
};
static const unsigned int nop_calibration_us = 1000;
@@ -993,6 +1004,8 @@ struct workload_balancer {
unsigned int flags;
unsigned int min_gen;
+ int (*init)(const struct workload_balancer *balancer,
+ struct workload *wrk);
unsigned int (*get_qd)(const struct workload_balancer *balancer,
struct workload *wrk,
enum intel_engine_id engine);
@@ -1242,6 +1255,108 @@ context_balance(const struct workload_balancer *balancer,
return get_vcs_engine(wrk->ctx_list[w->context].static_vcs);
}
+static unsigned int
+get_engine_busy(const struct workload_balancer *balancer,
+ struct workload *wrk, enum intel_engine_id engine)
+{
+ struct busy_balancer *bb = &wrk->busy_balancer;
+
+ if (engine == VCS2 && (wrk->flags & VCS2REMAP))
+ engine = BCS;
+
+ return bb->busy[bb->engine_map[engine]];
+}
+
+static void
+get_pmu_stats(const struct workload_balancer *b, struct workload *wrk)
+{
+ struct busy_balancer *bb = &wrk->busy_balancer;
+ uint64_t val[7];
+ unsigned int i;
+
+ igt_assert_eq(read(bb->fd, val, sizeof(val)),
+ (2 + bb->num_engines) * sizeof(uint64_t));
+
+ if (!bb->first) {
+ for (i = 0; i < bb->num_engines; i++) {
+ double d;
+
+ d = (val[2 + i] - bb->prev[i]) * 100;
+ d /= val[1] - bb->t_prev;
+ bb->busy[i] = d;
+ }
+ }
+
+ for (i = 0; i < bb->num_engines; i++)
+ bb->prev[i] = val[2 + i];
+
+ bb->t_prev = val[1];
+ bb->first = false;
+}
+
+static enum intel_engine_id
+busy_avg_balance(const struct workload_balancer *balancer,
+ struct workload *wrk, struct w_step *w)
+{
+ get_pmu_stats(balancer, wrk);
+
+ return qdavg_balance(balancer, wrk, w);
+}
+
+static enum intel_engine_id
+busy_balance(const struct workload_balancer *balancer,
+ struct workload *wrk, struct w_step *w)
+{
+ get_pmu_stats(balancer, wrk);
+
+ return qd_balance(balancer, wrk, w);
+}
+
+static int
+busy_init(const struct workload_balancer *balancer, struct workload *wrk)
+{
+ struct busy_balancer *bb = &wrk->busy_balancer;
+ struct engine_desc {
+ unsigned class, inst;
+ enum intel_engine_id id;
+ } *d, engines[] = {
+ { I915_ENGINE_CLASS_RENDER, 0, RCS },
+ { I915_ENGINE_CLASS_COPY, 0, BCS },
+ { I915_ENGINE_CLASS_VIDEO, 0, VCS1 },
+ { I915_ENGINE_CLASS_VIDEO, 1, VCS2 },
+ { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, VECS },
+ { 0, 0, VCS }
+ };
+
+ bb->num_engines = 0;
+ bb->first = true;
+ bb->fd = -1;
+
+ for (d = &engines[0]; d->id != VCS; d++) {
+ int pfd;
+
+ pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ d->inst),
+ bb->fd);
+ if (pfd < 0) {
+ if (d->id != VCS2)
+ return -(10 + bb->num_engines);
+ else
+ continue;
+ }
+
+ if (bb->num_engines == 0)
+ bb->fd = pfd;
+
+ bb->engine_map[d->id] = bb->num_engines++;
+ }
+
+ if (bb->num_engines < 5 && !(wrk->flags & VCS2REMAP))
+ return -1;
+
+ return 0;
+}
+
static const struct workload_balancer all_balancers[] = {
{
.id = 0,
@@ -1315,6 +1430,22 @@ static const struct workload_balancer all_balancers[] = {
.desc = "Static round-robin VCS assignment at context creation.",
.balance = context_balance,
},
+ {
+ .id = 9,
+ .name = "busy",
+ .desc = "Engine busyness based balancing.",
+ .init = busy_init,
+ .get_qd = get_engine_busy,
+ .balance = busy_balance,
+ },
+ {
+ .id = 10,
+ .name = "busy-avg",
+ .desc = "Average engine busyness based balancing.",
+ .init = busy_init,
+ .get_qd = get_engine_busy,
+ .balance = busy_avg_balance,
+ },
};
static unsigned int
@@ -2226,6 +2357,17 @@ int main(int argc, char **argv)
(verbose > 0 && master_workload == i);
prepare_workload(i, w[i], flags_);
+
+ if (balancer && balancer->init) {
+ int ret = balancer->init(balancer, w[i]);
+ if (ret) {
+ if (verbose)
+ fprintf(stderr,
+ "Failed to initialize balancing! (%u=%d)\n",
+ i, ret);
+ return 1;
+ }
+ }
}
gem_quiescent_gpu(fd);
--
2.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2017-10-10 9:30 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-10 9:29 [PATCH v4 i-g-t 0/7] IGT PMU support Tvrtko Ursulin
2017-10-10 9:30 ` [PATCH i-g-t 1/9] intel-gpu-overlay: Move local perf implementation to a library Tvrtko Ursulin
2017-11-21 19:34 ` [PATCH i-g-t v3 " Tvrtko Ursulin
2017-10-10 9:30 ` [PATCH i-g-t 2/9] intel-gpu-overlay: Consolidate perf PMU access to library Tvrtko Ursulin
2017-10-10 12:21 ` Chris Wilson
2017-10-10 9:30 ` [PATCH i-g-t 3/9] lib/perf: Fix data types and general tidy Tvrtko Ursulin
2017-10-10 12:22 ` Chris Wilson
2017-10-10 9:30 ` [PATCH i-g-t 4/9] intel-gpu-overlay: Fix interrupts PMU readout Tvrtko Ursulin
2017-10-10 12:23 ` Chris Wilson
2017-10-10 14:17 ` [PATCH i-g-t v2 " Tvrtko Ursulin
2017-10-10 9:30 ` [PATCH i-g-t 5/9] intel-gpu-overlay: Catch-up to new i915 PMU Tvrtko Ursulin
2017-11-21 18:20 ` Tvrtko Ursulin
2017-10-10 9:30 ` [PATCH i-g-t 6/9] intel-gpu-overlay: Use RAPL PMU for power reading Tvrtko Ursulin
2017-10-10 11:30 ` [PATCH i-g-t v2 " Tvrtko Ursulin
2017-10-10 12:05 ` [PATCH i-g-t v3 " Tvrtko Ursulin
2017-10-10 12:25 ` Chris Wilson
2017-11-21 19:35 ` [PATCH i-g-t v4 " Tvrtko Ursulin
2017-10-10 9:30 ` [PATCH i-g-t 7/9] tests/perf_pmu: Tests for i915 PMU API Tvrtko Ursulin
2017-10-10 12:37 ` Chris Wilson
2017-10-10 13:38 ` Tvrtko Ursulin
2017-10-10 13:46 ` Chris Wilson
2017-10-10 14:17 ` [PATCH i-g-t v6 " Tvrtko Ursulin
2017-10-10 16:39 ` Chris Wilson
2017-10-11 12:54 ` [PATCH i-g-t v7 " Tvrtko Ursulin
2017-11-21 11:50 ` Chris Wilson
2017-11-21 18:21 ` [PATCH i-g-t v8 " Tvrtko Ursulin
2017-11-21 19:36 ` [PATCH i-g-t v9 " Tvrtko Ursulin
2017-10-10 9:30 ` Tvrtko Ursulin [this message]
2017-11-21 19:37 ` [PATCH i-g-t v3 8/9] gem_wsim: Busy stats balancers Tvrtko Ursulin
2017-10-10 9:30 ` [PATCH i-g-t 9/9] media-bench.pl: Add busy balancers to the list Tvrtko Ursulin
2017-11-21 11:51 ` Chris Wilson
2017-10-10 9:42 ` ✗ Fi.CI.BAT: failure for IGT PMU support (rev7) Patchwork
2017-10-10 12:06 ` ✓ Fi.CI.BAT: success for IGT PMU support (rev8) Patchwork
2017-10-10 13:48 ` ✓ Fi.CI.BAT: success for IGT PMU support (rev9) Patchwork
2017-10-10 15:19 ` ✗ Fi.CI.IGT: failure for IGT PMU support (rev8) Patchwork
2017-10-10 18:42 ` ✓ Fi.CI.BAT: success for IGT PMU support (rev11) Patchwork
2017-10-11 1:28 ` ✓ Fi.CI.IGT: " Patchwork
2017-10-11 14:09 ` ✓ Fi.CI.BAT: success for IGT PMU support (rev12) Patchwork
2017-10-11 20:16 ` ✗ Fi.CI.IGT: failure " Patchwork
2017-11-22 11:41 ` ✓ Fi.CI.BAT: success for IGT PMU support (rev18) Patchwork
2017-11-22 11:57 ` Tvrtko Ursulin
2017-11-22 12:47 ` Petri Latvala
2017-11-22 14:31 ` ✓ Fi.CI.IGT: " Patchwork
2017-11-22 14:39 ` Petri Latvala
2017-11-22 14:50 ` Petri Latvala
2017-11-22 17:09 ` Tvrtko Ursulin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20171010093008.22804-9-tvrtko.ursulin@linux.intel.com \
--to=tursulin@ursulin.net \
--cc=Intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox