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From: Tvrtko Ursulin <tursulin@ursulin.net>
To: Intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/9] drm/i915: Extract intel_get_cagf
Date: Wed, 11 Oct 2017 13:55:09 +0100	[thread overview]
Message-ID: <20171011125517.1372-2-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20171011125517.1372-1-tvrtko.ursulin@linux.intel.com>

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Code to be shared between debugfs and the PMU implementation.

v2: Checkpatch cleanup.
v3: Also consolidate i915_sysfs.c/gt_act_freq_mhz_show.
v4: Rebase.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v2)
---
 drivers/gpu/drm/i915/i915_debugfs.c |  9 ++-------
 drivers/gpu/drm/i915/i915_drv.h     |  2 ++
 drivers/gpu/drm/i915/i915_sysfs.c   | 11 +++--------
 drivers/gpu/drm/i915/intel_pm.c     | 14 ++++++++++++++
 4 files changed, 21 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0bb6e01121fc..8d6b096891a5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1178,13 +1178,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
 		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
 		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
-		if (INTEL_GEN(dev_priv) >= 9)
-			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
-		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
-			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
-		else
-			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
-		cagf = intel_gpu_freq(dev_priv, cagf);
+		cagf = intel_gpu_freq(dev_priv,
+				      intel_get_cagf(dev_priv, rpstat));
 
 		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6bbc4b83aa0a..0f5e336a67f4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4187,6 +4187,8 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
 			   const i915_reg_t reg);
 
+u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
+
 #define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
 #define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
 
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 791759f632e1..450ac7d343ad 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -252,14 +252,9 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
 		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
 	} else {
-		u32 rpstat = I915_READ(GEN6_RPSTAT1);
-		if (INTEL_GEN(dev_priv) >= 9)
-			ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
-		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
-			ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
-		else
-			ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
-		ret = intel_gpu_freq(dev_priv, ret);
+		ret = intel_gpu_freq(dev_priv,
+				     intel_get_cagf(dev_priv,
+						    I915_READ(GEN6_RPSTAT1)));
 	}
 	mutex_unlock(&dev_priv->pcu_lock);
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2fcff9788b6f..a06ab60847eb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9513,3 +9513,17 @@ u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
 	intel_runtime_pm_put(dev_priv);
 	return DIV_ROUND_UP_ULL(time_hw * units, div);
 }
+
+u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)
+{
+	u32 cagf;
+
+	if (INTEL_GEN(dev_priv) >= 9)
+		cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
+	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+		cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
+	else
+		cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
+
+	return  cagf;
+}
-- 
2.9.5

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  reply	other threads:[~2017-10-11 12:55 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-11 12:55 [PATCH v7 0/9] i915 PMU and engine busy stats Tvrtko Ursulin
2017-10-11 12:55 ` Tvrtko Ursulin [this message]
2017-10-11 12:55 ` [PATCH 2/9] drm/i915/pmu: Expose a PMU interface for perf queries Tvrtko Ursulin
2017-10-11 12:55 ` [PATCH 3/9] drm/i915/pmu: Suspend sampling when GPU is idle Tvrtko Ursulin
2017-10-11 12:55 ` [PATCH 4/9] drm/i915: Wrap context schedule notification Tvrtko Ursulin
2017-10-11 12:55 ` [PATCH 5/9] drm/i915: Engine busy time tracking Tvrtko Ursulin
2017-10-17 10:46   ` [PATCH v10 " Tvrtko Ursulin
2017-10-17 11:07     ` Chris Wilson
2017-10-11 12:55 ` [PATCH 6/9] drm/i915/pmu: Wire up engine busy stats to PMU Tvrtko Ursulin
2017-10-11 12:55 ` [PATCH 7/9] drm/i915/pmu: Add interrupt count metric Tvrtko Ursulin
2017-10-11 12:55 ` [PATCH 8/9] drm/i915: Convert intel_rc6_residency_us to ns Tvrtko Ursulin
2017-10-11 12:55 ` [PATCH 9/9] drm/i915/pmu: Add RC6 residency metrics Tvrtko Ursulin
2017-10-11 13:27 ` ✗ Fi.CI.BAT: failure for i915 PMU and engine busy stats (rev17) Patchwork
2017-10-17 11:12 ` ✗ Fi.CI.BAT: failure for i915 PMU and engine busy stats (rev18) Patchwork
2017-10-17 11:21   ` Chris Wilson
  -- strict thread matches above, loose matches on Subject: below --
2017-10-20  9:24 [PATCH v8 0/9] i915 PMU and engine busy stats Tvrtko Ursulin
2017-10-20  9:24 ` [PATCH 1/9] drm/i915: Extract intel_get_cagf Tvrtko Ursulin
2017-10-25  9:05 [PATCH v9 0/9] i915 PMU and engine busy stats Tvrtko Ursulin
2017-10-25  9:05 ` [PATCH 1/9] drm/i915: Extract intel_get_cagf Tvrtko Ursulin
2017-11-13  8:57 [PATCH v10 0/9] i915 PMU and engine busy stats Tvrtko Ursulin
2017-11-13  8:57 ` [PATCH 1/9] drm/i915: Extract intel_get_cagf Tvrtko Ursulin

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