From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/i915: remove g4x lowfrew_avail and has_pipe_cxsr
Date: Thu, 12 Oct 2017 19:43:34 +0300 [thread overview]
Message-ID: <20171012164334.GP10981@intel.com> (raw)
In-Reply-To: <20171012164032.30911-1-jani.nikula@intel.com>
On Thu, Oct 12, 2017 at 07:40:32PM +0300, Jani Nikula wrote:
> They're unused and unsupported. Leave the reduced_clock pointers in
> place still, should they prove useful later on.
>
> v2: go from nuking DDI lowfrew_avail to nuking it entirely (Ville)
>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 --
> drivers/gpu/drm/i915/i915_pci.c | 2 --
> drivers/gpu/drm/i915/intel_display.c | 15 ---------------
> drivers/gpu/drm/i915/intel_drv.h | 1 -
> 4 files changed, 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6bbc4b83aa0a..e655b91944b7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -785,7 +785,6 @@ struct intel_csr {
> func(has_logical_ring_contexts); \
> func(has_logical_ring_preemption); \
> func(has_overlay); \
> - func(has_pipe_cxsr); \
> func(has_pooled_eu); \
> func(has_psr); \
> func(has_rc6); \
> @@ -3168,7 +3167,6 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
>
> #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
> -#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
> #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
> #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index bf467f30c99b..c162477ad1ff 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -193,7 +193,6 @@ static const struct intel_device_info intel_i965gm_info __initconst = {
> static const struct intel_device_info intel_g45_info __initconst = {
> GEN4_FEATURES,
> .platform = INTEL_G45,
> - .has_pipe_cxsr = 1,
> .ring_mask = RENDER_RING | BSD_RING,
> };
>
> @@ -201,7 +200,6 @@ static const struct intel_device_info intel_gm45_info __initconst = {
> GEN4_FEATURES,
> .platform = INTEL_GM45,
> .is_mobile = 1, .has_fbc = 1,
> - .has_pipe_cxsr = 1,
> .supports_tv = 1,
> .ring_mask = RENDER_RING | BSD_RING,
> };
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7e91dc9a0fcf..8e5bcb7c1136 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6522,11 +6522,9 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
>
> crtc_state->dpll_hw_state.fp0 = fp;
>
> - crtc->lowfreq_avail = false;
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
> reduced_clock) {
> crtc_state->dpll_hw_state.fp1 = fp2;
> - crtc->lowfreq_avail = true;
> } else {
> crtc_state->dpll_hw_state.fp1 = fp;
> }
> @@ -7221,15 +7219,6 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
> }
> }
>
> - if (HAS_PIPE_CXSR(dev_priv)) {
> - if (intel_crtc->lowfreq_avail) {
> - DRM_DEBUG_KMS("enabling CxSR downclocking\n");
> - pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
> - } else {
> - DRM_DEBUG_KMS("disabling CxSR downclocking\n");
> - }
> - }
> -
> if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> if (INTEL_GEN(dev_priv) < 4 ||
> intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
> @@ -8365,8 +8354,6 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
> memset(&crtc_state->dpll_hw_state, 0,
> sizeof(crtc_state->dpll_hw_state));
>
> - crtc->lowfreq_avail = false;
> -
> /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
> if (!crtc_state->has_pch_encoder)
> return 0;
> @@ -9025,8 +9012,6 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> }
> }
>
> - crtc->lowfreq_avail = false;
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index b87946dcc53f..5b7db672a193 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -800,7 +800,6 @@ struct intel_crtc {
> * some outputs connected to this crtc.
> */
> bool active;
> - bool lowfreq_avail;
> u8 plane_ids_mask;
> unsigned long long enabled_power_domains;
> struct intel_overlay *overlay;
> --
> 2.11.0
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2017-10-12 16:43 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-12 16:05 [PATCH 1/4] drm/i915: remove redundant lowfreq_avail setting for DDI Jani Nikula
2017-10-12 16:05 ` [PATCH 2/4] drm/i915/crt: split compute_config hook by platforms Jani Nikula
2017-10-12 16:23 ` Ville Syrjälä
2017-10-12 16:05 ` [PATCH 3/4] drm/i915: push crtc compute clock to encoder compute config on DDI Jani Nikula
2017-10-12 16:29 ` Ville Syrjälä
2017-12-16 12:25 ` Chauhan, Madhav
2017-10-12 16:05 ` [PATCH 4/4] drm/i915: push shared dpll enable to encoders on DDI platforms Jani Nikula
2017-12-18 12:31 ` Chauhan, Madhav
2017-12-18 12:51 ` Jani Nikula
2017-12-18 13:05 ` Chauhan, Madhav
2017-12-20 11:07 ` Chauhan, Madhav
2017-10-12 16:17 ` [PATCH 1/4] drm/i915: remove redundant lowfreq_avail setting for DDI Ville Syrjälä
2017-10-12 16:30 ` ✗ Fi.CI.BAT: failure for series starting with [1/4] " Patchwork
2017-10-12 16:40 ` [PATCH v2] drm/i915: remove g4x lowfrew_avail and has_pipe_cxsr Jani Nikula
2017-10-12 16:43 ` Ville Syrjälä [this message]
2017-10-12 17:19 ` ✗ Fi.CI.BAT: failure for series starting with [v2] drm/i915: remove g4x lowfrew_avail and has_pipe_cxsr (rev2) Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20171012164334.GP10981@intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=daniel.vetter@ffwll.ch \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox