* [PATCH 1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
@ 2017-10-16 21:29 Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 2/9] drm/i915/cnl: Add Port F definition Rodrigo Vivi
` (11 more replies)
0 siblings, 12 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2017-10-16 21:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
By the Spec all CNL skus are GT2.
v2: Really include the PCI IDs to the picidlist[];
v3: Add the PCI Id for another SKU (Anusha).
v4: Update IDs, really include to pciidlists again.
v5: Unify all GT2 IDs.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 3 +--
include/drm/i915_pciids.h | 18 +++++++-----------
2 files changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 745b6a6e0188..0a51bd8ac963 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -613,8 +613,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
- INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
- INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
+ INTEL_CNL_GT2_IDS(&intel_cannonlake_gt2_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 972a25633525..3a9f307bdf98 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -392,24 +392,20 @@
INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \
INTEL_VGA_DEVICE(0x3EA5, info) /* ULT GT3 */
-/* CNL U 2+2 */
-#define INTEL_CNL_U_GT2_IDS(info) \
+/* CNL */
+#define INTEL_CNL_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x5A52, info), \
INTEL_VGA_DEVICE(0x5A5A, info), \
INTEL_VGA_DEVICE(0x5A42, info), \
- INTEL_VGA_DEVICE(0x5A4A, info)
-
-/* CNL Y 2+2 */
-#define INTEL_CNL_Y_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x5A4A, info), \
INTEL_VGA_DEVICE(0x5A51, info), \
INTEL_VGA_DEVICE(0x5A59, info), \
INTEL_VGA_DEVICE(0x5A41, info), \
INTEL_VGA_DEVICE(0x5A49, info), \
INTEL_VGA_DEVICE(0x5A71, info), \
- INTEL_VGA_DEVICE(0x5A79, info)
-
-#define INTEL_CNL_IDS(info) \
- INTEL_CNL_U_GT2_IDS(info), \
- INTEL_CNL_Y_GT2_IDS(info)
+ INTEL_VGA_DEVICE(0x5A79, info), \
+ INTEL_VGA_DEVICE(0x5A54, info), \
+ INTEL_VGA_DEVICE(0x5A5C, info), \
+ INTEL_VGA_DEVICE(0x5A44, info)
#endif /* _I915_PCIIDS_H */
--
2.13.5
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* [PATCH 2/9] drm/i915/cnl: Add Port F definition.
2017-10-16 21:29 [PATCH 1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
@ 2017-10-16 21:29 ` Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 3/9] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
` (10 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2017-10-16 21:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Some Cannonlake SKUs will come with a full split between
port A and port E. This will be called port F although it
is not a 6th port, but only a split.
v2: Fix size of dvo_ports found by Ander.
v3: Adding missing cases from intel_bios.c for Port_F
v4: Adding other missing cases and fix the commit message.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 9 +++++++++
drivers/gpu/drm/i915/intel_dp.c | 2 ++
drivers/gpu/drm/i915/intel_vbt_defs.h | 2 ++
include/drm/i915_component.h | 3 +--
5 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1fc7080bfa7b..967b9f0a3f92 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -346,6 +346,7 @@ enum port {
PORT_C,
PORT_D,
PORT_E,
+ PORT_F,
I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 3747d8df0175..5940e4a3f89f 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1128,6 +1128,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
{DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
{DVO_PORT_HDMID, DVO_PORT_DPD, -1},
{DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
+ {DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
};
/*
@@ -1670,6 +1671,7 @@ bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port por
[PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
[PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
[PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
+ [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
};
int i;
@@ -1708,6 +1710,7 @@ bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
[PORT_C] = DVO_PORT_DPC,
[PORT_D] = DVO_PORT_DPD,
[PORT_E] = DVO_PORT_DPE,
+ [PORT_F] = DVO_PORT_DPF,
};
int i;
@@ -1743,6 +1746,7 @@ static bool child_dev_is_dp_dual_mode(const struct child_device_config *child,
[PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
[PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
[PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
+ [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
};
if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
@@ -1909,6 +1913,11 @@ intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
if (port == PORT_D)
return true;
break;
+ case DVO_PORT_DPF:
+ case DVO_PORT_HDMIF:
+ if (port == PORT_F)
+ return true;
+ break;
default:
break;
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ca48bce23a6f..edc3676c0477 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1404,6 +1404,7 @@ static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
case PORT_B:
case PORT_C:
case PORT_D:
+ case PORT_F:
return DP_AUX_CH_CTL(port);
default:
MISSING_CASE(port);
@@ -1419,6 +1420,7 @@ static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
case PORT_B:
case PORT_C:
case PORT_D:
+ case PORT_F:
return DP_AUX_CH_DATA(port, index);
default:
MISSING_CASE(port);
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index 404569c9fdfc..56282d2704f8 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -299,6 +299,8 @@ struct bdb_general_features {
#define DVO_PORT_DPA 10
#define DVO_PORT_DPE 11 /* 193 */
#define DVO_PORT_HDMIE 12 /* 193 */
+#define DVO_PORT_DPF 13
+#define DVO_PORT_HDMIF 14
#define DVO_PORT_MIPIA 21 /* 171 */
#define DVO_PORT_MIPIB 22 /* 171 */
#define DVO_PORT_MIPIC 23 /* 171 */
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 545c6e0fea7d..346b1f5cb180 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -26,9 +26,8 @@
/* MAX_PORT is the number of port
* It must be sync with I915_MAX_PORTS defined i915_drv.h
- * 5 should be enough as only HSW, BDW, SKL need such fix.
*/
-#define MAX_PORTS 5
+#define MAX_PORTS 6
/**
* struct i915_audio_component_ops - Ops implemented by i915 driver, called by hda driver
--
2.13.5
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/9] drm/i915/cnl: Add AUX-F support
2017-10-16 21:29 [PATCH 1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 2/9] drm/i915/cnl: Add Port F definition Rodrigo Vivi
@ 2017-10-16 21:29 ` Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 4/9] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition Rodrigo Vivi
` (9 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2017-10-16 21:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
On some Cannonlake SKUs we have a dedicated Aux for port F,
that is only the full split between port A and port E.
There is still no Aux E for Port E, as in previous platforms,
because port_E still means shared lanes with port A.
v2: Rebase.
v3: Add couple missed PORT_F cases on intel_dp.
v4: Rebase and fix commit message.
v5: Squash Imre's "drm/i915: Add missing AUX_F power well string"
Cc: Imre Deak <imre.deak@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
drivers/gpu/drm/i915/intel_dp.c | 8 ++++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
5 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 967b9f0a3f92..ac01a3e50e4e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -397,6 +397,8 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
+ POWER_DOMAIN_AUX_F,
+
POWER_DOMAIN_GMBUS,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_INIT,
@@ -1667,6 +1669,7 @@ enum modeset_restore {
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30
+#define DP_AUX_F 0x50
#define DDC_PIN_B 0x05
#define DDC_PIN_C 0x04
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index de777139f6a1..29ad6649ac87 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2569,6 +2569,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
+ if (IS_CANNONLAKE(dev_priv))
+ tmp_mask |= CNL_AUX_CHANNEL_F;
+
if (iir & tmp_mask) {
dp_aux_irq_handler(dev_priv);
found = true;
@@ -3601,6 +3604,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
}
+ if (IS_CANNONLAKE(dev_priv))
+ de_port_masked |= CNL_AUX_CHANNEL_F;
+
de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
GEN8_PIPE_FIFO_UNDERRUN;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e7dba5539b11..a72d18f5b31e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1277,6 +1277,7 @@ enum i915_power_well_id {
CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
CNL_DISP_PW_AUX_D,
+ CNL_DISP_PW_AUX_F = 13,
SKL_DISP_PW_1 = 14,
SKL_DISP_PW_2,
@@ -5229,6 +5230,13 @@ enum {
#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
+#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
+#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
+#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
+#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
+#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
+#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
+
#define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
#define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
@@ -6880,6 +6888,7 @@ enum {
#define GEN8_DE_PORT_IMR _MMIO(0x44444)
#define GEN8_DE_PORT_IIR _MMIO(0x44448)
#define GEN8_DE_PORT_IER _MMIO(0x4444c)
+#define CNL_AUX_CHANNEL_F (1 << 28)
#define GEN9_AUX_CHANNEL_D (1 << 27)
#define GEN9_AUX_CHANNEL_C (1 << 26)
#define GEN9_AUX_CHANNEL_B (1 << 25)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index edc3676c0477..de6ebeaf1c1b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1324,6 +1324,9 @@ static enum port intel_aux_port(struct drm_i915_private *dev_priv,
case DP_AUX_D:
aux_port = PORT_D;
break;
+ case DP_AUX_F:
+ aux_port = PORT_F;
+ break;
default:
MISSING_CASE(info->alternate_aux_channel);
aux_port = PORT_A;
@@ -1343,6 +1346,7 @@ static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
case PORT_B:
case PORT_C:
case PORT_D:
+ case PORT_F:
return DP_AUX_CH_CTL(port);
default:
MISSING_CASE(port);
@@ -1357,6 +1361,7 @@ static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
case PORT_B:
case PORT_C:
case PORT_D:
+ case PORT_F:
return DP_AUX_CH_DATA(port, index);
default:
MISSING_CASE(port);
@@ -5980,6 +5985,9 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
/* FIXME: Check VBT for actual wiring of PORT E */
intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
break;
+ case PORT_F:
+ intel_dp->aux_power_domain = POWER_DOMAIN_AUX_F;
+ break;
default:
MISSING_CASE(intel_dig_port->port);
}
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 3791c3f5f56d..4091eda05ac2 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -124,6 +124,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_C";
case POWER_DOMAIN_AUX_D:
return "AUX_D";
+ case POWER_DOMAIN_AUX_F:
+ return "AUX_F";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
case POWER_DOMAIN_INIT:
@@ -1829,6 +1831,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_F) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
@@ -2378,6 +2383,12 @@ static struct i915_power_well cnl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_D,
},
+ {
+ .name = "AUX F",
+ .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = CNL_DISP_PW_AUX_F,
+ },
};
static int
--
2.13.5
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/9] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
2017-10-16 21:29 [PATCH 1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 2/9] drm/i915/cnl: Add Port F definition Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 3/9] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
@ 2017-10-16 21:29 ` Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 5/9] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F Rodrigo Vivi
` (8 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2017-10-16 21:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
This was wrong since its introduction on commit '04416108ccea
("drm/i915/cnl: Add registers related to voltage swing sequences.")'
But since no Port F was needed so far we don't need to
propagate fixes back there.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a72d18f5b31e..55295365f654 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1929,7 +1929,7 @@ enum i915_power_well_id {
#define _CNL_PORT_TX_DW2_LN0_B 0x162648
#define _CNL_PORT_TX_DW2_LN0_C 0x162C48
#define _CNL_PORT_TX_DW2_LN0_D 0x162E48
-#define _CNL_PORT_TX_DW2_LN0_F 0x162A48
+#define _CNL_PORT_TX_DW2_LN0_F 0x162848
#define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \
_CNL_PORT_TX_DW2_GRP_AE, \
_CNL_PORT_TX_DW2_GRP_B, \
--
2.13.5
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/9] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
2017-10-16 21:29 [PATCH 1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (2 preceding siblings ...)
2017-10-16 21:29 ` [PATCH 4/9] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition Rodrigo Vivi
@ 2017-10-16 21:29 ` Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 6/9] drm/i915/cnl: Enable DDI-F on Cannonlake Rodrigo Vivi
` (7 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2017-10-16 21:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Since when it got introduced with commit '555e38d27317
("drm/i915/cnl: DDI - PLL mapping")' the support for Port F
was wrong, because Port F bits are far from bits used
for A to E.
Since Port F is not used so far we don't need to propagate
Fixes back there.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55295365f654..514ba39eb433 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8606,10 +8606,14 @@ enum skl_power_gate {
* CNL Clocks
*/
#define DPCLKA_CFGCR0 _MMIO(0x6C200)
-#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)+10))
-#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << ((port)*2))
-#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port)*2)
-#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << ((port)*2))
+#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
+ (port)+10))
+#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << ((port) == PORT_F ? 21 : \
+ (port)*2))
+#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
+ (port)*2)
+#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << ((port) == PORT_F ? 21 : \
+ (port)*2))
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
--
2.13.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 6/9] drm/i915/cnl: Enable DDI-F on Cannonlake.
2017-10-16 21:29 [PATCH 1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (3 preceding siblings ...)
2017-10-16 21:29 ` [PATCH 5/9] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F Rodrigo Vivi
@ 2017-10-16 21:29 ` Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 7/9] drm/i915/cnl: Add HPD support for Port F Rodrigo Vivi
` (6 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2017-10-16 21:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Now let's finish the Port-F support by adding the
proper port F detection, irq and power well support.
v2: Rebase
v3: Use BIT_ULL
v4: Cover missed case on ddi init.
v5: Update commit message.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ddi.c | 4 ++++
drivers/gpu/drm/i915/intel_display.c | 6 +++++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +++++++++++++
5 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ac01a3e50e4e..74732af5af3c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -382,11 +382,13 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_C_LANES,
POWER_DOMAIN_PORT_DDI_D_LANES,
POWER_DOMAIN_PORT_DDI_E_LANES,
+ POWER_DOMAIN_PORT_DDI_F_LANES,
POWER_DOMAIN_PORT_DDI_A_IO,
POWER_DOMAIN_PORT_DDI_B_IO,
POWER_DOMAIN_PORT_DDI_C_IO,
POWER_DOMAIN_PORT_DDI_D_IO,
POWER_DOMAIN_PORT_DDI_E_IO,
+ POWER_DOMAIN_PORT_DDI_F_IO,
POWER_DOMAIN_PORT_DSI,
POWER_DOMAIN_PORT_CRT,
POWER_DOMAIN_PORT_OTHER,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 514ba39eb433..e9d2d225f950 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1269,6 +1269,7 @@ enum i915_power_well_id {
SKL_DISP_PW_DDI_B,
SKL_DISP_PW_DDI_C,
SKL_DISP_PW_DDI_D,
+ CNL_DISP_PW_DDI_F = 6,
GLK_DISP_PW_AUX_A = 8,
GLK_DISP_PW_AUX_B,
@@ -8709,6 +8710,7 @@ enum skl_power_gate {
#define SFUSE_STRAP_RAW_FREQUENCY (1<<8)
#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
#define SFUSE_STRAP_CRT_DISABLED (1<<6)
+#define SFUSE_STRAP_DDIF_DETECTED (1<<3)
#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
#define SFUSE_STRAP_DDID_DETECTED (1<<0)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f7c91bb9d13e..adeb71ab7eb5 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2746,6 +2746,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
intel_dig_port->ddi_io_power_domain =
POWER_DOMAIN_PORT_DDI_E_IO;
break;
+ case PORT_F:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_F_IO;
+ break;
default:
MISSING_CASE(port);
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cdb2e25a577c..afeeaebe6922 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5750,6 +5750,8 @@ enum intel_display_power_domain intel_port_to_power_domain(enum port port)
return POWER_DOMAIN_PORT_DDI_D_LANES;
case PORT_E:
return POWER_DOMAIN_PORT_DDI_E_LANES;
+ case PORT_F:
+ return POWER_DOMAIN_PORT_DDI_F_LANES;
default:
MISSING_CASE(port);
return POWER_DOMAIN_PORT_OTHER;
@@ -13686,7 +13688,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (found || IS_GEN9_BC(dev_priv))
intel_ddi_init(dev_priv, PORT_A);
- /* DDI B, C and D detection is indicated by the SFUSE_STRAP
+ /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
* register */
found = I915_READ(SFUSE_STRAP);
@@ -13696,6 +13698,8 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
intel_ddi_init(dev_priv, PORT_C);
if (found & SFUSE_STRAP_DDID_DETECTED)
intel_ddi_init(dev_priv, PORT_D);
+ if (found & SFUSE_STRAP_DDIF_DETECTED)
+ intel_ddi_init(dev_priv, PORT_F);
/*
* On SKL we don't have a way to detect DDI-E so we rely on VBT.
*/
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4091eda05ac2..6f27399162d4 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -94,6 +94,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_D_LANES";
case POWER_DOMAIN_PORT_DDI_E_LANES:
return "PORT_DDI_E_LANES";
+ case POWER_DOMAIN_PORT_DDI_F_LANES:
+ return "PORT_DDI_F_LANES";
case POWER_DOMAIN_PORT_DDI_A_IO:
return "PORT_DDI_A_IO";
case POWER_DOMAIN_PORT_DDI_B_IO:
@@ -104,6 +106,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_D_IO";
case POWER_DOMAIN_PORT_DDI_E_IO:
return "PORT_DDI_E_IO";
+ case POWER_DOMAIN_PORT_DDI_F_IO:
+ return "PORT_DDI_F_IO";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -1834,6 +1838,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_F) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
@@ -2384,6 +2391,12 @@ static struct i915_power_well cnl_power_wells[] = {
.id = SKL_DISP_PW_DDI_D,
},
{
+ .name = "DDI F IO power well",
+ .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = CNL_DISP_PW_DDI_F,
+ },
+ {
.name = "AUX F",
.domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
--
2.13.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 7/9] drm/i915/cnl: Add HPD support for Port F.
2017-10-16 21:29 [PATCH 1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (4 preceding siblings ...)
2017-10-16 21:29 ` [PATCH 6/9] drm/i915/cnl: Enable DDI-F on Cannonlake Rodrigo Vivi
@ 2017-10-16 21:29 ` Rodrigo Vivi
2017-10-17 12:28 ` Ville Syrjälä
2017-10-16 21:29 ` [PATCH 8/9] drm/i915/cnl: Add right GMBUS pin number for HDMI on " Rodrigo Vivi
` (5 subsequent siblings)
11 siblings, 1 reply; 14+ messages in thread
From: Rodrigo Vivi @ 2017-10-16 21:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
On CNP boards that are using DDI F,
bit 25 (SDE_PORTE_HOTPLUG_SPT) is representing
the Digital Port F hotplug line when the Digital
Port F hotplug detect input is enabled.
v2: Reuse all existent structure instead of adding a
new HPD_PORT_F pointing to pin of port E.
v3: Use IS_CNL_WITH_PORT_F so we can start upstreaming
this right now. If that SKU ever get a proper name
we come back and update it.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++++--
drivers/gpu/drm/i915/i915_irq.c | 35 +++++++++++++++++++----------------
drivers/gpu/drm/i915/intel_dp.c | 7 +++++--
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/intel_hotplug.c | 14 +++++++++++---
5 files changed, 41 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 74732af5af3c..4e1ce795dd2b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3007,6 +3007,8 @@ intel_info(const struct drm_i915_private *dev_priv)
(INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
(dev_priv)->info.gt == 2)
+#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
+ (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
@@ -3290,8 +3292,9 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
-enum port intel_hpd_pin_to_port(enum hpd_pin pin);
-enum hpd_pin intel_hpd_pin(enum port port);
+enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
+ enum hpd_pin pin);
+enum hpd_pin intel_hpd_pin(struct drm_i915_private *dev_priv, enum port port);
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 29ad6649ac87..6c90c3ffe30a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1556,10 +1556,11 @@ static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
*
* Note that the caller is expected to zero out the masks initially.
*/
-static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
- u32 hotplug_trigger, u32 dig_hotplug_reg,
- const u32 hpd[HPD_NUM_PINS],
- bool long_pulse_detect(enum port port, u32 val))
+static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
+ u32 *pin_mask, u32 *long_mask,
+ u32 hotplug_trigger, u32 dig_hotplug_reg,
+ const u32 hpd[HPD_NUM_PINS],
+ bool long_pulse_detect(enum port port, u32 val))
{
enum port port;
int i;
@@ -1570,7 +1571,7 @@ static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
*pin_mask |= BIT(i);
- port = intel_hpd_pin_to_port(i);
+ port = intel_hpd_pin_to_port(dev_priv, i);
if (port == PORT_NONE)
continue;
@@ -1956,8 +1957,9 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
if (hotplug_trigger) {
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
- hotplug_trigger, hpd_status_g4x,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hotplug_trigger, hotplug_trigger,
+ hpd_status_g4x,
i9xx_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -1969,8 +1971,9 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
if (hotplug_trigger) {
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
- hotplug_trigger, hpd_status_i915,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hotplug_trigger, hotplug_trigger,
+ hpd_status_i915,
i9xx_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
}
@@ -2171,7 +2174,7 @@ static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (!hotplug_trigger)
return;
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
dig_hotplug_reg, hpd,
pch_port_hotplug_long_detect);
@@ -2317,8 +2320,8 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
- dig_hotplug_reg, hpd_spt,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hotplug_trigger, dig_hotplug_reg, hpd_spt,
spt_port_hotplug_long_detect);
}
@@ -2328,8 +2331,8 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
- dig_hotplug_reg, hpd_spt,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hotplug2_trigger, dig_hotplug_reg, hpd_spt,
spt_port_hotplug2_long_detect);
}
@@ -2349,7 +2352,7 @@ static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
dig_hotplug_reg, hpd,
ilk_port_hotplug_long_detect);
@@ -2526,7 +2529,7 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
dig_hotplug_reg, hpd,
bxt_port_hotplug_long_detect);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index de6ebeaf1c1b..4d520c6b766a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4528,6 +4528,8 @@ static bool spt_digital_port_connected(struct drm_i915_private *dev_priv,
case PORT_A:
bit = SDE_PORTA_HOTPLUG_SPT;
break;
+ case PORT_F:
+ WARN_ON(!IS_CNL_WITH_PORT_F(dev_priv));
case PORT_E:
bit = SDE_PORTE_HOTPLUG_SPT;
break;
@@ -4627,7 +4629,7 @@ static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
enum port port;
u32 bit;
- port = intel_hpd_pin_to_port(intel_encoder->hpd_pin);
+ port = intel_hpd_pin_to_port(dev_priv, intel_encoder->hpd_pin);
switch (port) {
case PORT_A:
bit = BXT_DE_PORT_HP_DDIA;
@@ -5965,8 +5967,9 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
{
struct intel_encoder *encoder = &intel_dig_port->base;
struct intel_dp *intel_dp = &intel_dig_port->dp;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- encoder->hpd_pin = intel_hpd_pin(intel_dig_port->port);
+ encoder->hpd_pin = intel_hpd_pin(dev_priv, intel_dig_port->port);
switch (intel_dig_port->port) {
case PORT_A:
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index e6f8f30ce7bd..9aa63cfb7fe0 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2022,7 +2022,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
if (WARN_ON(port == PORT_A))
return;
- intel_encoder->hpd_pin = intel_hpd_pin(port);
+ intel_encoder->hpd_pin = intel_hpd_pin(dev_priv, port);
if (HAS_DDI(dev_priv))
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index 875d5d218d5c..dfc64e135069 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -78,12 +78,14 @@
/**
* intel_hpd_port - return port hard associated with certain pin.
+ * @dev_priv: private driver data pointer
* @pin: the hpd pin to get associated port
*
* Return port that is associatade with @pin and PORT_NONE if no port is
* hard associated with that @pin.
*/
-enum port intel_hpd_pin_to_port(enum hpd_pin pin)
+enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
+ enum hpd_pin pin)
{
switch (pin) {
case HPD_PORT_A:
@@ -95,6 +97,8 @@ enum port intel_hpd_pin_to_port(enum hpd_pin pin)
case HPD_PORT_D:
return PORT_D;
case HPD_PORT_E:
+ if (IS_CNL_WITH_PORT_F(dev_priv))
+ return PORT_F;
return PORT_E;
default:
return PORT_NONE; /* no port for this pin */
@@ -103,12 +107,13 @@ enum port intel_hpd_pin_to_port(enum hpd_pin pin)
/**
* intel_hpd_pin - return pin hard associated with certain port.
+ * @dev_priv: private driver data pointer
* @port: the hpd port to get associated pin
*
* Return pin that is associatade with @port and HDP_NONE if no pin is
* hard associated with that @port.
*/
-enum hpd_pin intel_hpd_pin(enum port port)
+enum hpd_pin intel_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
{
switch (port) {
case PORT_A:
@@ -121,6 +126,9 @@ enum hpd_pin intel_hpd_pin(enum port port)
return HPD_PORT_D;
case PORT_E:
return HPD_PORT_E;
+ case PORT_F:
+ if (IS_CNL_WITH_PORT_F(dev_priv))
+ return HPD_PORT_E;
default:
MISSING_CASE(port);
return HPD_NONE;
@@ -417,7 +425,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (!(BIT(i) & pin_mask))
continue;
- port = intel_hpd_pin_to_port(i);
+ port = intel_hpd_pin_to_port(dev_priv, i);
is_dig_port = port != PORT_NONE &&
dev_priv->hotplug.irq_port[port];
--
2.13.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 8/9] drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.
2017-10-16 21:29 [PATCH 1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (5 preceding siblings ...)
2017-10-16 21:29 ` [PATCH 7/9] drm/i915/cnl: Add HPD support for Port F Rodrigo Vivi
@ 2017-10-16 21:29 ` Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 9/9] drm/i915/cnl: Fix DP max rate for Cannonlake with port F Rodrigo Vivi
` (4 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2017-10-16 21:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
On CNP Pin 3 is for misc of Port F usage depending on the
configuration. For CNL that uses Port F, pin 3 is the one.
v2: Make it more generic and update commit message.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 9aa63cfb7fe0..944c793cd4a1 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1902,6 +1902,9 @@ static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
case PORT_D:
ddc_pin = GMBUS_PIN_4_CNP;
break;
+ case PORT_F:
+ ddc_pin = GMBUS_PIN_3_BXT;
+ break;
default:
MISSING_CASE(port);
ddc_pin = GMBUS_PIN_1_BXT;
--
2.13.5
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 9/9] drm/i915/cnl: Fix DP max rate for Cannonlake with port F.
2017-10-16 21:29 [PATCH 1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (6 preceding siblings ...)
2017-10-16 21:29 ` [PATCH 8/9] drm/i915/cnl: Add right GMBUS pin number for HDMI on " Rodrigo Vivi
@ 2017-10-16 21:29 ` Rodrigo Vivi
2017-10-16 21:32 ` ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2017-10-16 21:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
On CNL SKUs that uses port F, max DP rate is 8.1G for all
ports when we have the elevated voltage.
v2: Make commit message more generic.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4d520c6b766a..eced3281cb2f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -248,8 +248,9 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
source_rates = cnl_rates;
size = ARRAY_SIZE(cnl_rates);
voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
- if (port == PORT_A || port == PORT_D ||
- voltage == VOLTAGE_INFO_0_85V)
+ if (voltage == VOLTAGE_INFO_0_85V ||
+ (!IS_CNL_WITH_PORT_F(dev_priv) && (port == PORT_A ||
+ port == PORT_D)))
size -= 2;
} else if (IS_GEN9_BC(dev_priv)) {
source_rates = skl_rates;
--
2.13.5
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
2017-10-16 21:29 [PATCH 1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (7 preceding siblings ...)
2017-10-16 21:29 ` [PATCH 9/9] drm/i915/cnl: Fix DP max rate for Cannonlake with port F Rodrigo Vivi
@ 2017-10-16 21:32 ` Patchwork
2017-10-17 0:26 ` [PATCH] " Rodrigo Vivi
` (2 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2017-10-16 21:32 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
URL : https://patchwork.freedesktop.org/series/32069/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CHK include/generated/bounds.h
CHK include/generated/timeconst.h
CHK include/generated/asm-offsets.h
CALL scripts/checksyscalls.sh
CHK scripts/mod/devicetable-offsets.h
CHK include/generated/compile.h
CC arch/x86/kernel/early-quirks.o
arch/x86/kernel/early-quirks.c:530:2: error: implicit declaration of function ‘INTEL_CNL_IDS’ [-Werror=implicit-function-declaration]
INTEL_CNL_IDS(&gen9_early_ops),
^~~~~~~~~~~~~
arch/x86/kernel/early-quirks.c:530:2: error: initializer element is not constant
arch/x86/kernel/early-quirks.c:530:2: note: (near initialization for ‘intel_early_ids[187].vendor’)
arch/x86/kernel/early-quirks.c:501:67: warning: missing braces around initializer [-Wmissing-braces]
static const struct pci_device_id intel_early_ids[] __initconst = {
^
arch/x86/kernel/early-quirks.c:501:67: note: (near initialization for ‘intel_early_ids’)
cc1: some warnings being treated as errors
scripts/Makefile.build:313: recipe for target 'arch/x86/kernel/early-quirks.o' failed
make[2]: *** [arch/x86/kernel/early-quirks.o] Error 1
scripts/Makefile.build:572: recipe for target 'arch/x86/kernel' failed
make[1]: *** [arch/x86/kernel] Error 2
Makefile:1023: recipe for target 'arch/x86' failed
make: *** [arch/x86] Error 2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
2017-10-16 21:29 [PATCH 1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (8 preceding siblings ...)
2017-10-16 21:32 ` ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Patchwork
@ 2017-10-17 0:26 ` Rodrigo Vivi
2017-10-17 1:20 ` ✓ Fi.CI.BAT: success for series starting with drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev2) Patchwork
2017-10-17 17:20 ` ✓ Fi.CI.IGT: " Patchwork
11 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2017-10-17 0:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
By the Spec all CNL skus are GT2.
v2: Really include the PCI IDs to the picidlist[];
v3: Add the PCI Id for another SKU (Anusha).
v4: Update IDs, really include to pciidlists again.
v5: Unify all GT2 IDs.
v6: Prefer INTEL_CNL_IDS for the union since it is already
in use at arch/x86/kernel/early-quirks.c.
Bit thanks to CI.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 3 +--
include/drm/i915_pciids.h | 18 +++++++-----------
2 files changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index bf467f30c99b..95ec2b302703 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -634,8 +634,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
- INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
- INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
+ INTEL_CNL_IDS(&intel_cannonlake_gt2_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 972a25633525..d338d612ba45 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -392,24 +392,20 @@
INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \
INTEL_VGA_DEVICE(0x3EA5, info) /* ULT GT3 */
-/* CNL U 2+2 */
-#define INTEL_CNL_U_GT2_IDS(info) \
+/* CNL */
+#define INTEL_CNL_IDS(info) \
INTEL_VGA_DEVICE(0x5A52, info), \
INTEL_VGA_DEVICE(0x5A5A, info), \
INTEL_VGA_DEVICE(0x5A42, info), \
- INTEL_VGA_DEVICE(0x5A4A, info)
-
-/* CNL Y 2+2 */
-#define INTEL_CNL_Y_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x5A4A, info), \
INTEL_VGA_DEVICE(0x5A51, info), \
INTEL_VGA_DEVICE(0x5A59, info), \
INTEL_VGA_DEVICE(0x5A41, info), \
INTEL_VGA_DEVICE(0x5A49, info), \
INTEL_VGA_DEVICE(0x5A71, info), \
- INTEL_VGA_DEVICE(0x5A79, info)
-
-#define INTEL_CNL_IDS(info) \
- INTEL_CNL_U_GT2_IDS(info), \
- INTEL_CNL_Y_GT2_IDS(info)
+ INTEL_VGA_DEVICE(0x5A79, info), \
+ INTEL_VGA_DEVICE(0x5A54, info), \
+ INTEL_VGA_DEVICE(0x5A5C, info), \
+ INTEL_VGA_DEVICE(0x5A44, info)
#endif /* _I915_PCIIDS_H */
--
2.13.5
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev2)
2017-10-16 21:29 [PATCH 1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (9 preceding siblings ...)
2017-10-17 0:26 ` [PATCH] " Rodrigo Vivi
@ 2017-10-17 1:20 ` Patchwork
2017-10-17 17:20 ` ✓ Fi.CI.IGT: " Patchwork
11 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2017-10-17 1:20 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev2)
URL : https://patchwork.freedesktop.org/series/32069/
State : success
== Summary ==
Series 32069v2 series starting with drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
https://patchwork.freedesktop.org/api/1.0/series/32069/revisions/2/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> FAIL (fi-skl-6700k) fdo#100367
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (fi-byt-n2820) fdo#101705
fdo#100367 https://bugs.freedesktop.org/show_bug.cgi?id=100367
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:437s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:448s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:369s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:523s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:261s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:500s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:495s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:497s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:481s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:419s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:249s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:577s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:433s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:432s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:487s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:458s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:481s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:568s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:473s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:585s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:544s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:447s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:647s
fi-skl-6700k total:289 pass:264 dwarn:0 dfail:0 fail:1 skip:24 time:515s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:491s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:459s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:560s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:423s
ba1af442e4884a1148422a7f92ae2f978cfb26a1 drm-tip: 2017y-10m-17d-00h-18m-03s UTC integration manifest
8845100bfcba drm/i915/cnl: Fix DP max rate for Cannonlake with port F.
6c688f0c0066 drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.
4b473a8272b6 drm/i915/cnl: Add HPD support for Port F.
9050d0c3240c drm/i915/cnl: Enable DDI-F on Cannonlake.
2cebb6f10d73 drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
50f947ba7409 drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
0ff3585f62a6 drm/i915/cnl: Add AUX-F support
803bf87149ba drm/i915/cnl: Add Port F definition.
b840c8228320 drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6061/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 7/9] drm/i915/cnl: Add HPD support for Port F.
2017-10-16 21:29 ` [PATCH 7/9] drm/i915/cnl: Add HPD support for Port F Rodrigo Vivi
@ 2017-10-17 12:28 ` Ville Syrjälä
0 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2017-10-17 12:28 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Dhinakaran Pandiyan
On Mon, Oct 16, 2017 at 02:29:37PM -0700, Rodrigo Vivi wrote:
> On CNP boards that are using DDI F,
> bit 25 (SDE_PORTE_HOTPLUG_SPT) is representing
> the Digital Port F hotplug line when the Digital
> Port F hotplug detect input is enabled.
>
> v2: Reuse all existent structure instead of adding a
> new HPD_PORT_F pointing to pin of port E.
> v3: Use IS_CNL_WITH_PORT_F so we can start upstreaming
> this right now. If that SKU ever get a proper name
> we come back and update it.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 7 +++++--
> drivers/gpu/drm/i915/i915_irq.c | 35 +++++++++++++++++++----------------
> drivers/gpu/drm/i915/intel_dp.c | 7 +++++--
> drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> drivers/gpu/drm/i915/intel_hotplug.c | 14 +++++++++++---
> 5 files changed, 41 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 74732af5af3c..4e1ce795dd2b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3007,6 +3007,8 @@ intel_info(const struct drm_i915_private *dev_priv)
> (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
> #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> (dev_priv)->info.gt == 2)
> +#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
> + (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
>
> #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
>
> @@ -3290,8 +3292,9 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
> void intel_hpd_init(struct drm_i915_private *dev_priv);
> void intel_hpd_init_work(struct drm_i915_private *dev_priv);
> void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
> -enum port intel_hpd_pin_to_port(enum hpd_pin pin);
> -enum hpd_pin intel_hpd_pin(enum port port);
> +enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
> + enum hpd_pin pin);
> +enum hpd_pin intel_hpd_pin(struct drm_i915_private *dev_priv, enum port port);
> bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
> void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 29ad6649ac87..6c90c3ffe30a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1556,10 +1556,11 @@ static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
> *
> * Note that the caller is expected to zero out the masks initially.
> */
> -static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
> - u32 hotplug_trigger, u32 dig_hotplug_reg,
> - const u32 hpd[HPD_NUM_PINS],
> - bool long_pulse_detect(enum port port, u32 val))
> +static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
> + u32 *pin_mask, u32 *long_mask,
> + u32 hotplug_trigger, u32 dig_hotplug_reg,
> + const u32 hpd[HPD_NUM_PINS],
> + bool long_pulse_detect(enum port port, u32 val))
> {
> enum port port;
> int i;
> @@ -1570,7 +1571,7 @@ static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
>
> *pin_mask |= BIT(i);
>
> - port = intel_hpd_pin_to_port(i);
> + port = intel_hpd_pin_to_port(dev_priv, i);
> if (port == PORT_NONE)
> continue;
>
> @@ -1956,8 +1957,9 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
> u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
>
> if (hotplug_trigger) {
> - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> - hotplug_trigger, hpd_status_g4x,
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + hotplug_trigger, hotplug_trigger,
> + hpd_status_g4x,
> i9xx_port_hotplug_long_detect);
>
> intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> @@ -1969,8 +1971,9 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
> u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
>
> if (hotplug_trigger) {
> - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> - hotplug_trigger, hpd_status_i915,
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + hotplug_trigger, hotplug_trigger,
> + hpd_status_i915,
> i9xx_port_hotplug_long_detect);
> intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> }
> @@ -2171,7 +2174,7 @@ static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
> if (!hotplug_trigger)
> return;
>
> - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
> dig_hotplug_reg, hpd,
> pch_port_hotplug_long_detect);
>
> @@ -2317,8 +2320,8 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
> I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
>
> - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> - dig_hotplug_reg, hpd_spt,
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + hotplug_trigger, dig_hotplug_reg, hpd_spt,
> spt_port_hotplug_long_detect);
> }
>
> @@ -2328,8 +2331,8 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
> I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
>
> - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
> - dig_hotplug_reg, hpd_spt,
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + hotplug2_trigger, dig_hotplug_reg, hpd_spt,
> spt_port_hotplug2_long_detect);
> }
>
> @@ -2349,7 +2352,7 @@ static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
> dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
> I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
>
> - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
> dig_hotplug_reg, hpd,
> ilk_port_hotplug_long_detect);
>
> @@ -2526,7 +2529,7 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
> dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
> I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
>
> - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
> dig_hotplug_reg, hpd,
> bxt_port_hotplug_long_detect);
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index de6ebeaf1c1b..4d520c6b766a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4528,6 +4528,8 @@ static bool spt_digital_port_connected(struct drm_i915_private *dev_priv,
> case PORT_A:
> bit = SDE_PORTA_HOTPLUG_SPT;
> break;
> + case PORT_F:
> + WARN_ON(!IS_CNL_WITH_PORT_F(dev_priv));
I'd like to see these functions to be changed to just look at
encoder->hpd_pin instead of ->port.
And while at it you could just as well change them to take
'struct intel_encoder *encoder' directly instead of passing
in dev_priv+dig_port.
> case PORT_E:
> bit = SDE_PORTE_HOTPLUG_SPT;
> break;
> @@ -4627,7 +4629,7 @@ static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
> enum port port;
> u32 bit;
>
> - port = intel_hpd_pin_to_port(intel_encoder->hpd_pin);
> + port = intel_hpd_pin_to_port(dev_priv, intel_encoder->hpd_pin);
> switch (port) {
> case PORT_A:
> bit = BXT_DE_PORT_HP_DDIA;
> @@ -5965,8 +5967,9 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
> {
> struct intel_encoder *encoder = &intel_dig_port->base;
> struct intel_dp *intel_dp = &intel_dig_port->dp;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - encoder->hpd_pin = intel_hpd_pin(intel_dig_port->port);
> + encoder->hpd_pin = intel_hpd_pin(dev_priv, intel_dig_port->port);
>
> switch (intel_dig_port->port) {
> case PORT_A:
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index e6f8f30ce7bd..9aa63cfb7fe0 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -2022,7 +2022,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>
> if (WARN_ON(port == PORT_A))
> return;
> - intel_encoder->hpd_pin = intel_hpd_pin(port);
> + intel_encoder->hpd_pin = intel_hpd_pin(dev_priv, port);
>
> if (HAS_DDI(dev_priv))
> intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
> index 875d5d218d5c..dfc64e135069 100644
> --- a/drivers/gpu/drm/i915/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/intel_hotplug.c
> @@ -78,12 +78,14 @@
>
> /**
> * intel_hpd_port - return port hard associated with certain pin.
> + * @dev_priv: private driver data pointer
> * @pin: the hpd pin to get associated port
> *
> * Return port that is associatade with @pin and PORT_NONE if no port is
> * hard associated with that @pin.
> */
> -enum port intel_hpd_pin_to_port(enum hpd_pin pin)
> +enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
> + enum hpd_pin pin)
> {
> switch (pin) {
> case HPD_PORT_A:
> @@ -95,6 +97,8 @@ enum port intel_hpd_pin_to_port(enum hpd_pin pin)
> case HPD_PORT_D:
> return PORT_D;
> case HPD_PORT_E:
> + if (IS_CNL_WITH_PORT_F(dev_priv))
> + return PORT_F;
I think we'll just want to replace this whole switch with something like
for_each_intel_encoder() {
if (encoder->hdp_pin == pin)
return encoder->port;
}
That will make it work with any port<->hpd_pin mapping in the future.
> return PORT_E;
> default:
> return PORT_NONE; /* no port for this pin */
> @@ -103,12 +107,13 @@ enum port intel_hpd_pin_to_port(enum hpd_pin pin)
>
> /**
> * intel_hpd_pin - return pin hard associated with certain port.
> + * @dev_priv: private driver data pointer
> * @port: the hpd port to get associated pin
> *
> * Return pin that is associatade with @port and HDP_NONE if no pin is
> * hard associated with that @port.
> */
> -enum hpd_pin intel_hpd_pin(enum port port)
> +enum hpd_pin intel_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
We should probably rename this function to be something
intel_default_hpd_pin() to reflect the fact this is just
our default port->hpd_pin mapping. Maybe we should also put
dig_port or something to the name since this doesn't apply to
other encoder types.
Hmm. I thought VBT would provide us with the hpd pin as well, but
now I don't see anything like that. Maybe I was mistaken? I guess
that might happen at some point anyway, so I think the renaming
would still make things a bit less confusing.
> {
> switch (port) {
> case PORT_A:
> @@ -121,6 +126,9 @@ enum hpd_pin intel_hpd_pin(enum port port)
> return HPD_PORT_D;
> case PORT_E:
> return HPD_PORT_E;
> + case PORT_F:
> + if (IS_CNL_WITH_PORT_F(dev_priv))
> + return HPD_PORT_E;
> default:
> MISSING_CASE(port);
> return HPD_NONE;
> @@ -417,7 +425,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
> if (!(BIT(i) & pin_mask))
> continue;
>
> - port = intel_hpd_pin_to_port(i);
> + port = intel_hpd_pin_to_port(dev_priv, i);
> is_dig_port = port != PORT_NONE &&
> dev_priv->hotplug.irq_port[port];
>
> --
> 2.13.5
--
Ville Syrjälä
Intel OTC
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev2)
2017-10-16 21:29 [PATCH 1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (10 preceding siblings ...)
2017-10-17 1:20 ` ✓ Fi.CI.BAT: success for series starting with drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev2) Patchwork
@ 2017-10-17 17:20 ` Patchwork
11 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2017-10-17 17:20 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev2)
URL : https://patchwork.freedesktop.org/series/32069/
State : success
== Summary ==
Test gem_sync:
Subgroup basic-many-each:
fail -> PASS (shard-hsw) fdo#100007
Test kms_cursor_legacy:
Subgroup flip-vs-cursor-atomic:
pass -> FAIL (shard-hsw) fdo#102670
fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
shard-hsw total:2553 pass:1439 dwarn:0 dfail:0 fail:11 skip:1103 time:9292s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6061/shards.html
_______________________________________________
Intel-gfx mailing list
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2017-10-17 17:20 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-10-16 21:29 [PATCH 1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 2/9] drm/i915/cnl: Add Port F definition Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 3/9] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 4/9] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 5/9] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 6/9] drm/i915/cnl: Enable DDI-F on Cannonlake Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 7/9] drm/i915/cnl: Add HPD support for Port F Rodrigo Vivi
2017-10-17 12:28 ` Ville Syrjälä
2017-10-16 21:29 ` [PATCH 8/9] drm/i915/cnl: Add right GMBUS pin number for HDMI on " Rodrigo Vivi
2017-10-16 21:29 ` [PATCH 9/9] drm/i915/cnl: Fix DP max rate for Cannonlake with port F Rodrigo Vivi
2017-10-16 21:32 ` ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Patchwork
2017-10-17 0:26 ` [PATCH] " Rodrigo Vivi
2017-10-17 1:20 ` ✓ Fi.CI.BAT: success for series starting with drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev2) Patchwork
2017-10-17 17:20 ` ✓ Fi.CI.IGT: " Patchwork
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