[PATCH 1/5] drm/i915: move adjusted_x/y from crtc to cache.

[PATCH 1/5] drm/i915: move adjusted_x/y from crtc to cache.

[Juha-Pekka Heikkila]

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  8 ++++++++
 drivers/gpu/drm/i915/intel_display.c | 10 ++++++----
 drivers/gpu/drm/i915/intel_drv.h     |  2 --
 drivers/gpu/drm/i915/intel_fbc.c     | 11 ++++++++---
 4 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6d7d871..17960ba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1095,6 +1095,14 @@ struct intel_fbc {
 			int src_w;
 			int src_h;
 			bool visible;
+			/*
+			 * Display surface base address adjustement for
+			 * pageflips. Note that on gen4+ this only adjusts up
+			 * to a tile, offsets within a tile are handled in
+			 * the hw itself (with the TILEOFF register).
+			 */
+			int adjusted_x;
+			int adjusted_y;
 		} plane;
 
 		struct {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8599e42..92e8370 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3307,6 +3307,7 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	int x = plane_state->main.x;
 	int y = plane_state->main.y;
 	unsigned long irqflags;
+	struct intel_fbc *fbc = &dev_priv->fbc;
 
 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
@@ -3315,8 +3316,8 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	else
 		crtc->dspaddr_offset = linear_offset;
 
-	crtc->adjusted_x = x;
-	crtc->adjusted_y = y;
+	fbc->state_cache.plane.adjusted_x = x;
+	fbc->state_cache.plane.adjusted_y = y;
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
@@ -3577,6 +3578,7 @@ static void skylake_update_primary_plane(struct intel_plane *plane,
 	int dst_w = drm_rect_width(&plane_state->base.dst);
 	int dst_h = drm_rect_height(&plane_state->base.dst);
 	unsigned long irqflags;
+	struct intel_fbc *fbc = &dev_priv->fbc;
 
 	/* Sizes are 0 based */
 	src_w--;
@@ -3586,8 +3588,8 @@ static void skylake_update_primary_plane(struct intel_plane *plane,
 
 	crtc->dspaddr_offset = surf_addr;
 
-	crtc->adjusted_x = src_x;
-	crtc->adjusted_y = src_y;
+	fbc->state_cache.plane.adjusted_x = src_x;
+	fbc->state_cache.plane.adjusted_y = src_y;
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3078076..62aada7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -807,8 +807,6 @@ struct intel_crtc {
 	 * gen4+ this only adjusts up to a tile, offsets within a tile are
 	 * handled in the hw itself (with the TILEOFF register). */
 	u32 dspaddr_offset;
-	int adjusted_x;
-	int adjusted_y;
 
 	struct intel_crtc_state *config;
 
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 58a772d..dc059808 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -71,7 +71,10 @@ static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  */
 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
 {
-	return crtc->base.y - crtc->adjusted_y;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_fbc *fbc = &dev_priv->fbc;
+
+	return crtc->base.y - fbc->state_cache.plane.adjusted_y;
 }
 
 /*
@@ -727,8 +730,8 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 
 	intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 					&effective_h);
-	effective_w += crtc->adjusted_x;
-	effective_h += crtc->adjusted_y;
+	effective_w += fbc->state_cache.plane.adjusted_x;
+	effective_h += fbc->state_cache.plane.adjusted_y;
 
 	return effective_w <= max_w && effective_h <= max_h;
 }
@@ -757,6 +760,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 	cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 	cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 	cache->plane.visible = plane_state->base.visible;
+	cache->plane.adjusted_x = plane_state->main.x;
+	cache->plane.adjusted_y = plane_state->main.y;
 
 	if (!cache->plane.visible)
 		return;
-- 
2.7.4

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Re: [PATCH 1/5] drm/i915: move adjusted_x/y from crtc to cache.

[Ville Syrjälä]

On Tue, Sep 19, 2017 at 10:44:05PM +0300, Juha-Pekka Heikkila wrote:
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  8 ++++++++
>  drivers/gpu/drm/i915/intel_display.c | 10 ++++++----
>  drivers/gpu/drm/i915/intel_drv.h     |  2 --
>  drivers/gpu/drm/i915/intel_fbc.c     | 11 ++++++++---
>  4 files changed, 22 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6d7d871..17960ba 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1095,6 +1095,14 @@ struct intel_fbc {
>  			int src_w;
>  			int src_h;
>  			bool visible;
> +			/*
> +			 * Display surface base address adjustement for
> +			 * pageflips. Note that on gen4+ this only adjusts up
> +			 * to a tile, offsets within a tile are handled in
> +			 * the hw itself (with the TILEOFF register).
> +			 */
> +			int adjusted_x;
> +			int adjusted_y;
>  		} plane;
>  
>  		struct {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 8599e42..92e8370 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3307,6 +3307,7 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
>  	int x = plane_state->main.x;
>  	int y = plane_state->main.y;
>  	unsigned long irqflags;
> +	struct intel_fbc *fbc = &dev_priv->fbc;
>  
>  	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>  
> @@ -3315,8 +3316,8 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
>  	else
>  		crtc->dspaddr_offset = linear_offset;
>  
> -	crtc->adjusted_x = x;
> -	crtc->adjusted_y = y;
> +	fbc->state_cache.plane.adjusted_x = x;
> +	fbc->state_cache.plane.adjusted_y = y;

This shouldn't be here. Just doing the update in
intel_fbc_update_state_cache() should be good enough.

>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> @@ -3577,6 +3578,7 @@ static void skylake_update_primary_plane(struct intel_plane *plane,
>  	int dst_w = drm_rect_width(&plane_state->base.dst);
>  	int dst_h = drm_rect_height(&plane_state->base.dst);
>  	unsigned long irqflags;
> +	struct intel_fbc *fbc = &dev_priv->fbc;
>  
>  	/* Sizes are 0 based */
>  	src_w--;
> @@ -3586,8 +3588,8 @@ static void skylake_update_primary_plane(struct intel_plane *plane,
>  
>  	crtc->dspaddr_offset = surf_addr;
>  
> -	crtc->adjusted_x = src_x;
> -	crtc->adjusted_y = src_y;
> +	fbc->state_cache.plane.adjusted_x = src_x;
> +	fbc->state_cache.plane.adjusted_y = src_y;

ditto

>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 3078076..62aada7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -807,8 +807,6 @@ struct intel_crtc {
>  	 * gen4+ this only adjusts up to a tile, offsets within a tile are
>  	 * handled in the hw itself (with the TILEOFF register). */
>  	u32 dspaddr_offset;
> -	int adjusted_x;
> -	int adjusted_y;
>  
>  	struct intel_crtc_state *config;
>  
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 58a772d..dc059808 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -71,7 +71,10 @@ static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
>   */
>  static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
>  {
> -	return crtc->base.y - crtc->adjusted_y;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct intel_fbc *fbc = &dev_priv->fbc;
> +
> +	return crtc->base.y - fbc->state_cache.plane.adjusted_y;
>  }
>  
>  /*
> @@ -727,8 +730,8 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
>  
>  	intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
>  					&effective_h);
> -	effective_w += crtc->adjusted_x;
> -	effective_h += crtc->adjusted_y;
> +	effective_w += fbc->state_cache.plane.adjusted_x;
> +	effective_h += fbc->state_cache.plane.adjusted_y;
>  
>  	return effective_w <= max_w && effective_h <= max_h;
>  }
> @@ -757,6 +760,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
>  	cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
>  	cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
>  	cache->plane.visible = plane_state->base.visible;
> +	cache->plane.adjusted_x = plane_state->main.x;
> +	cache->plane.adjusted_y = plane_state->main.y;
>  
>  	if (!cache->plane.visible)
>  		return;
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[PATCH 0/5] drm/i915: Skylake plane update/disable unifications [v6]

[Juha-Pekka Heikkila]

[v6] small adjustments and rebase (ville syrjälä)

[v5] use clipped y coordinate at get_crtc_fence_y_offset() (ville syrjälä)

[v4] rebase

[v3] Took into account fbc adjusted y/x for primary plane (ville syrjälä)

[v2] Fixed missed references which were brough on rebase.

/Juha-Pekka

Juha-Pekka Heikkila (5):
  drm/i915: move adjusted_x/y from crtc to cache.
  drm/i915: dspaddr_offset doesn't need to be more than local variable
  drm/i915: Unify skylake plane update
  drm/i915: Unify skylake plane disable
  drm/i915: adjust get_crtc_fence_y_offset() to use base.y instead of
    crtc.y

 drivers/gpu/drm/i915/i915_drv.h      |  10 +++
 drivers/gpu/drm/i915/intel_display.c | 117 +++--------------------------------
 drivers/gpu/drm/i915/intel_drv.h     |  11 ++--
 drivers/gpu/drm/i915/intel_fbc.c     |  13 ++--
 drivers/gpu/drm/i915/intel_sprite.c  |   4 +-
 5 files changed, 34 insertions(+), 121 deletions(-)

-- 
2.7.4

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[PATCH 1/5] drm/i915: move adjusted_x/y from crtc to cache.

[Juha-Pekka Heikkila]

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  8 ++++++++
 drivers/gpu/drm/i915/intel_display.c |  6 ------
 drivers/gpu/drm/i915/intel_drv.h     |  2 --
 drivers/gpu/drm/i915/intel_fbc.c     | 11 ++++++++---
 4 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dd141b2..93046b0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1108,6 +1108,14 @@ struct intel_fbc {
 			int src_w;
 			int src_h;
 			bool visible;
+			/*
+			 * Display surface base address adjustement for
+			 * pageflips. Note that on gen4+ this only adjusts up
+			 * to a tile, offsets within a tile are handled in
+			 * the hw itself (with the TILEOFF register).
+			 */
+			int adjusted_x;
+			int adjusted_y;
 		} plane;
 
 		struct {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 17a9a57..ccbc7ff 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3306,9 +3306,6 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	else
 		crtc->dspaddr_offset = linear_offset;
 
-	crtc->adjusted_x = x;
-	crtc->adjusted_y = y;
-
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
 	if (INTEL_GEN(dev_priv) < 4) {
@@ -3577,9 +3574,6 @@ static void skylake_update_primary_plane(struct intel_plane *plane,
 
 	crtc->dspaddr_offset = surf_addr;
 
-	crtc->adjusted_x = src_x;
-	crtc->adjusted_y = src_y;
-
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
 	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8296df5..298986f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -812,8 +812,6 @@ struct intel_crtc {
 	 * gen4+ this only adjusts up to a tile, offsets within a tile are
 	 * handled in the hw itself (with the TILEOFF register). */
 	u32 dspaddr_offset;
-	int adjusted_x;
-	int adjusted_y;
 
 	struct intel_crtc_state *config;
 
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 8e3a055..0ee65be 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -71,7 +71,10 @@ static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  */
 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
 {
-	return crtc->base.y - crtc->adjusted_y;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_fbc *fbc = &dev_priv->fbc;
+
+	return crtc->base.y - fbc->state_cache.plane.adjusted_y;
 }
 
 /*
@@ -727,8 +730,8 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 
 	intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 					&effective_h);
-	effective_w += crtc->adjusted_x;
-	effective_h += crtc->adjusted_y;
+	effective_w += fbc->state_cache.plane.adjusted_x;
+	effective_h += fbc->state_cache.plane.adjusted_y;
 
 	return effective_w <= max_w && effective_h <= max_h;
 }
@@ -757,6 +760,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 	cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 	cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 	cache->plane.visible = plane_state->base.visible;
+	cache->plane.adjusted_x = plane_state->main.x;
+	cache->plane.adjusted_y = plane_state->main.y;
 
 	if (!cache->plane.visible)
 		return;
-- 
2.7.4

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[PATCH 2/5] drm/i915: dspaddr_offset doesn't need to be more than local variable

[Juha-Pekka Heikkila]

Move u32 dspaddr_offset from struct intel_crtc member into local
variable in i9xx_update_primary_plane()

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 15 ++++++---------
 drivers/gpu/drm/i915/intel_drv.h     |  5 -----
 2 files changed, 6 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ccbc7ff..d468adb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3289,7 +3289,6 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 				      const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	enum plane plane = primary->plane;
 	u32 linear_offset;
@@ -3298,13 +3297,14 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	int x = plane_state->main.x;
 	int y = plane_state->main.y;
 	unsigned long irqflags;
+	u32 dspaddr_offset;
 
 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
 	if (INTEL_GEN(dev_priv) >= 4)
-		crtc->dspaddr_offset = plane_state->main.offset;
+		dspaddr_offset = plane_state->main.offset;
 	else
-		crtc->dspaddr_offset = linear_offset;
+		dspaddr_offset = linear_offset;
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
@@ -3330,18 +3330,18 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		I915_WRITE_FW(DSPSURF(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
 	} else if (INTEL_GEN(dev_priv) >= 4) {
 		I915_WRITE_FW(DSPSURF(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 		I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
 		I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
 	} else {
 		I915_WRITE_FW(DSPADDR(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 	}
 	POSTING_READ_FW(reg);
 
@@ -3546,7 +3546,6 @@ static void skylake_update_primary_plane(struct intel_plane *plane,
 					 const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	enum plane_id plane_id = plane->id;
 	enum pipe pipe = plane->pipe;
@@ -3572,8 +3571,6 @@ static void skylake_update_primary_plane(struct intel_plane *plane,
 	dst_w--;
 	dst_h--;
 
-	crtc->dspaddr_offset = surf_addr;
-
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
 	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 298986f..36133e4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -808,11 +808,6 @@ struct intel_crtc {
 	unsigned long long enabled_power_domains;
 	struct intel_overlay *overlay;
 
-	/* Display surface base address adjustement for pageflips. Note that on
-	 * gen4+ this only adjusts up to a tile, offsets within a tile are
-	 * handled in the hw itself (with the TILEOFF register). */
-	u32 dspaddr_offset;
-
 	struct intel_crtc_state *config;
 
 	/* global reset count when the last flip was submitted */
-- 
2.7.4

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[PATCH 3/5] drm/i915: Unify skylake plane update

[Juha-Pekka Heikkila]

Don't handle skylake primary plane separately as it is similar
plane as the others.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 75 +-----------------------------------
 drivers/gpu/drm/i915/intel_drv.h     |  3 ++
 drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
 3 files changed, 6 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d468adb..42d0fdf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3541,77 +3541,6 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 	return plane_ctl;
 }
 
-static void skylake_update_primary_plane(struct intel_plane *plane,
-					 const struct intel_crtc_state *crtc_state,
-					 const struct intel_plane_state *plane_state)
-{
-	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	enum plane_id plane_id = plane->id;
-	enum pipe pipe = plane->pipe;
-	u32 plane_ctl = plane_state->ctl;
-	unsigned int rotation = plane_state->base.rotation;
-	u32 stride = skl_plane_stride(fb, 0, rotation);
-	u32 aux_stride = skl_plane_stride(fb, 1, rotation);
-	u32 surf_addr = plane_state->main.offset;
-	int scaler_id = plane_state->scaler_id;
-	int src_x = plane_state->main.x;
-	int src_y = plane_state->main.y;
-	int src_w = drm_rect_width(&plane_state->base.src) >> 16;
-	int src_h = drm_rect_height(&plane_state->base.src) >> 16;
-	int dst_x = plane_state->base.dst.x1;
-	int dst_y = plane_state->base.dst.y1;
-	int dst_w = drm_rect_width(&plane_state->base.dst);
-	int dst_h = drm_rect_height(&plane_state->base.dst);
-	unsigned long irqflags;
-
-	/* Sizes are 0 based */
-	src_w--;
-	src_h--;
-	dst_w--;
-	dst_h--;
-
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
-	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
-			      PLANE_COLOR_PIPE_GAMMA_ENABLE |
-			      PLANE_COLOR_PIPE_CSC_ENABLE |
-			      PLANE_COLOR_PLANE_GAMMA_DISABLE);
-	}
-
-	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
-	I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
-	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
-	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
-	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
-		      (plane_state->aux.offset - surf_addr) | aux_stride);
-	I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
-		      (plane_state->aux.y << 16) | plane_state->aux.x);
-
-	if (scaler_id >= 0) {
-		uint32_t ps_ctrl = 0;
-
-		WARN_ON(!dst_w || !dst_h);
-		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
-			crtc_state->scaler_state.scalers[scaler_id].mode;
-		I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
-		I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
-		I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
-		I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
-		I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
-	} else {
-		I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
-	}
-
-	I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
-		      intel_plane_ggtt_offset(plane_state) + surf_addr);
-
-	POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
-
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
-}
-
 static void skylake_disable_primary_plane(struct intel_plane *primary,
 					  struct intel_crtc *crtc)
 {
@@ -13284,7 +13213,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		num_formats = ARRAY_SIZE(skl_primary_formats);
 		modifiers = skl_format_modifiers_ccs;
 
-		primary->update_plane = skylake_update_primary_plane;
+		primary->update_plane = skl_update_plane;
 		primary->disable_plane = skylake_disable_primary_plane;
 	} else if (INTEL_GEN(dev_priv) >= 9) {
 		intel_primary_formats = skl_primary_formats;
@@ -13294,7 +13223,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		else
 			modifiers = skl_format_modifiers_noccs;
 
-		primary->update_plane = skylake_update_primary_plane;
+		primary->update_plane = skl_update_plane;
 		primary->disable_plane = skylake_disable_primary_plane;
 	} else if (INTEL_GEN(dev_priv) >= 4) {
 		intel_primary_formats = i965_primary_formats;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 36133e4..4d267c4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1922,6 +1922,9 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 			      struct drm_file *file_priv);
 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
+void skl_update_plane(struct intel_plane *plane,
+		      const struct intel_crtc_state *crtc_state,
+		      const struct intel_plane_state *plane_state);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 86fc9b5..c3583dc 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -230,7 +230,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 #endif
 }
 
-static void
+void
 skl_update_plane(struct intel_plane *plane,
 		 const struct intel_crtc_state *crtc_state,
 		 const struct intel_plane_state *plane_state)
-- 
2.7.4

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[PATCH 4/5] drm/i915: Unify skylake plane disable

[Juha-Pekka Heikkila]

Don't handle skylake primary plane separately as it is similar
plane as the others.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 21 ++-------------------
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
 3 files changed, 4 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 42d0fdf..bd62c0a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3541,23 +3541,6 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 	return plane_ctl;
 }
 
-static void skylake_disable_primary_plane(struct intel_plane *primary,
-					  struct intel_crtc *crtc)
-{
-	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
-	enum plane_id plane_id = primary->id;
-	enum pipe pipe = primary->pipe;
-	unsigned long irqflags;
-
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
-	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
-	I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
-	POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
-
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
-}
-
 static int
 __intel_display_resume(struct drm_device *dev,
 		       struct drm_atomic_state *state,
@@ -13214,7 +13197,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		modifiers = skl_format_modifiers_ccs;
 
 		primary->update_plane = skl_update_plane;
-		primary->disable_plane = skylake_disable_primary_plane;
+		primary->disable_plane = skl_disable_plane;
 	} else if (INTEL_GEN(dev_priv) >= 9) {
 		intel_primary_formats = skl_primary_formats;
 		num_formats = ARRAY_SIZE(skl_primary_formats);
@@ -13224,7 +13207,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 			modifiers = skl_format_modifiers_noccs;
 
 		primary->update_plane = skl_update_plane;
-		primary->disable_plane = skylake_disable_primary_plane;
+		primary->disable_plane = skl_disable_plane;
 	} else if (INTEL_GEN(dev_priv) >= 4) {
 		intel_primary_formats = i965_primary_formats;
 		num_formats = ARRAY_SIZE(i965_primary_formats);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4d267c4..a05ab3a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1925,6 +1925,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
 void skl_update_plane(struct intel_plane *plane,
 		      const struct intel_crtc_state *crtc_state,
 		      const struct intel_plane_state *plane_state);
+void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index c3583dc..4fcf80c 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -311,7 +311,7 @@ skl_update_plane(struct intel_plane *plane,
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
-static void
+void
 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-- 
2.7.4

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[PATCH 5/5] drm/i915: adjust get_crtc_fence_y_offset() to use base.y instead of crtc.y

[Juha-Pekka Heikkila]

This is to use clipped y coordinate here. I left get_crtc_fence_y_offset()
function itself in place as oneliner to maintain comment above it why this
is done.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 ++
 drivers/gpu/drm/i915/intel_fbc.c | 10 ++++------
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 93046b0..809bacf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1116,6 +1116,8 @@ struct intel_fbc {
 			 */
 			int adjusted_x;
 			int adjusted_y;
+
+			int y;
 		} plane;
 
 		struct {
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 0ee65be..1a0f5e0 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -69,12 +69,9 @@ static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  * address we program because it starts at the real start of the buffer, so we
  * have to take this into consideration here.
  */
-static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
+static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct intel_fbc *fbc = &dev_priv->fbc;
-
-	return crtc->base.y - fbc->state_cache.plane.adjusted_y;
+	return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
 }
 
 /*
@@ -762,6 +759,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 	cache->plane.visible = plane_state->base.visible;
 	cache->plane.adjusted_x = plane_state->main.x;
 	cache->plane.adjusted_y = plane_state->main.y;
+	cache->plane.y = plane_state->base.src.y1 >> 16;
 
 	if (!cache->plane.visible)
 		return;
@@ -893,7 +891,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 
 	params->crtc.pipe = crtc->pipe;
 	params->crtc.plane = crtc->plane;
-	params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
+	params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
 
 	params->fb.format = cache->fb.format;
 	params->fb.stride = cache->fb.stride;
-- 
2.7.4

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Re: [PATCH 0/5] drm/i915: Skylake plane update/disable unifications [v6]

[Ville Syrjälä]

On Tue, Oct 17, 2017 at 11:08:06PM +0300, Juha-Pekka Heikkila wrote:
> [v6] small adjustments and rebase (ville syrjälä)
> 
> [v5] use clipped y coordinate at get_crtc_fence_y_offset() (ville syrjälä)
> 
> [v4] rebase
> 
> [v3] Took into account fbc adjusted y/x for primary plane (ville syrjälä)
> 
> [v2] Fixed missed references which were brough on rebase.

In the future please include such changelogs directly in the commit
messages of individual patches (plenty of examples of that in git log).

Anyways, patches look good to me. If they pass CI I'll suck them in.

> 
> /Juha-Pekka
> 
> Juha-Pekka Heikkila (5):
>   drm/i915: move adjusted_x/y from crtc to cache.
>   drm/i915: dspaddr_offset doesn't need to be more than local variable
>   drm/i915: Unify skylake plane update
>   drm/i915: Unify skylake plane disable
>   drm/i915: adjust get_crtc_fence_y_offset() to use base.y instead of
>     crtc.y
> 
>  drivers/gpu/drm/i915/i915_drv.h      |  10 +++
>  drivers/gpu/drm/i915/intel_display.c | 117 +++--------------------------------
>  drivers/gpu/drm/i915/intel_drv.h     |  11 ++--
>  drivers/gpu/drm/i915/intel_fbc.c     |  13 ++--
>  drivers/gpu/drm/i915/intel_sprite.c  |   4 +-
>  5 files changed, 34 insertions(+), 121 deletions(-)
> 
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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✓ Fi.CI.BAT: success for drm/i915: Skylake plane update/disable unifications [v6]

[Patchwork]

== Series Details ==

Series: drm/i915: Skylake plane update/disable unifications [v6]
URL   : https://patchwork.freedesktop.org/series/32157/
State : success

== Summary ==

Series 32157v1 drm/i915: Skylake plane update/disable unifications [v6]
https://patchwork.freedesktop.org/api/1.0/series/32157/revisions/1/mbox/

Test debugfs_test:
        Subgroup read_all_entries:
                dmesg-warn -> PASS       (fi-kbl-7500u) fdo#103285
Test gem_exec_reloc:
        Subgroup basic-cpu-active:
                fail       -> PASS       (fi-gdg-551) fdo#102582 +2
        Subgroup basic-write-gtt-active:
                fail       -> PASS       (fi-gdg-551)

fdo#103285 https://bugs.freedesktop.org/show_bug.cgi?id=103285
fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:441s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:457s
fi-blb-e6850     total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:373s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:538s
fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 time:264s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:501s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:495s
fi-byt-j1900     total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  time:493s
fi-byt-n2820     total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  time:484s
fi-cfl-s         total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  time:549s
fi-elk-e7500     total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:418s
fi-gdg-551       total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 time:251s
fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:580s
fi-hsw-4770r     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:424s
fi-ilk-650       total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  time:435s
fi-ivb-3520m     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:488s
fi-ivb-3770      total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:460s
fi-kbl-7500u     total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  time:486s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:561s
fi-kbl-7567u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:470s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:591s
fi-pnv-d510      total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  time:543s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:449s
fi-skl-6700hq    total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:645s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:518s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:491s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:453s
fi-snb-2520m     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:561s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  time:413s

79104a2f00df1f402e8dad934d6a574f50a1b669 drm-tip: 2017y-10m-17d-15h-35m-59s UTC integration manifest
502341d8d439 drm/i915: adjust get_crtc_fence_y_offset() to use base.y instead of crtc.y
5a4b8b5de667 drm/i915: Unify skylake plane disable
d19644403366 drm/i915: Unify skylake plane update
a4135e7b7279 drm/i915: dspaddr_offset doesn't need to be more than local variable
933f4887ba5b drm/i915: move adjusted_x/y from crtc to cache.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6080/
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✗ Fi.CI.IGT: warning for drm/i915: Skylake plane update/disable unifications [v6]

[Patchwork]

== Series Details ==

Series: drm/i915: Skylake plane update/disable unifications [v6]
URL   : https://patchwork.freedesktop.org/series/32157/
State : warning

== Summary ==

Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-primscrn-spr-indfb-move:
                pass       -> SKIP       (shard-hsw)
Test kms_setmode:
        Subgroup basic:
                pass       -> FAIL       (shard-hsw) fdo#99912

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hsw        total:2551 pass:1440 dwarn:0   dfail:0   fail:9   skip:1102 time:9232s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6080/shards.html
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Re: [PATCH 1/5] drm/i915: move adjusted_x/y from crtc to cache.

[Ville Syrjälä]

On Tue, Oct 17, 2017 at 11:08:07PM +0300, Juha-Pekka Heikkila wrote:

This one lacked a commit message. I just slapped in something
rudimentary this time. In the future make sure the commit messages
are there, and that they're useful ;)

Entire series pushed to dinq. Thanks for the patches.

> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  8 ++++++++
>  drivers/gpu/drm/i915/intel_display.c |  6 ------
>  drivers/gpu/drm/i915/intel_drv.h     |  2 --
>  drivers/gpu/drm/i915/intel_fbc.c     | 11 ++++++++---
>  4 files changed, 16 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index dd141b2..93046b0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1108,6 +1108,14 @@ struct intel_fbc {
>  			int src_w;
>  			int src_h;
>  			bool visible;
> +			/*
> +			 * Display surface base address adjustement for
> +			 * pageflips. Note that on gen4+ this only adjusts up
> +			 * to a tile, offsets within a tile are handled in
> +			 * the hw itself (with the TILEOFF register).
> +			 */
> +			int adjusted_x;
> +			int adjusted_y;
>  		} plane;
>  
>  		struct {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 17a9a57..ccbc7ff 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3306,9 +3306,6 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
>  	else
>  		crtc->dspaddr_offset = linear_offset;
>  
> -	crtc->adjusted_x = x;
> -	crtc->adjusted_y = y;
> -
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
>  	if (INTEL_GEN(dev_priv) < 4) {
> @@ -3577,9 +3574,6 @@ static void skylake_update_primary_plane(struct intel_plane *plane,
>  
>  	crtc->dspaddr_offset = surf_addr;
>  
> -	crtc->adjusted_x = src_x;
> -	crtc->adjusted_y = src_y;
> -
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
>  	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 8296df5..298986f 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -812,8 +812,6 @@ struct intel_crtc {
>  	 * gen4+ this only adjusts up to a tile, offsets within a tile are
>  	 * handled in the hw itself (with the TILEOFF register). */
>  	u32 dspaddr_offset;
> -	int adjusted_x;
> -	int adjusted_y;
>  
>  	struct intel_crtc_state *config;
>  
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 8e3a055..0ee65be 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -71,7 +71,10 @@ static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
>   */
>  static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
>  {
> -	return crtc->base.y - crtc->adjusted_y;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct intel_fbc *fbc = &dev_priv->fbc;
> +
> +	return crtc->base.y - fbc->state_cache.plane.adjusted_y;
>  }
>  
>  /*
> @@ -727,8 +730,8 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
>  
>  	intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
>  					&effective_h);
> -	effective_w += crtc->adjusted_x;
> -	effective_h += crtc->adjusted_y;
> +	effective_w += fbc->state_cache.plane.adjusted_x;
> +	effective_h += fbc->state_cache.plane.adjusted_y;
>  
>  	return effective_w <= max_w && effective_h <= max_h;
>  }
> @@ -757,6 +760,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
>  	cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
>  	cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
>  	cache->plane.visible = plane_state->base.visible;
> +	cache->plane.adjusted_x = plane_state->main.x;
> +	cache->plane.adjusted_y = plane_state->main.y;
>  
>  	if (!cache->plane.visible)
>  		return;
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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