[PATCH 0/8] drm/i915: CNL DVFS thing

Ville Syrjala
2017-10-18T20:48:32Z

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Here's my idea on how the CNL DVFS thing ought to be implemented.
Not sure I gleaned the details of the port clock limits correctly, but
other than that I think this should work.

Entire series available here:
git://github.com/vsyrjala/linux.git dvfs_voltage_4

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Ville Syrjälä (8):
drm/i915: Clean up some cdclk switch statements
drm/i915: Start tracking voltage level in the cdclk state
drm/i915: USe cdclk_state->voltage on VLV/CHV
drm/i915: Use cdclk_state->voltage on BDW
drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL
drm/i915: Use cdclk_state->voltage on BXT/GLK
drm/i915: Use cdclk_state->voltage on CNL
drm/i915: Adjust system agent voltage on CNL if required by DDI ports

drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/intel_cdclk.c | 318 +++++++++++++++++++++++---------
drivers/gpu/drm/i915/intel_ddi.c | 13 ++
drivers/gpu/drm/i915/intel_display.c | 14 +-
drivers/gpu/drm/i915/intel_dp_mst.c | 5 +
drivers/gpu/drm/i915/intel_drv.h | 10 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +-
7 files changed, 276 insertions(+), 90 deletions(-)

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2.13.6