Re: [PATCH v2 4/8] drm/i915: Use cdclk_state->voltage on BDW

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Fri, Oct 20, 2017 at 05:03:58PM +0000, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Track the system agent voltage we request from pcode in the cdclk state
> on BDW. Annoyingly we can't actually read out the current value since
> there's no pcode command to do that, so we'll have to just assume that
> it worked.
> 
> v2: Keep the WARN_ON (Rodrigo)

thanks

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> 
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 32 ++++++++++++++++++++++++++------
>  1 file changed, 26 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index e2f18545d20c..ab0481183bae 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -639,6 +639,21 @@ static int bdw_calc_cdclk(int min_cdclk)
>  		return 337500;
>  }
>  
> +static u8 bdw_calc_voltage(int cdclk)
> +{
> +	switch (cdclk) {
> +	default:
> +	case 337500:
> +		return 2;
> +	case 450000:
> +		return 0;
> +	case 540000:
> +		return 1;
> +	case 675000:
> +		return 3;
> +	}
> +}
> +
>  static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
>  			  struct intel_cdclk_state *cdclk_state)
>  {
> @@ -657,13 +672,19 @@ static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
>  		cdclk_state->cdclk = 337500;
>  	else
>  		cdclk_state->cdclk = 675000;
> +
> +	/*
> +	 * Can't read this out :( Let's assume it's
> +	 * at least what the CDCLK frequency requires.
> +	 */
> +	cdclk_state->voltage = bdw_calc_voltage(cdclk_state->cdclk);
>  }
>  
>  static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
>  			  const struct intel_cdclk_state *cdclk_state)
>  {
>  	int cdclk = cdclk_state->cdclk;
> -	uint32_t val, data;
> +	uint32_t val;
>  	int ret;
>  
>  	if (WARN((I915_READ(LCPLL_CTL) &
> @@ -704,19 +725,15 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
>  		/* fall through */
>  	case 337500:
>  		val |= LCPLL_CLK_FREQ_337_5_BDW;
> -		data = 2;
>  		break;
>  	case 450000:
>  		val |= LCPLL_CLK_FREQ_450;
> -		data = 0;
>  		break;
>  	case 540000:
>  		val |= LCPLL_CLK_FREQ_54O_BDW;
> -		data = 1;
>  		break;
>  	case 675000:
>  		val |= LCPLL_CLK_FREQ_675_BDW;
> -		data = 3;
>  		break;
>  	}
>  
> @@ -731,7 +748,8 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
>  		DRM_ERROR("Switching back to LCPLL failed\n");
>  
>  	mutex_lock(&dev_priv->pcu_lock);
> -	sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
> +	sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
> +				cdclk_state->voltage);
>  	mutex_unlock(&dev_priv->pcu_lock);
>  
>  	I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
> @@ -1910,11 +1928,13 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
>  	cdclk = bdw_calc_cdclk(min_cdclk);
>  
>  	intel_state->cdclk.logical.cdclk = cdclk;
> +	intel_state->cdclk.logical.voltage = bdw_calc_voltage(cdclk);
>  
>  	if (!intel_state->active_crtcs) {
>  		cdclk = bdw_calc_cdclk(0);
>  
>  		intel_state->cdclk.actual.cdclk = cdclk;
> +		intel_state->cdclk.actual.voltage = bdw_calc_voltage(cdclk);
>  	} else {
>  		intel_state->cdclk.actual =
>  			intel_state->cdclk.logical;
> -- 
> 2.13.6
> 
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