From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 6/8] drm/i915: Use cdclk_state->voltage on BXT/GLK
Date: Fri, 20 Oct 2017 13:51:42 -0700 [thread overview]
Message-ID: <20171020205142.uxfofe2ug47fuez3@intel.com> (raw)
In-Reply-To: <20171018204825.2500-7-ville.syrjala@linux.intel.com>
On Wed, Oct 18, 2017 at 08:48:23PM +0000, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Track the system agent voltage we request from pcode in the cdclk state
> on BXT/GLK. Annoyingly we can't actually read out the current value since
> there's no pcode command to do that, so we'll have to just assume that
> it worked.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 6f7b5abe6e3f..1b4dcd9689da 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1166,6 +1166,11 @@ static int glk_calc_cdclk(int min_cdclk)
> return 79200;
> }
>
> +static u8 bxt_calc_voltage(int cdclk)
> +{
> + return DIV_ROUND_UP(cdclk, 25000);
> +}
> +
> static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> {
> int ratio;
> @@ -1242,7 +1247,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> cdclk_state->cdclk = cdclk_state->ref;
>
> if (cdclk_state->vco == 0)
> - return;
> + goto out;
>
> divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
>
> @@ -1266,6 +1271,13 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> }
>
> cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
> +
> + out:
> + /*
> + * Can't read this out :( Let's assume it's
> + * at least what the CDCLK frequency requires.
> + */
> + cdclk_state->voltage = bxt_calc_voltage(cdclk_state->cdclk);
> }
>
> static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
> @@ -1368,7 +1380,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>
> mutex_lock(&dev_priv->pcu_lock);
> ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
> - DIV_ROUND_UP(cdclk, 25000));
> + cdclk_state->voltage);
> mutex_unlock(&dev_priv->pcu_lock);
>
> if (ret) {
> @@ -1460,6 +1472,7 @@ void bxt_init_cdclk(struct drm_i915_private *dev_priv)
> cdclk_state.cdclk = bxt_calc_cdclk(0);
> cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
> }
> + cdclk_state.voltage = bxt_calc_voltage(cdclk_state.cdclk);
>
> bxt_set_cdclk(dev_priv, &cdclk_state);
> }
> @@ -1477,6 +1490,7 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> cdclk_state.cdclk = cdclk_state.ref;
> cdclk_state.vco = 0;
> + cdclk_state.voltage = bxt_calc_voltage(cdclk_state.cdclk);
>
> bxt_set_cdclk(dev_priv, &cdclk_state);
> }
> @@ -2030,6 +2044,7 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>
> intel_state->cdclk.logical.vco = vco;
> intel_state->cdclk.logical.cdclk = cdclk;
> + intel_state->cdclk.logical.voltage = bxt_calc_voltage(cdclk);
>
> if (!intel_state->active_crtcs) {
> if (IS_GEMINILAKE(dev_priv)) {
> @@ -2042,6 +2057,7 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>
> intel_state->cdclk.actual.vco = vco;
> intel_state->cdclk.actual.cdclk = cdclk;
> + intel_state->cdclk.actual.voltage = bxt_calc_voltage(cdclk);
> } else {
> intel_state->cdclk.actual =
> intel_state->cdclk.logical;
> --
> 2.13.6
>
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next prev parent reply other threads:[~2017-10-20 20:51 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-18 20:48 [PATCH 0/8] drm/i915: CNL DVFS thing Ville Syrjala
2017-10-18 20:48 ` [PATCH 1/8] drm/i915: Clean up some cdclk switch statements Ville Syrjala
2017-10-19 7:20 ` Mika Kahola
2017-10-18 20:48 ` [PATCH 2/8] drm/i915: Start tracking voltage level in the cdclk state Ville Syrjala
2017-10-19 23:32 ` Rodrigo Vivi
2017-10-20 14:01 ` Ville Syrjälä
2017-10-20 20:43 ` Rodrigo Vivi
2017-10-23 12:13 ` Ville Syrjälä
2017-10-23 17:14 ` Rodrigo Vivi
2017-10-18 20:48 ` [PATCH 3/8] drm/i915: USe cdclk_state->voltage on VLV/CHV Ville Syrjala
2017-10-19 17:43 ` [PATCH v2 3/8] drm/i915: Use " Ville Syrjala
2017-10-19 23:42 ` Rodrigo Vivi
2017-10-20 16:20 ` Ville Syrjälä
2017-10-20 17:03 ` [PATCH v3 " Ville Syrjala
2017-10-18 20:48 ` [PATCH 4/8] drm/i915: Use cdclk_state->voltage on BDW Ville Syrjala
2017-10-19 23:44 ` Rodrigo Vivi
2017-10-20 16:14 ` Ville Syrjälä
2017-10-20 17:03 ` [PATCH v2 " Ville Syrjala
2017-10-20 20:47 ` Rodrigo Vivi
2017-10-18 20:48 ` [PATCH 5/8] drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL Ville Syrjala
2017-10-19 23:47 ` Rodrigo Vivi
2017-10-20 11:18 ` Ville Syrjälä
2017-10-20 20:45 ` Rodrigo Vivi
2017-10-18 20:48 ` [PATCH 6/8] drm/i915: Use cdclk_state->voltage on BXT/GLK Ville Syrjala
2017-10-20 20:51 ` Rodrigo Vivi [this message]
2017-10-18 20:48 ` [PATCH 7/8] drm/i915: Use cdclk_state->voltage on CNL Ville Syrjala
2017-10-18 21:50 ` Rodrigo Vivi
2017-10-18 22:43 ` Rodrigo Vivi
2017-10-19 10:48 ` Ville Syrjälä
2017-10-19 10:56 ` Mika Kahola
2017-10-19 12:19 ` Ville Syrjälä
2017-10-19 23:52 ` Rodrigo Vivi
2017-10-23 18:29 ` Rodrigo Vivi
2017-10-18 20:48 ` [PATCH 8/8] drm/i915: Adjust system agent voltage on CNL if required by DDI ports Ville Syrjala
2017-10-19 23:54 ` Rodrigo Vivi
2017-10-20 11:11 ` Ville Syrjälä
2017-10-20 17:48 ` Runyan, Arthur J
2017-10-20 20:07 ` Ville Syrjälä
2017-10-20 20:36 ` Rodrigo Vivi
2017-10-20 21:44 ` Runyan, Arthur J
2017-10-23 12:03 ` Ville Syrjälä
2017-10-23 11:48 ` Ville Syrjälä
2017-10-20 14:18 ` Ville Syrjälä
2017-10-20 16:11 ` Ville Syrjälä
2017-10-20 16:09 ` [PATCH v2 " Ville Syrjala
2017-10-20 16:52 ` Ville Syrjälä
2017-10-20 17:05 ` [PATCH v3 " Ville Syrjala
2017-10-23 18:39 ` Rodrigo Vivi
2017-10-18 21:07 ` ✗ Fi.CI.BAT: warning for drm/i915: CNL DVFS thing Patchwork
2017-10-19 17:31 ` Ville Syrjälä
2017-10-19 18:17 ` ✗ Fi.CI.BAT: failure for drm/i915: CNL DVFS thing (rev2) Patchwork
2017-10-19 18:52 ` Patchwork
2017-10-19 20:07 ` ✗ Fi.CI.BAT: warning " Patchwork
2017-10-19 23:27 ` ✓ Fi.CI.BAT: success " Patchwork
2017-10-20 0:22 ` ✓ Fi.CI.IGT: " Patchwork
2017-10-20 16:28 ` ✓ Fi.CI.BAT: success for drm/i915: CNL DVFS thing (rev3) Patchwork
2017-10-20 17:48 ` ✓ Fi.CI.BAT: success for drm/i915: CNL DVFS thing (rev6) Patchwork
2017-10-20 19:19 ` ✓ Fi.CI.IGT: " Patchwork
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