From: Tvrtko Ursulin <tursulin@ursulin.net>
To: Intel-gfx@lists.freedesktop.org
Subject: [PATCH 9/9] drm/i915/pmu: Add RC6 residency metrics
Date: Wed, 25 Oct 2017 10:06:07 +0100 [thread overview]
Message-ID: <20171025090607.24748-10-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20171025090607.24748-1-tvrtko.ursulin@linux.intel.com>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
For clients like intel-gpu-overlay it is easier to read the
counters via the perf API than having to parse sysfs.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_pmu.c | 31 +++++++++++++++++++++++++++++++
include/uapi/drm/i915_drm.h | 6 +++++-
2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 2e049205eb59..312e26095c4b 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -361,6 +361,15 @@ static int i915_pmu_event_init(struct perf_event *event)
break;
case I915_PMU_INTERRUPTS:
break;
+ case I915_PMU_RC6_RESIDENCY:
+ if (!HAS_RC6(i915))
+ ret = -ENODEV;
+ break;
+ case I915_PMU_RC6p_RESIDENCY:
+ case I915_PMU_RC6pp_RESIDENCY:
+ if (!HAS_RC6p(i915))
+ ret = -ENODEV;
+ break;
default:
ret = -ENOENT;
break;
@@ -413,6 +422,24 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
case I915_PMU_INTERRUPTS:
val = count_interrupts(i915);
break;
+ case I915_PMU_RC6_RESIDENCY:
+ intel_runtime_pm_get(i915);
+ val = intel_rc6_residency_ns(i915,
+ IS_VALLEYVIEW(i915) ?
+ VLV_GT_RENDER_RC6 :
+ GEN6_GT_GFX_RC6);
+ intel_runtime_pm_put(i915);
+ break;
+ case I915_PMU_RC6p_RESIDENCY:
+ intel_runtime_pm_get(i915);
+ val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
+ intel_runtime_pm_put(i915);
+ break;
+ case I915_PMU_RC6pp_RESIDENCY:
+ intel_runtime_pm_get(i915);
+ val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
+ intel_runtime_pm_put(i915);
+ break;
}
}
@@ -677,6 +704,10 @@ static struct attribute *i915_pmu_events_attrs[] = {
I915_EVENT_ATTR(interrupts, I915_PMU_INTERRUPTS),
+ I915_EVENT(rc6-residency, I915_PMU_RC6_RESIDENCY, "ns"),
+ I915_EVENT(rc6p-residency, I915_PMU_RC6p_RESIDENCY, "ns"),
+ I915_EVENT(rc6pp-residency, I915_PMU_RC6pp_RESIDENCY, "ns"),
+
NULL,
};
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 8aceb7f57e0c..709f28fc0970 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -134,7 +134,11 @@ enum drm_i915_pmu_engine_sample {
#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
-#define I915_PMU_LAST I915_PMU_INTERRUPTS
+#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
+#define I915_PMU_RC6p_RESIDENCY __I915_PMU_OTHER(4)
+#define I915_PMU_RC6pp_RESIDENCY __I915_PMU_OTHER(5)
+
+#define I915_PMU_LAST I915_PMU_RC6pp_RESIDENCY
/* Each region is a minimum of 16k, and there are at most 255 of them.
*/
--
2.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2017-10-25 9:06 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-25 9:05 [PATCH v9 0/9] i915 PMU and engine busy stats Tvrtko Ursulin
2017-10-25 9:05 ` [PATCH 1/9] drm/i915: Extract intel_get_cagf Tvrtko Ursulin
2017-10-25 9:06 ` [PATCH 2/9] drm/i915/pmu: Expose a PMU interface for perf queries Tvrtko Ursulin
2017-10-25 9:06 ` [PATCH 3/9] drm/i915/pmu: Suspend sampling when GPU is idle Tvrtko Ursulin
2017-10-25 9:13 ` Chris Wilson
2017-10-25 12:44 ` Tvrtko Ursulin
2017-10-25 12:58 ` Chris Wilson
2017-10-25 14:27 ` [PATCH v11 " Tvrtko Ursulin
2017-10-25 9:06 ` [PATCH 4/9] drm/i915: Wrap context schedule notification Tvrtko Ursulin
2017-10-25 9:06 ` [PATCH 5/9] drm/i915: Engine busy time tracking Tvrtko Ursulin
2017-10-25 9:06 ` [PATCH 6/9] drm/i915/pmu: Wire up engine busy stats to PMU Tvrtko Ursulin
2017-10-25 9:06 ` [PATCH 7/9] drm/i915/pmu: Add interrupt count metric Tvrtko Ursulin
2017-10-25 9:06 ` [PATCH 8/9] drm/i915: Convert intel_rc6_residency_us to ns Tvrtko Ursulin
2017-10-25 9:06 ` Tvrtko Ursulin [this message]
2017-10-25 9:54 ` ✓ Fi.CI.BAT: success for i915 PMU and engine busy stats (rev20) Patchwork
2017-10-25 10:52 ` ✓ Fi.CI.IGT: " Patchwork
2017-10-25 15:10 ` ✓ Fi.CI.BAT: success for i915 PMU and engine busy stats (rev21) Patchwork
2017-10-25 16:05 ` ✗ Fi.CI.IGT: warning " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2017-11-13 8:57 [PATCH v10 0/9] i915 PMU and engine busy stats Tvrtko Ursulin
2017-11-13 8:57 ` [PATCH 9/9] drm/i915/pmu: Add RC6 residency metrics Tvrtko Ursulin
2017-10-20 9:24 [PATCH v8 0/9] i915 PMU and engine busy stats Tvrtko Ursulin
2017-10-20 9:24 ` [PATCH 9/9] drm/i915/pmu: Add RC6 residency metrics Tvrtko Ursulin
2017-10-11 12:55 [PATCH v7 0/9] i915 PMU and engine busy stats Tvrtko Ursulin
2017-10-11 12:55 ` [PATCH 9/9] drm/i915/pmu: Add RC6 residency metrics Tvrtko Ursulin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20171025090607.24748-10-tvrtko.ursulin@linux.intel.com \
--to=tursulin@ursulin.net \
--cc=Intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox