* [PATCH 01/10] drm/i915: Clean up some cdclk switch statements
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
@ 2017-10-24 9:52 ` Ville Syrjala
2017-10-24 9:52 ` [PATCH v2 02/10] drm/i915: Start tracking voltage level in the cdclk state Ville Syrjala
` (16 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2017-10-24 9:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Redo some switch statements in the cdclk code to use a common
fall through for the default case. Makes everything look a bit
more uniform
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 68 +++++++++++++++++++-------------------
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index b2a6d62b71c0..4bffd31a8924 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -681,6 +681,13 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
val &= ~LCPLL_CLK_FREQ_MASK;
switch (cdclk) {
+ default:
+ MISSING_CASE(cdclk);
+ /* fall through */
+ case 337500:
+ val |= LCPLL_CLK_FREQ_337_5_BDW;
+ data = 2;
+ break;
case 450000:
val |= LCPLL_CLK_FREQ_450;
data = 0;
@@ -689,17 +696,10 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
val |= LCPLL_CLK_FREQ_54O_BDW;
data = 1;
break;
- case 337500:
- val |= LCPLL_CLK_FREQ_337_5_BDW;
- data = 2;
- break;
case 675000:
val |= LCPLL_CLK_FREQ_675_BDW;
data = 3;
break;
- default:
- WARN(1, "invalid cdclk frequency\n");
- return;
}
I915_WRITE(LCPLL_CTL, val);
@@ -926,8 +926,6 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
u32 freq_select, pcu_ack;
int ret;
- WARN_ON((cdclk == 24000) != (vco == 0));
-
mutex_lock(&dev_priv->pcu_lock);
ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
SKL_CDCLK_PREPARE_FOR_CHANGE,
@@ -942,6 +940,15 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
/* set CDCLK_CTL */
switch (cdclk) {
+ default:
+ WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
+ WARN_ON(vco != 0);
+ /* fall through */
+ case 308571:
+ case 337500:
+ freq_select = CDCLK_FREQ_337_308;
+ pcu_ack = 0;
+ break;
case 450000:
case 432000:
freq_select = CDCLK_FREQ_450_432;
@@ -951,12 +958,6 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
freq_select = CDCLK_FREQ_540;
pcu_ack = 2;
break;
- case 308571:
- case 337500:
- default:
- freq_select = CDCLK_FREQ_337_308;
- pcu_ack = 0;
- break;
case 617143:
case 675000:
freq_select = CDCLK_FREQ_675_617;
@@ -1110,6 +1111,7 @@ static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
switch (cdclk) {
default:
MISSING_CASE(cdclk);
+ /* fall through */
case 144000:
case 288000:
case 384000:
@@ -1134,6 +1136,7 @@ static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
switch (cdclk) {
default:
MISSING_CASE(cdclk);
+ /* fall through */
case 79200:
case 158400:
case 316800:
@@ -1246,24 +1249,22 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
/* cdclk = vco / 2 / div{1,1.5,2,4} */
switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
- case 8:
- divider = BXT_CDCLK_CD2X_DIV_SEL_4;
- break;
- case 4:
- divider = BXT_CDCLK_CD2X_DIV_SEL_2;
+ default:
+ WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
+ WARN_ON(vco != 0);
+ /* fall through */
+ case 2:
+ divider = BXT_CDCLK_CD2X_DIV_SEL_1;
break;
case 3:
WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
break;
- case 2:
- divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+ case 4:
+ divider = BXT_CDCLK_CD2X_DIV_SEL_2;
break;
- default:
- WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
- WARN_ON(vco != 0);
-
- divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+ case 8:
+ divider = BXT_CDCLK_CD2X_DIV_SEL_4;
break;
}
@@ -1532,18 +1533,16 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
/* cdclk = vco / 2 / div{1,2} */
switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
- case 4:
- divider = BXT_CDCLK_CD2X_DIV_SEL_2;
- break;
- case 2:
- divider = BXT_CDCLK_CD2X_DIV_SEL_1;
- break;
default:
WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
WARN_ON(vco != 0);
-
+ /* fall through */
+ case 2:
divider = BXT_CDCLK_CD2X_DIV_SEL_1;
break;
+ case 4:
+ divider = BXT_CDCLK_CD2X_DIV_SEL_2;
+ break;
}
switch (cdclk) {
@@ -1592,6 +1591,7 @@ static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
switch (cdclk) {
default:
MISSING_CASE(cdclk);
+ /* fall through */
case 168000:
case 336000:
ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
--
2.13.6
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 02/10] drm/i915: Start tracking voltage level in the cdclk state
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
2017-10-24 9:52 ` [PATCH 01/10] drm/i915: Clean up some cdclk switch statements Ville Syrjala
@ 2017-10-24 9:52 ` Ville Syrjala
2017-10-24 9:52 ` [PATCH v4 03/10] drm/i915: Use cdclk_state->voltage on VLV/CHV Ville Syrjala
` (15 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2017-10-24 9:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
For CNL we'll need to start considering the port clocks when we select
the voltage level for the system agent. To that end start tracking the
voltage in the cdclk state (since that already has to adjust it).
v2: s/voltage/voltage_level/ (Rodrigo)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_cdclk.c | 31 ++++++++++++++++++++++++-------
drivers/gpu/drm/i915/intel_display.c | 8 ++++----
drivers/gpu/drm/i915/intel_drv.h | 4 +++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 ++-
5 files changed, 34 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54b5d4c582b6..2c64c6680ac7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2228,6 +2228,7 @@ struct i915_oa_ops {
struct intel_cdclk_state {
unsigned int cdclk, vco, ref;
+ u8 voltage_level;
};
struct drm_i915_private {
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 4bffd31a8924..6dad2efd5e27 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1690,17 +1690,34 @@ void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
}
/**
- * intel_cdclk_state_compare - Determine if two CDCLK states differ
+ * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes
* @a: first CDCLK state
* @b: second CDCLK state
*
* Returns:
- * True if the CDCLK states are identical, false if they differ.
+ * True if the CDCLK states require pipes to be off during reprogramming, false if not.
*/
-bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
+bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
const struct intel_cdclk_state *b)
{
- return memcmp(a, b, sizeof(*a)) == 0;
+ return a->cdclk != b->cdclk ||
+ a->vco != b->vco ||
+ a->ref != b->ref;
+}
+
+/**
+ * intel_cdclk_changed - Determine if two CDCLK states are different
+ * @a: first CDCLK state
+ * @b: second CDCLK state
+ *
+ * Returns:
+ * True if the CDCLK states don't match, false if they do.
+ */
+bool intel_cdclk_changed(const struct intel_cdclk_state *a,
+ const struct intel_cdclk_state *b)
+{
+ return intel_cdclk_needs_modeset(a, b) ||
+ a->voltage_level != b->voltage_level;
}
/**
@@ -1714,15 +1731,15 @@ bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
void intel_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *cdclk_state)
{
- if (intel_cdclk_state_compare(&dev_priv->cdclk.hw, cdclk_state))
+ if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
return;
if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
return;
- DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n",
+ DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz, voltage_level %d\n",
cdclk_state->cdclk, cdclk_state->vco,
- cdclk_state->ref);
+ cdclk_state->ref, cdclk_state->voltage_level);
dev_priv->display.set_cdclk(dev_priv, cdclk_state);
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e2ac976844d8..1d2031a5f4bb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11931,16 +11931,16 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
* holding all the crtc locks, even if we don't end up
* touching the hardware
*/
- if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
- &intel_state->cdclk.logical)) {
+ if (intel_cdclk_changed(&dev_priv->cdclk.logical,
+ &intel_state->cdclk.logical)) {
ret = intel_lock_all_pipes(state);
if (ret < 0)
return ret;
}
/* All pipes must be switched off while we change the cdclk. */
- if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
- &intel_state->cdclk.actual)) {
+ if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
+ &intel_state->cdclk.actual)) {
ret = intel_modeset_all_pipes(state);
if (ret < 0)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 47d022d48718..a551aadb157b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1323,8 +1323,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
void intel_update_cdclk(struct drm_i915_private *dev_priv);
void intel_update_rawclk(struct drm_i915_private *dev_priv);
-bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
+bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
const struct intel_cdclk_state *b);
+bool intel_cdclk_changed(const struct intel_cdclk_state *a,
+ const struct intel_cdclk_state *b);
void intel_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *cdclk_state);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8af286c63d3b..8315499452dc 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -705,7 +705,8 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
- WARN_ON(!intel_cdclk_state_compare(&dev_priv->cdclk.hw, &cdclk_state));
+ /* Can't read out voltage_level so can't use intel_cdclk_changed() */
+ WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
gen9_assert_dbuf_enabled(dev_priv);
--
2.13.6
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v4 03/10] drm/i915: Use cdclk_state->voltage on VLV/CHV
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
2017-10-24 9:52 ` [PATCH 01/10] drm/i915: Clean up some cdclk switch statements Ville Syrjala
2017-10-24 9:52 ` [PATCH v2 02/10] drm/i915: Start tracking voltage level in the cdclk state Ville Syrjala
@ 2017-10-24 9:52 ` Ville Syrjala
2017-10-24 9:52 ` [PATCH v3 04/10] drm/i915: Use cdclk_state->voltage on BDW Ville Syrjala
` (14 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2017-10-24 9:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Store the punit DSPFREQUAR value into cdclk_state->voltage on
VLV/CHV. Since we can actually read that out from the hardware
this can give us a bit more cross checking between the hardware
and software state.
v2: Don't break waiting for cdclk change on VLV/CHV
v3: Split out the cdclk sanity check in vlv_set_cdclk() (Rodrigo)
v4: s/voltage/voltage_level/ (Rodrigo)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 54 +++++++++++++++++++++++++++-----------
1 file changed, 38 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 6dad2efd5e27..8bc093082511 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -437,13 +437,45 @@ static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
return 200000;
}
+static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
+{
+ if (IS_VALLEYVIEW(dev_priv)) {
+ if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
+ return 2;
+ else if (cdclk >= 266667)
+ return 1;
+ else
+ return 0;
+ } else {
+ /*
+ * Specs are full of misinformation, but testing on actual
+ * hardware has shown that we just need to write the desired
+ * CCK divider into the Punit register.
+ */
+ return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
+ }
+}
+
static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_state)
{
+ u32 val;
+
cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
CCK_DISPLAY_CLOCK_CONTROL,
cdclk_state->vco);
+
+ mutex_lock(&dev_priv->pcu_lock);
+ val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
+ mutex_unlock(&dev_priv->pcu_lock);
+
+ if (IS_VALLEYVIEW(dev_priv))
+ cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
+ DSPFREQGUAR_SHIFT;
+ else
+ cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
+ DSPFREQGUAR_SHIFT_CHV;
}
static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
@@ -486,7 +518,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *cdclk_state)
{
int cdclk = cdclk_state->cdclk;
- u32 val, cmd;
+ u32 val, cmd = cdclk_state->voltage_level;
/* There are cases where we can end up here with power domains
* off and a CDCLK frequency other than the minimum, like when
@@ -496,13 +528,6 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
*/
intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
- if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
- cmd = 2;
- else if (cdclk == 266667)
- cmd = 1;
- else
- cmd = 0;
-
mutex_lock(&dev_priv->pcu_lock);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
val &= ~DSPFREQGUAR_MASK;
@@ -562,7 +587,7 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *cdclk_state)
{
int cdclk = cdclk_state->cdclk;
- u32 val, cmd;
+ u32 val, cmd = cdclk_state->voltage_level;
switch (cdclk) {
case 333333:
@@ -583,13 +608,6 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
*/
intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
- /*
- * Specs are full of misinformation, but testing on actual
- * hardware has shown that we just need to write the desired
- * CCK divider into the Punit register.
- */
- cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
-
mutex_lock(&dev_priv->pcu_lock);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
val &= ~DSPFREQGUAR_MASK_CHV;
@@ -1859,11 +1877,15 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
intel_state->cdclk.logical.cdclk = cdclk;
+ intel_state->cdclk.logical.voltage_level =
+ vlv_calc_voltage_level(dev_priv, cdclk);
if (!intel_state->active_crtcs) {
cdclk = vlv_calc_cdclk(dev_priv, 0);
intel_state->cdclk.actual.cdclk = cdclk;
+ intel_state->cdclk.actual.voltage_level =
+ vlv_calc_voltage_level(dev_priv, cdclk);
} else {
intel_state->cdclk.actual =
intel_state->cdclk.logical;
--
2.13.6
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 04/10] drm/i915: Use cdclk_state->voltage on BDW
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (2 preceding siblings ...)
2017-10-24 9:52 ` [PATCH v4 03/10] drm/i915: Use cdclk_state->voltage on VLV/CHV Ville Syrjala
@ 2017-10-24 9:52 ` Ville Syrjala
2017-10-24 9:52 ` [PATCH v2 05/10] drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL Ville Syrjala
` (13 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2017-10-24 9:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Track the system agent voltage we request from pcode in the cdclk state
on BDW. Annoyingly we can't actually read out the current value since
there's no pcode command to do that, so we'll have to just assume that
it worked.
v2: Keep the WARN_ON (Rodrigo)
v3: s/voltage/voltage_level/ (Rodrigo)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 35 +++++++++++++++++++++++++++++------
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 8bc093082511..c98fec333dd1 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -639,6 +639,21 @@ static int bdw_calc_cdclk(int min_cdclk)
return 337500;
}
+static u8 bdw_calc_voltage_level(int cdclk)
+{
+ switch (cdclk) {
+ default:
+ case 337500:
+ return 2;
+ case 450000:
+ return 0;
+ case 540000:
+ return 1;
+ case 675000:
+ return 3;
+ }
+}
+
static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_state)
{
@@ -657,13 +672,20 @@ static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
cdclk_state->cdclk = 337500;
else
cdclk_state->cdclk = 675000;
+
+ /*
+ * Can't read this out :( Let's assume it's
+ * at least what the CDCLK frequency requires.
+ */
+ cdclk_state->voltage_level =
+ bdw_calc_voltage_level(cdclk_state->cdclk);
}
static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *cdclk_state)
{
int cdclk = cdclk_state->cdclk;
- uint32_t val, data;
+ uint32_t val;
int ret;
if (WARN((I915_READ(LCPLL_CTL) &
@@ -704,19 +726,15 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
/* fall through */
case 337500:
val |= LCPLL_CLK_FREQ_337_5_BDW;
- data = 2;
break;
case 450000:
val |= LCPLL_CLK_FREQ_450;
- data = 0;
break;
case 540000:
val |= LCPLL_CLK_FREQ_54O_BDW;
- data = 1;
break;
case 675000:
val |= LCPLL_CLK_FREQ_675_BDW;
- data = 3;
break;
}
@@ -731,7 +749,8 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
DRM_ERROR("Switching back to LCPLL failed\n");
mutex_lock(&dev_priv->pcu_lock);
- sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
+ sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
+ cdclk_state->voltage_level);
mutex_unlock(&dev_priv->pcu_lock);
I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
@@ -1910,11 +1929,15 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
cdclk = bdw_calc_cdclk(min_cdclk);
intel_state->cdclk.logical.cdclk = cdclk;
+ intel_state->cdclk.logical.voltage_level =
+ bdw_calc_voltage_level(cdclk);
if (!intel_state->active_crtcs) {
cdclk = bdw_calc_cdclk(0);
intel_state->cdclk.actual.cdclk = cdclk;
+ intel_state->cdclk.actual.voltage_level =
+ bdw_calc_voltage_level(cdclk);
} else {
intel_state->cdclk.actual =
intel_state->cdclk.logical;
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 05/10] drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (3 preceding siblings ...)
2017-10-24 9:52 ` [PATCH v3 04/10] drm/i915: Use cdclk_state->voltage on BDW Ville Syrjala
@ 2017-10-24 9:52 ` Ville Syrjala
2017-10-24 9:52 ` [PATCH v2 06/10] drm/i915: Use cdclk_state->voltage on BXT/GLK Ville Syrjala
` (12 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2017-10-24 9:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Track the system agent voltage we request from pcode in the cdclk state
on SKL/KBL/CFL. Annoyingly we can't actually read out the current value since
there's no pcode command to do that, so we'll have to just assume that
it worked.
v2: s/voltage/voltage_level/ (Rodrigo)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 43 +++++++++++++++++++++++++++++++-------
1 file changed, 36 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index c98fec333dd1..38e31df265bd 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -785,6 +785,24 @@ static int skl_calc_cdclk(int min_cdclk, int vco)
}
}
+static u8 skl_calc_voltage_level(int cdclk)
+{
+ switch (cdclk) {
+ default:
+ case 308571:
+ case 337500:
+ return 0;
+ case 450000:
+ case 432000:
+ return 1;
+ case 540000:
+ return 2;
+ case 617143:
+ case 675000:
+ return 3;
+ }
+}
+
static void skl_dpll0_update(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_state)
{
@@ -835,7 +853,7 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv,
cdclk_state->cdclk = cdclk_state->ref;
if (cdclk_state->vco == 0)
- return;
+ goto out;
cdctl = I915_READ(CDCLK_CTL);
@@ -876,6 +894,14 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv,
break;
}
}
+
+ out:
+ /*
+ * Can't read this out :( Let's assume it's
+ * at least what the CDCLK frequency requires.
+ */
+ cdclk_state->voltage_level =
+ skl_calc_voltage_level(cdclk_state->cdclk);
}
/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
@@ -960,7 +986,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
{
int cdclk = cdclk_state->cdclk;
int vco = cdclk_state->vco;
- u32 freq_select, pcu_ack;
+ u32 freq_select;
int ret;
mutex_lock(&dev_priv->pcu_lock);
@@ -984,21 +1010,17 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
case 308571:
case 337500:
freq_select = CDCLK_FREQ_337_308;
- pcu_ack = 0;
break;
case 450000:
case 432000:
freq_select = CDCLK_FREQ_450_432;
- pcu_ack = 1;
break;
case 540000:
freq_select = CDCLK_FREQ_540;
- pcu_ack = 2;
break;
case 617143:
case 675000:
freq_select = CDCLK_FREQ_675_617;
- pcu_ack = 3;
break;
}
@@ -1014,7 +1036,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
/* inform PCU of the change */
mutex_lock(&dev_priv->pcu_lock);
- sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
+ sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ cdclk_state->voltage_level);
mutex_unlock(&dev_priv->pcu_lock);
intel_update_cdclk(dev_priv);
@@ -1093,6 +1116,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
if (cdclk_state.vco == 0)
cdclk_state.vco = 8100000;
cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
+ cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
skl_set_cdclk(dev_priv, &cdclk_state);
}
@@ -1110,6 +1134,7 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
cdclk_state.cdclk = cdclk_state.ref;
cdclk_state.vco = 0;
+ cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
skl_set_cdclk(dev_priv, &cdclk_state);
}
@@ -1968,12 +1993,16 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
intel_state->cdclk.logical.vco = vco;
intel_state->cdclk.logical.cdclk = cdclk;
+ intel_state->cdclk.logical.voltage_level =
+ skl_calc_voltage_level(cdclk);
if (!intel_state->active_crtcs) {
cdclk = skl_calc_cdclk(0, vco);
intel_state->cdclk.actual.vco = vco;
intel_state->cdclk.actual.cdclk = cdclk;
+ intel_state->cdclk.actual.voltage_level =
+ skl_calc_voltage_level(cdclk);
} else {
intel_state->cdclk.actual =
intel_state->cdclk.logical;
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 06/10] drm/i915: Use cdclk_state->voltage on BXT/GLK
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (4 preceding siblings ...)
2017-10-24 9:52 ` [PATCH v2 05/10] drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL Ville Syrjala
@ 2017-10-24 9:52 ` Ville Syrjala
2017-10-24 9:52 ` [PATCH v2 07/10] drm/i915: Use cdclk_state->voltage on CNL Ville Syrjala
` (11 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2017-10-24 9:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Track the system agent voltage we request from pcode in the cdclk state
on BXT/GLK. Annoyingly we can't actually read out the current value since
there's no pcode command to do that, so we'll have to just assume that
it worked.
v2: s/voltage/voltage_level/ (Rodrigo)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 38e31df265bd..a40dc66dc773 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1163,6 +1163,11 @@ static int glk_calc_cdclk(int min_cdclk)
return 79200;
}
+static u8 bxt_calc_voltage_level(int cdclk)
+{
+ return DIV_ROUND_UP(cdclk, 25000);
+}
+
static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
{
int ratio;
@@ -1239,7 +1244,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
cdclk_state->cdclk = cdclk_state->ref;
if (cdclk_state->vco == 0)
- return;
+ goto out;
divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
@@ -1263,6 +1268,14 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
}
cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
+
+ out:
+ /*
+ * Can't read this out :( Let's assume it's
+ * at least what the CDCLK frequency requires.
+ */
+ cdclk_state->voltage_level =
+ bxt_calc_voltage_level(cdclk_state->cdclk);
}
static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1365,7 +1378,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
mutex_lock(&dev_priv->pcu_lock);
ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
- DIV_ROUND_UP(cdclk, 25000));
+ cdclk_state->voltage_level);
mutex_unlock(&dev_priv->pcu_lock);
if (ret) {
@@ -1457,6 +1470,7 @@ void bxt_init_cdclk(struct drm_i915_private *dev_priv)
cdclk_state.cdclk = bxt_calc_cdclk(0);
cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
}
+ cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
bxt_set_cdclk(dev_priv, &cdclk_state);
}
@@ -1474,6 +1488,7 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
cdclk_state.cdclk = cdclk_state.ref;
cdclk_state.vco = 0;
+ cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
bxt_set_cdclk(dev_priv, &cdclk_state);
}
@@ -2031,6 +2046,8 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
intel_state->cdclk.logical.vco = vco;
intel_state->cdclk.logical.cdclk = cdclk;
+ intel_state->cdclk.logical.voltage_level =
+ bxt_calc_voltage_level(cdclk);
if (!intel_state->active_crtcs) {
if (IS_GEMINILAKE(dev_priv)) {
@@ -2043,6 +2060,8 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
intel_state->cdclk.actual.vco = vco;
intel_state->cdclk.actual.cdclk = cdclk;
+ intel_state->cdclk.actual.voltage_level =
+ bxt_calc_voltage_level(cdclk);
} else {
intel_state->cdclk.actual =
intel_state->cdclk.logical;
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 07/10] drm/i915: Use cdclk_state->voltage on CNL
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (5 preceding siblings ...)
2017-10-24 9:52 ` [PATCH v2 06/10] drm/i915: Use cdclk_state->voltage on BXT/GLK Ville Syrjala
@ 2017-10-24 9:52 ` Ville Syrjala
2017-10-24 9:52 ` [PATCH v4 08/10] drm/i915: Adjust system agent voltage on CNL if required by DDI ports Ville Syrjala
` (10 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2017-10-24 9:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Track the system agent voltage we request from pcode in the cdclk state
on CNL. Annoyingly we can't actually read out the current value since
there's no pcode command to do that, so we'll have to just assume that
it worked.
v2: s/voltage/voltage_level/ (Rodrigo)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 47 +++++++++++++++++++++++++-------------
1 file changed, 31 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index a40dc66dc773..210e79193fe6 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1503,6 +1503,19 @@ static int cnl_calc_cdclk(int min_cdclk)
return 168000;
}
+static u8 cnl_calc_voltage_level(int cdclk)
+{
+ switch (cdclk) {
+ default:
+ case 168000:
+ return 0;
+ case 336000:
+ return 1;
+ case 528000:
+ return 2;
+ }
+}
+
static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_state)
{
@@ -1536,7 +1549,7 @@ static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
cdclk_state->cdclk = cdclk_state->ref;
if (cdclk_state->vco == 0)
- return;
+ goto out;
divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
@@ -1553,6 +1566,14 @@ static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
}
cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
+
+ out:
+ /*
+ * Can't read this out :( Let's assume it's
+ * at least what the CDCLK frequency requires.
+ */
+ cdclk_state->voltage_level =
+ cnl_calc_voltage_level(cdclk_state->cdclk);
}
static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
@@ -1593,7 +1614,7 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
{
int cdclk = cdclk_state->cdclk;
int vco = cdclk_state->vco;
- u32 val, divider, pcu_ack;
+ u32 val, divider;
int ret;
mutex_lock(&dev_priv->pcu_lock);
@@ -1622,19 +1643,6 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
break;
}
- switch (cdclk) {
- case 528000:
- pcu_ack = 2;
- break;
- case 336000:
- pcu_ack = 1;
- break;
- case 168000:
- default:
- pcu_ack = 0;
- break;
- }
-
if (dev_priv->cdclk.hw.vco != 0 &&
dev_priv->cdclk.hw.vco != vco)
cnl_cdclk_pll_disable(dev_priv);
@@ -1652,7 +1660,8 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
/* inform PCU of the change */
mutex_lock(&dev_priv->pcu_lock);
- sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
+ sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ cdclk_state->voltage_level);
mutex_unlock(&dev_priv->pcu_lock);
intel_update_cdclk(dev_priv);
@@ -1745,6 +1754,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv)
cdclk_state.cdclk = cnl_calc_cdclk(0);
cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
+ cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
cnl_set_cdclk(dev_priv, &cdclk_state);
}
@@ -1762,6 +1772,7 @@ void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
cdclk_state.cdclk = cdclk_state.ref;
cdclk_state.vco = 0;
+ cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
cnl_set_cdclk(dev_priv, &cdclk_state);
}
@@ -2085,6 +2096,8 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
intel_state->cdclk.logical.vco = vco;
intel_state->cdclk.logical.cdclk = cdclk;
+ intel_state->cdclk.logical.voltage_level =
+ cnl_calc_voltage_level(cdclk);
if (!intel_state->active_crtcs) {
cdclk = cnl_calc_cdclk(0);
@@ -2092,6 +2105,8 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
intel_state->cdclk.actual.vco = vco;
intel_state->cdclk.actual.cdclk = cdclk;
+ intel_state->cdclk.actual.voltage_level =
+ cnl_calc_voltage_level(cdclk);
} else {
intel_state->cdclk.actual =
intel_state->cdclk.logical;
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v4 08/10] drm/i915: Adjust system agent voltage on CNL if required by DDI ports
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (6 preceding siblings ...)
2017-10-24 9:52 ` [PATCH v2 07/10] drm/i915: Use cdclk_state->voltage on CNL Ville Syrjala
@ 2017-10-24 9:52 ` Ville Syrjala
2017-10-24 9:52 ` [PATCH 09/10] drm/i915: Sanity check cdclk in vlv_set_cdclk() Ville Syrjala
` (9 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2017-10-24 9:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On CNL we may need to bump up the system agent voltage not only due
to CDCLK but also when driving DDI port with a sufficiently high clock.
To that end start tracking the minimum acceptable voltage for each crtc.
We do the tracking via crtcs because we don't have any kind of encoder
state. Also there's no downside to doing it this way, and it matches how
we track cdclk requirements on account of pixel rate.
v2: Allow disabled crtcs to use the min voltage
Add IS_CNL check to intel_ddi_compute_min_voltage() since
we're using CNL specific values there
s/intel_compute_min_voltage/cnl_compute_min_voltage/ since
the function makes hw specific assumptions about the voltage
values
v3: Drop the test hack leftovers from skl_modeset_calc_cdclk()
v4: s/voltage/voltage_level/ (Rodrigo)
Replace DPLL DVFS FIXMEs with an explanation why we don't
do anything there (Rodrigo)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_cdclk.c | 46 ++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++
drivers/gpu/drm/i915/intel_display.c | 11 +++++++++
drivers/gpu/drm/i915/intel_dp_mst.c | 5 ++++
drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 ++++++------
drivers/gpu/drm/i915/intel_drv.h | 7 ++++++
7 files changed, 89 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c64c6680ac7..366ba74b0ad2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2416,6 +2416,8 @@ struct drm_i915_private {
unsigned int active_crtcs;
/* minimum acceptable cdclk for each pipe */
int min_cdclk[I915_MAX_PIPES];
+ /* minimum acceptable voltage level for each pipe */
+ u8 min_voltage_level[I915_MAX_PIPES];
int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 210e79193fe6..4ca4a34b7bfa 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1665,6 +1665,12 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
mutex_unlock(&dev_priv->pcu_lock);
intel_update_cdclk(dev_priv);
+
+ /*
+ * Can't read out the voltage level :(
+ * Let's just assume everything is as expected.
+ */
+ dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
}
static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
@@ -1934,6 +1940,43 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
return min_cdclk;
}
+/*
+ * Note that this functions assumes that 0 is
+ * the lowest voltage value, and higher values
+ * correspond to increasingly higher voltages.
+ *
+ * Should that relationship no longer hold on
+ * future platforms this code will need to be
+ * adjusted.
+ */
+static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
+ u8 min_voltage_level;
+ int i;
+ enum pipe pipe;
+
+ memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
+ sizeof(state->min_voltage_level));
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ if (crtc_state->base.enable)
+ state->min_voltage_level[i] =
+ crtc_state->min_voltage_level;
+ else
+ state->min_voltage_level[i] = 0;
+ }
+
+ min_voltage_level = 0;
+ for_each_pipe(dev_priv, pipe)
+ min_voltage_level = max(state->min_voltage_level[pipe],
+ min_voltage_level);
+
+ return min_voltage_level;
+}
+
static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->dev);
@@ -2097,7 +2140,8 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
intel_state->cdclk.logical.vco = vco;
intel_state->cdclk.logical.cdclk = cdclk;
intel_state->cdclk.logical.voltage_level =
- cnl_calc_voltage_level(cdclk);
+ max(cnl_calc_voltage_level(cdclk),
+ cnl_compute_min_voltage_level(intel_state));
if (!intel_state->active_crtcs) {
cdclk = cnl_calc_cdclk(0);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 933c18fd4258..4c02930363a8 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2542,6 +2542,13 @@ bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
return false;
}
+void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
+ struct intel_crtc_state *crtc_state)
+{
+ if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
+ crtc_state->min_voltage_level = 2;
+}
+
void intel_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -2641,6 +2648,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
if (IS_GEN9_LP(dev_priv))
pipe_config->lane_lat_optim_mask =
bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
+
+ intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
}
static bool intel_ddi_compute_config(struct intel_encoder *encoder,
@@ -2667,6 +2676,8 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
pipe_config->lane_count);
+ intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
+
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1d2031a5f4bb..b5fa643e1812 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5938,6 +5938,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
dev_priv->min_cdclk[intel_crtc->pipe] = 0;
+ dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
}
/*
@@ -11289,6 +11290,8 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
+ PIPE_CONF_CHECK_I(min_voltage_level);
+
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
#undef PIPE_CONF_CHECK_P
@@ -11949,6 +11952,9 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
intel_state->cdclk.logical.cdclk,
intel_state->cdclk.actual.cdclk);
+ DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
+ intel_state->cdclk.logical.voltage_level,
+ intel_state->cdclk.actual.voltage_level);
} else {
to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
}
@@ -12517,6 +12523,9 @@ static int intel_atomic_commit(struct drm_device *dev,
if (intel_state->modeset) {
memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
sizeof(intel_state->min_cdclk));
+ memcpy(dev_priv->min_voltage_level,
+ intel_state->min_voltage_level,
+ sizeof(intel_state->min_voltage_level));
dev_priv->active_crtcs = intel_state->active_crtcs;
dev_priv->cdclk.logical = intel_state->cdclk.logical;
dev_priv->cdclk.actual = intel_state->cdclk.actual;
@@ -15027,6 +15036,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
}
dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
+ dev_priv->min_voltage_level[crtc->pipe] =
+ crtc_state->min_voltage_level;
intel_pipe_config_sanity_check(dev_priv, crtc_state);
}
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 772521440a9f..3d62c63c0763 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -34,6 +34,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
struct intel_digital_port *intel_dig_port = intel_mst->primary;
struct intel_dp *intel_dp = &intel_dig_port->dp;
@@ -87,6 +88,8 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
pipe_config->dp_m_n.tu = slots;
+ intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
+
return true;
}
@@ -307,6 +310,8 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
intel_dp_get_m_n(crtc, pipe_config);
intel_ddi_clock_get(&intel_dig_port->base, pipe_config);
+
+ intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
}
static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index df808a94c511..897fffe1ecd8 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2008,8 +2008,8 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
* requirement, follow the Display Voltage Frequency Switching
* Sequence Before Frequency Change
*
- * FIXME: (DVFS) is used to adjust the display voltage to match the
- * display clock frequencies
+ * Note: DVFS is actually handled via the cdclk code paths,
+ * hence we do nothing here.
*/
/* 6. Enable DPLL in DPLL_ENABLE. */
@@ -2030,8 +2030,8 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
* requirement, follow the Display Voltage Frequency Switching
* Sequence After Frequency Change
*
- * FIXME: (DVFS) is used to adjust the display voltage to match the
- * display clock frequencies
+ * Note: DVFS is actually handled via the cdclk code paths,
+ * hence we do nothing here.
*/
/*
@@ -2055,8 +2055,8 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
* requirement, follow the Display Voltage Frequency Switching
* Sequence Before Frequency Change
*
- * FIXME: (DVFS) is used to adjust the display voltage to match the
- * display clock frequencies
+ * Note: DVFS is actually handled via the cdclk code paths,
+ * hence we do nothing here.
*/
/* 3. Disable DPLL through DPLL_ENABLE. */
@@ -2077,8 +2077,8 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
* requirement, follow the Display Voltage Frequency Switching
* Sequence After Frequency Change
*
- * FIXME: (DVFS) is used to adjust the display voltage to match the
- * display clock frequencies
+ * Note: DVFS is actually handled via the cdclk code paths,
+ * hence we do nothing here.
*/
/* 6. Disable DPLL power in DPLL_ENABLE. */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a551aadb157b..3de8d98baed7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -386,6 +386,8 @@ struct intel_atomic_state {
unsigned int active_crtcs;
/* minimum acceptable cdclk for each pipe */
int min_cdclk[I915_MAX_PIPES];
+ /* minimum acceptable voltage level for each pipe */
+ u8 min_voltage_level[I915_MAX_PIPES];
struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
@@ -739,6 +741,9 @@ struct intel_crtc_state {
*/
uint8_t lane_lat_optim_mask;
+ /* minimum acceptable voltage level */
+ u8 min_voltage_level;
+
/* Panel fitter controls for gen2-gen4 + VLV */
struct {
u32 control;
@@ -1293,6 +1298,8 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
bool state);
+void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
+ struct intel_crtc_state *crtc_state);
u32 bxt_signal_levels(struct intel_dp *intel_dp);
uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
--
2.13.6
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 09/10] drm/i915: Sanity check cdclk in vlv_set_cdclk()
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (7 preceding siblings ...)
2017-10-24 9:52 ` [PATCH v4 08/10] drm/i915: Adjust system agent voltage on CNL if required by DDI ports Ville Syrjala
@ 2017-10-24 9:52 ` Ville Syrjala
2017-10-24 17:47 ` Rodrigo Vivi
2017-10-24 9:52 ` [PATCH 10/10] drm/i915: Perform a central cdclk state sanity check Ville Syrjala
` (8 subsequent siblings)
17 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjala @ 2017-10-24 9:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
chv_set_cdclk() sanity checks that the cdclk frequency is one of the
legal values. Do the same in the VLV function.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 4ca4a34b7bfa..fedfe3c720b6 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -520,6 +520,18 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
int cdclk = cdclk_state->cdclk;
u32 val, cmd = cdclk_state->voltage_level;
+ switch (cdclk) {
+ case 400000:
+ case 333333:
+ case 320000:
+ case 266667:
+ case 200000:
+ break;
+ default:
+ MISSING_CASE(cdclk);
+ return;
+ }
+
/* There are cases where we can end up here with power domains
* off and a CDCLK frequency other than the minimum, like when
* issuing a modeset without actually changing any display after
--
2.13.6
_______________________________________________
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 09/10] drm/i915: Sanity check cdclk in vlv_set_cdclk()
2017-10-24 9:52 ` [PATCH 09/10] drm/i915: Sanity check cdclk in vlv_set_cdclk() Ville Syrjala
@ 2017-10-24 17:47 ` Rodrigo Vivi
0 siblings, 0 replies; 22+ messages in thread
From: Rodrigo Vivi @ 2017-10-24 17:47 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Oct 24, 2017 at 09:52:15AM +0000, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> chv_set_cdclk() sanity checks that the cdclk frequency is one of the
> legal values. Do the same in the VLV function.
thanks for spliting in separated patch.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 4ca4a34b7bfa..fedfe3c720b6 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -520,6 +520,18 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
> int cdclk = cdclk_state->cdclk;
> u32 val, cmd = cdclk_state->voltage_level;
>
> + switch (cdclk) {
> + case 400000:
> + case 333333:
> + case 320000:
> + case 266667:
> + case 200000:
values match vlv_calc_cdclk
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> + break;
> + default:
> + MISSING_CASE(cdclk);
> + return;
> + }
> +
> /* There are cases where we can end up here with power domains
> * off and a CDCLK frequency other than the minimum, like when
> * issuing a modeset without actually changing any display after
> --
> 2.13.6
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 10/10] drm/i915: Perform a central cdclk state sanity check
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (8 preceding siblings ...)
2017-10-24 9:52 ` [PATCH 09/10] drm/i915: Sanity check cdclk in vlv_set_cdclk() Ville Syrjala
@ 2017-10-24 9:52 ` Ville Syrjala
2017-10-24 21:51 ` Rodrigo Vivi
2017-10-24 10:01 ` [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjälä
` (7 subsequent siblings)
17 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjala @ 2017-10-24 9:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
WARN if the cdclk state doesn't match what we expect after programming.
And let's remove the WARN from bdw_set_cdclk() that's trying to achieve
the same thing in a more limite fashion.
Also take the opportunity to refactor the code to use a common function
for dumping out a cdclk state.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 30 +++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_display.c | 3 +++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index fedfe3c720b6..51cd23dd8676 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -768,10 +768,6 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
intel_update_cdclk(dev_priv);
-
- WARN(cdclk != dev_priv->cdclk.hw.cdclk,
- "cdclk requested %d kHz but got %d kHz\n",
- cdclk, dev_priv->cdclk.hw.cdclk);
}
static int skl_calc_cdclk(int min_cdclk, int vco)
@@ -1068,6 +1064,8 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
goto sanitize;
intel_update_cdclk(dev_priv);
+ intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
+
/* Is PLL enabled and locked ? */
if (dev_priv->cdclk.hw.vco == 0 ||
dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
@@ -1407,6 +1405,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
u32 cdctl, expected;
intel_update_cdclk(dev_priv);
+ intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
if (dev_priv->cdclk.hw.vco == 0 ||
dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
@@ -1713,6 +1712,7 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
u32 cdctl, expected;
intel_update_cdclk(dev_priv);
+ intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
if (dev_priv->cdclk.hw.vco == 0 ||
dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
@@ -1826,6 +1826,14 @@ bool intel_cdclk_changed(const struct intel_cdclk_state *a,
a->voltage_level != b->voltage_level;
}
+void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
+ const char *context)
+{
+ DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, voltage level %d\n",
+ context, cdclk_state->cdclk, cdclk_state->vco,
+ cdclk_state->ref, cdclk_state->voltage_level);
+}
+
/**
* intel_set_cdclk - Push the CDCLK state to the hardware
* @dev_priv: i915 device
@@ -1843,11 +1851,15 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
return;
- DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz, voltage_level %d\n",
- cdclk_state->cdclk, cdclk_state->vco,
- cdclk_state->ref, cdclk_state->voltage_level);
+ intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
dev_priv->display.set_cdclk(dev_priv, cdclk_state);
+
+ if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
+ "cdclk state doesn't match!\n")) {
+ intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
+ intel_dump_cdclk_state(cdclk_state, "[sw state]");
+ }
}
static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
@@ -2280,10 +2292,6 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
{
dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
- DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
- dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
- dev_priv->cdclk.hw.ref);
-
/*
* 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
* Programmng [sic] note: bit[9:2] should be programmed to the number
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b5fa643e1812..7d7952b78a3b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8857,7 +8857,9 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
}
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
intel_update_cdclk(dev_priv);
+ intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
}
/*
@@ -14358,6 +14360,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev);
intel_update_cdclk(dev_priv);
+ intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
intel_init_clock_gating(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3de8d98baed7..3b4eafd39f55 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1336,6 +1336,8 @@ bool intel_cdclk_changed(const struct intel_cdclk_state *a,
const struct intel_cdclk_state *b);
void intel_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *cdclk_state);
+void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
+ const char *context);
/* intel_display.c */
void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
--
2.13.6
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 10/10] drm/i915: Perform a central cdclk state sanity check
2017-10-24 9:52 ` [PATCH 10/10] drm/i915: Perform a central cdclk state sanity check Ville Syrjala
@ 2017-10-24 21:51 ` Rodrigo Vivi
0 siblings, 0 replies; 22+ messages in thread
From: Rodrigo Vivi @ 2017-10-24 21:51 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Oct 24, 2017 at 09:52:16AM +0000, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> WARN if the cdclk state doesn't match what we expect after programming.
> And let's remove the WARN from bdw_set_cdclk() that's trying to achieve
> the same thing in a more limite fashion.
>
> Also take the opportunity to refactor the code to use a common function
> for dumping out a cdclk state.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
better code, better logs and right checks.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 30 +++++++++++++++++++-----------
> drivers/gpu/drm/i915/intel_display.c | 3 +++
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 24 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index fedfe3c720b6..51cd23dd8676 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -768,10 +768,6 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
> I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
>
> intel_update_cdclk(dev_priv);
> -
> - WARN(cdclk != dev_priv->cdclk.hw.cdclk,
> - "cdclk requested %d kHz but got %d kHz\n",
> - cdclk, dev_priv->cdclk.hw.cdclk);
> }
>
> static int skl_calc_cdclk(int min_cdclk, int vco)
> @@ -1068,6 +1064,8 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> goto sanitize;
>
> intel_update_cdclk(dev_priv);
> + intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> +
> /* Is PLL enabled and locked ? */
> if (dev_priv->cdclk.hw.vco == 0 ||
> dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
> @@ -1407,6 +1405,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
> u32 cdctl, expected;
>
> intel_update_cdclk(dev_priv);
> + intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
>
> if (dev_priv->cdclk.hw.vco == 0 ||
> dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
> @@ -1713,6 +1712,7 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> u32 cdctl, expected;
>
> intel_update_cdclk(dev_priv);
> + intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
>
> if (dev_priv->cdclk.hw.vco == 0 ||
> dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
> @@ -1826,6 +1826,14 @@ bool intel_cdclk_changed(const struct intel_cdclk_state *a,
> a->voltage_level != b->voltage_level;
> }
>
> +void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
> + const char *context)
> +{
> + DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, voltage level %d\n",
> + context, cdclk_state->cdclk, cdclk_state->vco,
> + cdclk_state->ref, cdclk_state->voltage_level);
> +}
> +
> /**
> * intel_set_cdclk - Push the CDCLK state to the hardware
> * @dev_priv: i915 device
> @@ -1843,11 +1851,15 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
> if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
> return;
>
> - DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz, voltage_level %d\n",
> - cdclk_state->cdclk, cdclk_state->vco,
> - cdclk_state->ref, cdclk_state->voltage_level);
> + intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
>
> dev_priv->display.set_cdclk(dev_priv, cdclk_state);
> +
> + if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
> + "cdclk state doesn't match!\n")) {
> + intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
> + intel_dump_cdclk_state(cdclk_state, "[sw state]");
> + }
> }
>
> static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
> @@ -2280,10 +2292,6 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
> {
> dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
>
> - DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
> - dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
> - dev_priv->cdclk.hw.ref);
> -
> /*
> * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
> * Programmng [sic] note: bit[9:2] should be programmed to the number
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b5fa643e1812..7d7952b78a3b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8857,7 +8857,9 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
> }
>
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +
> intel_update_cdclk(dev_priv);
> + intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> }
>
> /*
> @@ -14358,6 +14360,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> intel_update_cdclk(dev_priv);
> + intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
>
> intel_init_clock_gating(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 3de8d98baed7..3b4eafd39f55 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1336,6 +1336,8 @@ bool intel_cdclk_changed(const struct intel_cdclk_state *a,
> const struct intel_cdclk_state *b);
> void intel_set_cdclk(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_state *cdclk_state);
> +void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
> + const char *context);
>
> /* intel_display.c */
> void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
> --
> 2.13.6
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 00/10] drm/i915: CNL DVFS thing
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (9 preceding siblings ...)
2017-10-24 9:52 ` [PATCH 10/10] drm/i915: Perform a central cdclk state sanity check Ville Syrjala
@ 2017-10-24 10:01 ` Ville Syrjälä
2017-10-24 11:12 ` ✗ Fi.CI.BAT: failure for drm/i915: CNL DVFS thing (rev7) Patchwork
` (6 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjälä @ 2017-10-24 10:01 UTC (permalink / raw)
To: intel-gfx
On Tue, Oct 24, 2017 at 12:52:06PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> New version of the CNL DVFS series. Everything from the previous series
> (first 8 patches) are already reviewed. I slapped on two additional patches
> that fell out from the review of the first series.
Oh, and I forgot to mention that the other main change from the previous
series is that we now talk about "voltage_level" rather than "voltage"
everywhere. That required changes to almost all the patches, hence I
sent out a new full series.
>
> Entire series available here:
> git://github.com/vsyrjala/linux.git dvfs_voltage_6
>
> Ville Syrjälä (10):
> drm/i915: Clean up some cdclk switch statements
> drm/i915: Start tracking voltage level in the cdclk state
> drm/i915: Use cdclk_state->voltage on VLV/CHV
> drm/i915: Use cdclk_state->voltage on BDW
> drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL
> drm/i915: Use cdclk_state->voltage on BXT/GLK
> drm/i915: Use cdclk_state->voltage on CNL
> drm/i915: Adjust system agent voltage on CNL if required by DDI ports
> drm/i915: Sanity check cdclk in vlv_set_cdclk()
> drm/i915: Perform a central cdclk state sanity check
>
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/intel_cdclk.c | 377 ++++++++++++++++++++++++--------
> drivers/gpu/drm/i915/intel_ddi.c | 11 +
> drivers/gpu/drm/i915/intel_display.c | 22 +-
> drivers/gpu/drm/i915/intel_dp_mst.c | 5 +
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 +-
> drivers/gpu/drm/i915/intel_drv.h | 13 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +-
> 8 files changed, 342 insertions(+), 108 deletions(-)
>
> --
> 2.13.6
--
Ville Syrjälä
Intel OTC
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915: CNL DVFS thing (rev7)
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (10 preceding siblings ...)
2017-10-24 10:01 ` [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjälä
@ 2017-10-24 11:12 ` Patchwork
2017-10-24 13:23 ` Patchwork
` (5 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2017-10-24 11:12 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: CNL DVFS thing (rev7)
URL : https://patchwork.freedesktop.org/series/32247/
State : failure
== Summary ==
Series 32247v7 drm/i915: CNL DVFS thing
https://patchwork.freedesktop.org/api/1.0/series/32247/revisions/7/mbox/
Test chamelium:
Subgroup dp-crc-fast:
pass -> FAIL (fi-kbl-7500u) fdo#102514
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-skl-6700hq)
fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:442s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:453s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:370s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:522s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:264s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:498s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:500s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:493s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:476s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:556s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:420s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:249s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:578s
fi-glk-dsi total:289 pass:258 dwarn:0 dfail:0 fail:1 skip:30 time:487s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:425s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:427s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:427s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:487s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:458s
fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:482s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:576s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:474s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:584s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:544s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:455s
fi-skl-6700hq total:246 pass:221 dwarn:0 dfail:0 fail:0 skip:24
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:520s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:501s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:456s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:563s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:414s
5c82a37eff83ab4e60e760fbaf03db5ba0563497 drm-tip: 2017y-10m-23d-18h-06m-28s UTC integration manifest
ec580f178e62 drm/i915: Perform a central cdclk state sanity check
394fd358e1f3 drm/i915: Sanity check cdclk in vlv_set_cdclk()
c335ee11442a drm/i915: Adjust system agent voltage on CNL if required by DDI ports
8c83dfa21c6d drm/i915: Use cdclk_state->voltage on CNL
65271db422a1 drm/i915: Use cdclk_state->voltage on BXT/GLK
eb7c4d1139ab drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL
deb10eabc15e drm/i915: Use cdclk_state->voltage on BDW
e6ff0c197dd6 drm/i915: Use cdclk_state->voltage on VLV/CHV
cbb3881aac06 drm/i915: Start tracking voltage level in the cdclk state
fbbb9cbf05b7 drm/i915: Clean up some cdclk switch statements
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6153/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915: CNL DVFS thing (rev7)
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (11 preceding siblings ...)
2017-10-24 11:12 ` ✗ Fi.CI.BAT: failure for drm/i915: CNL DVFS thing (rev7) Patchwork
@ 2017-10-24 13:23 ` Patchwork
2017-10-24 17:01 ` ✗ Fi.CI.BAT: warning " Patchwork
` (4 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2017-10-24 13:23 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: CNL DVFS thing (rev7)
URL : https://patchwork.freedesktop.org/series/32247/
State : failure
== Summary ==
Series 32247v7 drm/i915: CNL DVFS thing
https://patchwork.freedesktop.org/api/1.0/series/32247/revisions/7/mbox/
Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-legacy:
pass -> INCOMPLETE (fi-kbl-7500u)
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:441s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:450s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:371s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:533s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:261s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:496s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:501s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:496s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:481s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:549s
fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:614s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:413s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:250s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:582s
fi-glk-dsi total:289 pass:258 dwarn:0 dfail:0 fail:1 skip:30 time:490s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:430s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:430s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:431s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:497s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:462s
fi-kbl-7500u total:212 pass:194 dwarn:1 dfail:0 fail:0 skip:16
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:578s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:478s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:591s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:542s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:445s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:647s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:534s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:502s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:456s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:573s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:424s
5c82a37eff83ab4e60e760fbaf03db5ba0563497 drm-tip: 2017y-10m-23d-18h-06m-28s UTC integration manifest
79e92e64702f drm/i915: Perform a central cdclk state sanity check
4daf11cee53f drm/i915: Sanity check cdclk in vlv_set_cdclk()
eaafe95996e5 drm/i915: Adjust system agent voltage on CNL if required by DDI ports
2369a11b7117 drm/i915: Use cdclk_state->voltage on CNL
19680061ffe1 drm/i915: Use cdclk_state->voltage on BXT/GLK
7360a7ab6801 drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL
1e3a3cbae375 drm/i915: Use cdclk_state->voltage on BDW
9cbcbfc9745e drm/i915: Use cdclk_state->voltage on VLV/CHV
ade92daa583d drm/i915: Start tracking voltage level in the cdclk state
df545f1cec2c drm/i915: Clean up some cdclk switch statements
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6158/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Fi.CI.BAT: warning for drm/i915: CNL DVFS thing (rev7)
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (12 preceding siblings ...)
2017-10-24 13:23 ` Patchwork
@ 2017-10-24 17:01 ` Patchwork
2017-10-24 18:30 ` ✗ Fi.CI.BAT: failure " Patchwork
` (3 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2017-10-24 17:01 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: CNL DVFS thing (rev7)
URL : https://patchwork.freedesktop.org/series/32247/
State : warning
== Summary ==
Series 32247v7 drm/i915: CNL DVFS thing
https://patchwork.freedesktop.org/api/1.0/series/32247/revisions/7/mbox/
Test gem_exec_reloc:
Subgroup basic-gtt-active:
dmesg-warn -> PASS (fi-gdg-551) fdo#102582 +5
Subgroup basic-write-cpu-active:
skip -> PASS (fi-gdg-551)
Subgroup basic-write-gtt-active:
skip -> PASS (fi-gdg-551) fdo#102582
Subgroup basic-softpin:
skip -> PASS (fi-gdg-551)
Test gem_linear_blits:
Subgroup basic:
skip -> PASS (fi-gdg-551)
Test gem_render_linear_blits:
Subgroup basic:
skip -> PASS (fi-gdg-551)
Test gem_render_tiled_blits:
Subgroup basic:
skip -> PASS (fi-gdg-551)
Test gem_sync:
Subgroup basic-all:
skip -> PASS (fi-gdg-551)
Subgroup basic-each:
skip -> PASS (fi-gdg-551)
Subgroup basic-many-each:
skip -> PASS (fi-gdg-551)
Subgroup basic-store-each:
skip -> PASS (fi-gdg-551)
Test gem_tiled_blits:
Subgroup basic:
skip -> PASS (fi-gdg-551)
Test gem_tiled_fence_blits:
Subgroup basic:
skip -> PASS (fi-gdg-551)
Test gem_wait:
Subgroup basic-busy-all:
skip -> PASS (fi-gdg-551)
Subgroup basic-wait-all:
skip -> PASS (fi-gdg-551)
Subgroup basic-await-all:
skip -> PASS (fi-gdg-551)
Test kms_busy:
Subgroup basic-flip-a:
skip -> PASS (fi-gdg-551) fdo#102654 +1
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
skip -> FAIL (fi-gdg-551) fdo#102618
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-b:
pass -> SKIP (fi-hsw-4770r)
Test drv_module_reload:
Subgroup basic-reload:
pass -> DMESG-WARN (fi-bsw-n3050)
fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#102654 https://bugs.freedesktop.org/show_bug.cgi?id=102654
fdo#102618 https://bugs.freedesktop.org/show_bug.cgi?id=102618
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:451s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:460s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:373s
fi-bsw-n3050 total:289 pass:242 dwarn:1 dfail:0 fail:0 skip:46 time:510s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:262s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:501s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:492s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:491s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:475s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:554s
fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:622s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:419s
fi-gdg-551 total:289 pass:177 dwarn:1 dfail:0 fail:2 skip:109 time:256s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:575s
fi-glk-dsi total:289 pass:258 dwarn:0 dfail:0 fail:1 skip:30 time:490s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:427s
fi-hsw-4770r total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:431s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:431s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:489s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:459s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:487s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:574s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:474s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:586s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:549s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:449s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:647s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:521s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:495s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:460s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:565s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:421s
bcee836068d98bd2aaa5d64124c5994acce6a6c4 drm-tip: 2017y-10m-24d-15h-00m-14s UTC integration manifest
831777b5ab5f drm/i915: Perform a central cdclk state sanity check
9f75cbcc04ef drm/i915: Sanity check cdclk in vlv_set_cdclk()
7dc2a49fcb26 drm/i915: Adjust system agent voltage on CNL if required by DDI ports
7fdc76a28bbd drm/i915: Use cdclk_state->voltage on CNL
14d1ef26ab51 drm/i915: Use cdclk_state->voltage on BXT/GLK
2af752b4f041 drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL
dd3b5c015e06 drm/i915: Use cdclk_state->voltage on BDW
19c7073c4833 drm/i915: Use cdclk_state->voltage on VLV/CHV
b0aee071504b drm/i915: Start tracking voltage level in the cdclk state
4acb9fc6cd4c drm/i915: Clean up some cdclk switch statements
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6166/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915: CNL DVFS thing (rev7)
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (13 preceding siblings ...)
2017-10-24 17:01 ` ✗ Fi.CI.BAT: warning " Patchwork
@ 2017-10-24 18:30 ` Patchwork
2017-10-24 20:08 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2017-10-24 18:30 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: CNL DVFS thing (rev7)
URL : https://patchwork.freedesktop.org/series/32247/
State : failure
== Summary ==
Series 32247v7 drm/i915: CNL DVFS thing
https://patchwork.freedesktop.org/api/1.0/series/32247/revisions/7/mbox/
Test gem_exec_reloc:
Subgroup basic-gtt-active:
dmesg-warn -> PASS (fi-gdg-551) fdo#102582 +5
Subgroup basic-write-cpu-active:
skip -> PASS (fi-gdg-551)
Subgroup basic-write-gtt-active:
skip -> PASS (fi-gdg-551) fdo#102582
Subgroup basic-softpin:
skip -> PASS (fi-gdg-551)
Test gem_linear_blits:
Subgroup basic:
skip -> PASS (fi-gdg-551)
Test gem_render_linear_blits:
Subgroup basic:
skip -> PASS (fi-gdg-551)
Test gem_render_tiled_blits:
Subgroup basic:
skip -> PASS (fi-gdg-551)
Test gem_sync:
Subgroup basic-all:
skip -> PASS (fi-gdg-551)
Subgroup basic-each:
skip -> PASS (fi-gdg-551)
Subgroup basic-many-each:
skip -> PASS (fi-gdg-551)
Subgroup basic-store-each:
skip -> PASS (fi-gdg-551)
Test gem_tiled_blits:
Subgroup basic:
skip -> PASS (fi-gdg-551)
Test gem_tiled_fence_blits:
Subgroup basic:
skip -> PASS (fi-gdg-551)
Test gem_wait:
Subgroup basic-busy-all:
skip -> PASS (fi-gdg-551)
Subgroup basic-wait-all:
skip -> PASS (fi-gdg-551)
Subgroup basic-await-all:
skip -> PASS (fi-gdg-551)
Test kms_busy:
Subgroup basic-flip-a:
skip -> PASS (fi-gdg-551) fdo#102654 +1
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
skip -> PASS (fi-gdg-551) fdo#102618
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> INCOMPLETE (fi-cnl-y)
fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#102654 https://bugs.freedesktop.org/show_bug.cgi?id=102654
fdo#102618 https://bugs.freedesktop.org/show_bug.cgi?id=102618
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:440s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:446s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:371s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:530s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:265s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:497s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:507s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:493s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:479s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:556s
fi-cnl-y total:245 pass:220 dwarn:0 dfail:0 fail:0 skip:24
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:414s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:249s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:587s
fi-glk-dsi total:289 pass:258 dwarn:0 dfail:0 fail:1 skip:30 time:486s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:432s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:433s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:436s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:491s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:456s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:487s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:569s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:475s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:577s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:541s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:452s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:642s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:516s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:497s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:453s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:562s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:414s
bcee836068d98bd2aaa5d64124c5994acce6a6c4 drm-tip: 2017y-10m-24d-15h-00m-14s UTC integration manifest
f96a5989c6bf drm/i915: Perform a central cdclk state sanity check
854d9bec1043 drm/i915: Sanity check cdclk in vlv_set_cdclk()
0eb7b8d4ee9c drm/i915: Adjust system agent voltage on CNL if required by DDI ports
c16401289eaa drm/i915: Use cdclk_state->voltage on CNL
d304fb574b10 drm/i915: Use cdclk_state->voltage on BXT/GLK
6ad4b659a241 drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL
45cfc6c0d92c drm/i915: Use cdclk_state->voltage on BDW
421f2d442c03 drm/i915: Use cdclk_state->voltage on VLV/CHV
b7ace80f089a drm/i915: Start tracking voltage level in the cdclk state
8ac5f67be0b0 drm/i915: Clean up some cdclk switch statements
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6169/
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: CNL DVFS thing (rev7)
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (14 preceding siblings ...)
2017-10-24 18:30 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2017-10-24 20:08 ` Patchwork
2017-10-25 6:15 ` Saarinen, Jani
2017-10-24 21:29 ` ✓ Fi.CI.IGT: " Patchwork
2017-10-25 13:22 ` [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjälä
17 siblings, 1 reply; 22+ messages in thread
From: Patchwork @ 2017-10-24 20:08 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: CNL DVFS thing (rev7)
URL : https://patchwork.freedesktop.org/series/32247/
State : success
== Summary ==
Series 32247v7 drm/i915: CNL DVFS thing
https://patchwork.freedesktop.org/api/1.0/series/32247/revisions/7/mbox/
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:441s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:371s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:525s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:262s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:496s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:497s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:492s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:473s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:545s
fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:595s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:406s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:247s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:578s
fi-glk-dsi total:289 pass:258 dwarn:0 dfail:0 fail:1 skip:30 time:489s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:429s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:426s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:428s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:492s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:456s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:492s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:572s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:468s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:582s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:557s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:450s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:643s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:519s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:494s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:453s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:558s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:423s
fi-bdw-gvtdvm failed to connect after reboot
4971297c57bdd02d8f64cddc9d44c9db6b3478b3 drm-tip: 2017y-10m-24d-17h-29m-57s UTC integration manifest
6a8a266dec20 drm/i915: Perform a central cdclk state sanity check
4454cb468b48 drm/i915: Sanity check cdclk in vlv_set_cdclk()
47ba882711ee drm/i915: Adjust system agent voltage on CNL if required by DDI ports
6c2a7a6e4a9b drm/i915: Use cdclk_state->voltage on CNL
6c21d2efb5e2 drm/i915: Use cdclk_state->voltage on BXT/GLK
c7372e650ad6 drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL
6013e43d0158 drm/i915: Use cdclk_state->voltage on BDW
ff7c375d3eb6 drm/i915: Use cdclk_state->voltage on VLV/CHV
59694b6d8bbc drm/i915: Start tracking voltage level in the cdclk state
27a1c98e8261 drm/i915: Clean up some cdclk switch statements
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6171/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: CNL DVFS thing (rev7)
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (15 preceding siblings ...)
2017-10-24 20:08 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2017-10-24 21:29 ` Patchwork
2017-10-25 13:22 ` [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjälä
17 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2017-10-24 21:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: CNL DVFS thing (rev7)
URL : https://patchwork.freedesktop.org/series/32247/
State : success
== Summary ==
Test kms_busy:
Subgroup extended-modeset-hang-newfb-with-reset-render-A:
dmesg-warn -> PASS (shard-hsw) fdo#102249 +2
Subgroup extended-modeset-hang-newfb-with-reset-render-B:
dmesg-warn -> PASS (shard-hsw) fdo#103038
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
Test kms_flip:
Subgroup dpms-vs-vblank-race:
fail -> PASS (shard-hsw) fdo#103060
Subgroup flip-vs-expired-vblank-interruptible:
pass -> FAIL (shard-hsw) fdo#102887
Test drv_module_reload:
Subgroup basic-no-display:
pass -> DMESG-WARN (shard-hsw) fdo#102707
fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249
fdo#103038 https://bugs.freedesktop.org/show_bug.cgi?id=103038
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
shard-hsw total:2540 pass:1430 dwarn:3 dfail:0 fail:10 skip:1097 time:9212s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6171/shards.html
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^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v2 00/10] drm/i915: CNL DVFS thing
2017-10-24 9:52 [PATCH v2 00/10] drm/i915: CNL DVFS thing Ville Syrjala
` (16 preceding siblings ...)
2017-10-24 21:29 ` ✓ Fi.CI.IGT: " Patchwork
@ 2017-10-25 13:22 ` Ville Syrjälä
17 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjälä @ 2017-10-25 13:22 UTC (permalink / raw)
To: intel-gfx
On Tue, Oct 24, 2017 at 12:52:06PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> New version of the CNL DVFS series. Everything from the previous series
> (first 8 patches) are already reviewed. I slapped on two additional patches
> that fell out from the review of the first series.
>
> Entire series available here:
> git://github.com/vsyrjala/linux.git dvfs_voltage_6
>
> Ville Syrjälä (10):
> drm/i915: Clean up some cdclk switch statements
> drm/i915: Start tracking voltage level in the cdclk state
> drm/i915: Use cdclk_state->voltage on VLV/CHV
> drm/i915: Use cdclk_state->voltage on BDW
> drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL
> drm/i915: Use cdclk_state->voltage on BXT/GLK
> drm/i915: Use cdclk_state->voltage on CNL
> drm/i915: Adjust system agent voltage on CNL if required by DDI ports
> drm/i915: Sanity check cdclk in vlv_set_cdclk()
> drm/i915: Perform a central cdclk state sanity check
Entire series pushed to dinq. Thanks for the review.
>
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/intel_cdclk.c | 377 ++++++++++++++++++++++++--------
> drivers/gpu/drm/i915/intel_ddi.c | 11 +
> drivers/gpu/drm/i915/intel_display.c | 22 +-
> drivers/gpu/drm/i915/intel_dp_mst.c | 5 +
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 +-
> drivers/gpu/drm/i915/intel_drv.h | 13 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +-
> 8 files changed, 342 insertions(+), 108 deletions(-)
>
> --
> 2.13.6
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 22+ messages in thread