* [PATCH 1/3] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3.
@ 2017-10-27 7:59 Maarten Lankhorst
2017-10-27 7:59 ` [PATCH 2/3] drm/i915: Calculate g4x intermediate watermarks correctly Maarten Lankhorst
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Maarten Lankhorst @ 2017-10-27 7:59 UTC (permalink / raw)
To: intel-gfx
The watermarks it should calculate against are the old optimal watermarks.
The currently active crtc watermarks are pure fiction, and are invalid in
case of a nonblocking modeset, page flip enabling/disabling planes or any
other reason.
When the crtc is disabled or during a modeset the intermediate watermarks
don't need to be programmed separately, and could be directly assigned
to the optimal watermarks.
CXSR must always be disabled in the intermediate case for modesets, else
we get a WARN for vblank wait timeout.
Also rename crtc_state to new_crtc_state, to distinguish it from the old state.
Changes since v1:
- Use intel_atomic_get_old_crtc_state. (ville)
Changes since v2:
- Always unset cxsr during modeset.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 07118c0b69d3..560042b91032 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2029,16 +2029,27 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
static int vlv_compute_intermediate_wm(struct drm_device *dev,
struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc_state *new_crtc_state)
{
- struct vlv_wm_state *intermediate = &crtc_state->wm.vlv.intermediate;
- const struct vlv_wm_state *optimal = &crtc_state->wm.vlv.optimal;
- const struct vlv_wm_state *active = &crtc->wm.active.vlv;
+ struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
+ const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
+ struct intel_atomic_state *intel_state =
+ to_intel_atomic_state(new_crtc_state->base.state);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(intel_state, crtc);
+ const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
int level;
+ if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
+ *intermediate = *optimal;
+
+ intermediate->cxsr = false;
+ goto out;
+ }
+
intermediate->num_levels = min(optimal->num_levels, active->num_levels);
intermediate->cxsr = optimal->cxsr && active->cxsr &&
- !crtc_state->disable_cxsr;
+ !new_crtc_state->disable_cxsr;
for (level = 0; level < intermediate->num_levels; level++) {
enum plane_id plane_id;
@@ -2057,12 +2068,13 @@ static int vlv_compute_intermediate_wm(struct drm_device *dev,
vlv_invalidate_wms(crtc, intermediate, level);
+out:
/*
* If our intermediate WM are identical to the final WM, then we can
* omit the post-vblank programming; only update if it's different.
*/
if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
- crtc_state->wm.need_postvbl_update = true;
+ new_crtc_state->wm.need_postvbl_update = true;
return 0;
}
--
2.14.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] drm/i915: Calculate g4x intermediate watermarks correctly
2017-10-27 7:59 [PATCH 1/3] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3 Maarten Lankhorst
@ 2017-10-27 7:59 ` Maarten Lankhorst
2017-10-27 7:59 ` [PATCH 3/3] drm/i915: Clean up skip_intermediate_wm handling Maarten Lankhorst
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Maarten Lankhorst @ 2017-10-27 7:59 UTC (permalink / raw)
To: intel-gfx
The watermarks it should calculate against are the old optimal watermarks.
The currently active crtc watermarks are pure fiction, and are invalid in
case of a nonblocking modeset, page flip enabling/disabling planes or any
other reason.
When the crtc is disabled or during a modeset the intermediate watermarks
don't need to be programmed separately, and could be directly assigned
to the optimal watermarks.
CXSR must always be disabled in the intermediate case for modesets,
else we get a WARN for vblank wait timeout.
Also rename crtc_state to new_crtc_state, to distinguish it from the old state.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 27 ++++++++++++++++++++-------
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 560042b91032..a9e7683d5a0d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1409,17 +1409,29 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
static int g4x_compute_intermediate_wm(struct drm_device *dev,
struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc_state *new_crtc_state)
{
- struct g4x_wm_state *intermediate = &crtc_state->wm.g4x.intermediate;
- const struct g4x_wm_state *optimal = &crtc_state->wm.g4x.optimal;
- const struct g4x_wm_state *active = &crtc->wm.active.g4x;
+ struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
+ const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
+ struct intel_atomic_state *intel_state =
+ to_intel_atomic_state(new_crtc_state->base.state);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(intel_state, crtc);
+ const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
enum plane_id plane_id;
+ if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
+ *intermediate = *optimal;
+
+ intermediate->cxsr = false;
+ intermediate->hpll_en = false;
+ goto out;
+ }
+
intermediate->cxsr = optimal->cxsr && active->cxsr &&
- !crtc_state->disable_cxsr;
+ !new_crtc_state->disable_cxsr;
intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&
- !crtc_state->disable_cxsr;
+ !new_crtc_state->disable_cxsr;
intermediate->fbc_en = optimal->fbc_en && active->fbc_en;
for_each_plane_id_on_crtc(crtc, plane_id) {
@@ -1461,12 +1473,13 @@ static int g4x_compute_intermediate_wm(struct drm_device *dev,
WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
intermediate->fbc_en && intermediate->hpll_en);
+out:
/*
* If our intermediate WM are identical to the final WM, then we can
* omit the post-vblank programming; only update if it's different.
*/
if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
- crtc_state->wm.need_postvbl_update = true;
+ new_crtc_state->wm.need_postvbl_update = true;
return 0;
}
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] drm/i915: Clean up skip_intermediate_wm handling
2017-10-27 7:59 [PATCH 1/3] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3 Maarten Lankhorst
2017-10-27 7:59 ` [PATCH 2/3] drm/i915: Calculate g4x intermediate watermarks correctly Maarten Lankhorst
@ 2017-10-27 7:59 ` Maarten Lankhorst
2017-10-27 12:01 ` Ville Syrjälä
2017-10-27 8:23 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3 Patchwork
2017-10-27 9:26 ` ✓ Fi.CI.IGT: " Patchwork
3 siblings, 1 reply; 6+ messages in thread
From: Maarten Lankhorst @ 2017-10-27 7:59 UTC (permalink / raw)
To: intel-gfx
Originally we implemented skip_intermediate_wm to fix up garbage
watermarks for ILK watermarks that are insane, but it makes sense
to extend this to all platforms with 2-style watermark programming.
We don't know what the previous contents of the watermarks are, and they
could be something entirely garbage when the pipe is off, so computing
them should only be based on the new state.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 13 +++----------
drivers/gpu/drm/i915/intel_pm.c | 9 ++++++---
2 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a369b35d044d..09313af4d64d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3571,8 +3571,7 @@ __intel_display_resume(struct drm_device *dev,
}
/* ignore any reset values/BIOS leftovers in the WM registers */
- if (!HAS_GMCH_DISPLAY(to_i915(dev)))
- to_intel_atomic_state(state)->skip_intermediate_wm = true;
+ to_intel_atomic_state(state)->skip_intermediate_wm = true;
ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
@@ -10379,7 +10378,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_crtc_state *pipe_config =
to_intel_crtc_state(crtc_state);
- struct drm_atomic_state *state = crtc_state->state;
int ret;
bool mode_changed = needs_modeset(crtc_state);
@@ -10416,8 +10414,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
}
}
- if (dev_priv->display.compute_intermediate_wm &&
- !to_intel_atomic_state(state)->skip_intermediate_wm) {
+ if (dev_priv->display.compute_intermediate_wm) {
if (WARN_ON(!dev_priv->display.compute_pipe_wm))
return 0;
@@ -10433,9 +10430,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
return ret;
}
- } else if (dev_priv->display.compute_intermediate_wm) {
- if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
- pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
}
if (INTEL_GEN(dev_priv) >= 9) {
@@ -14416,8 +14410,7 @@ static void sanitize_watermarks(struct drm_device *dev)
* intermediate watermarks (since we don't trust the current
* watermarks).
*/
- if (!HAS_GMCH_DISPLAY(dev_priv))
- intel_state->skip_intermediate_wm = true;
+ intel_state->skip_intermediate_wm = true;
ret = intel_atomic_check(dev, state);
if (ret) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a9e7683d5a0d..346c30a222cd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1420,7 +1420,8 @@ static int g4x_compute_intermediate_wm(struct drm_device *dev,
const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
enum plane_id plane_id;
- if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
+ if (!new_crtc_state->base.active || intel_state->skip_intermediate_wm ||
+ drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
*intermediate = *optimal;
intermediate->cxsr = false;
@@ -2053,7 +2054,8 @@ static int vlv_compute_intermediate_wm(struct drm_device *dev,
const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
int level;
- if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
+ if (!new_crtc_state->base.active || intel_state->skip_intermediate_wm ||
+ drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
*intermediate = *optimal;
intermediate->cxsr = false;
@@ -3162,7 +3164,8 @@ static int ilk_compute_intermediate_wm(struct drm_device *dev,
* and after the vblank.
*/
*a = newstate->wm.ilk.optimal;
- if (!newstate->base.active || drm_atomic_crtc_needs_modeset(&newstate->base))
+ if (!newstate->base.active || intel_state->skip_intermediate_wm ||
+ drm_atomic_crtc_needs_modeset(&newstate->base))
return 0;
a->pipe_enabled |= b->pipe_enabled;
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3.
2017-10-27 7:59 [PATCH 1/3] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3 Maarten Lankhorst
2017-10-27 7:59 ` [PATCH 2/3] drm/i915: Calculate g4x intermediate watermarks correctly Maarten Lankhorst
2017-10-27 7:59 ` [PATCH 3/3] drm/i915: Clean up skip_intermediate_wm handling Maarten Lankhorst
@ 2017-10-27 8:23 ` Patchwork
2017-10-27 9:26 ` ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-10-27 8:23 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3.
URL : https://patchwork.freedesktop.org/series/32739/
State : success
== Summary ==
Series 32739v1 series starting with [1/3] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3.
https://patchwork.freedesktop.org/api/1.0/series/32739/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS (fi-byt-j1900) fdo#101705
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:441s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:454s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:371s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:528s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:263s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:500s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:495s
fi-byt-j1900 total:289 pass:254 dwarn:0 dfail:0 fail:0 skip:35 time:495s
fi-byt-n2820 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:480s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:549s
fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:626s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:419s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:250s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:573s
fi-glk-dsi total:289 pass:258 dwarn:0 dfail:0 fail:1 skip:30 time:489s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:430s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:435s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:431s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:487s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:461s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:492s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:576s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:474s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:581s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:543s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:451s
fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:591s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:643s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:517s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:504s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:457s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:556s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:416s
1db1a27d38d789ce2886db512828ae306c998bc3 drm-tip: 2017y-10m-27d-07h-23m-09s UTC integration manifest
b769ce7c089a drm/i915: Clean up skip_intermediate_wm handling
d56ec0fb289c drm/i915: Calculate g4x intermediate watermarks correctly
7ab8f9b9a33f drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6223/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3.
2017-10-27 7:59 [PATCH 1/3] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3 Maarten Lankhorst
` (2 preceding siblings ...)
2017-10-27 8:23 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3 Patchwork
@ 2017-10-27 9:26 ` Patchwork
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-10-27 9:26 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3.
URL : https://patchwork.freedesktop.org/series/32739/
State : success
== Summary ==
Test kms_flip:
Subgroup dpms-vs-vblank-race:
fail -> PASS (shard-hsw) fdo#103060
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
shard-hsw total:2539 pass:1434 dwarn:0 dfail:0 fail:8 skip:1097 time:9198s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6223/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] drm/i915: Clean up skip_intermediate_wm handling
2017-10-27 7:59 ` [PATCH 3/3] drm/i915: Clean up skip_intermediate_wm handling Maarten Lankhorst
@ 2017-10-27 12:01 ` Ville Syrjälä
0 siblings, 0 replies; 6+ messages in thread
From: Ville Syrjälä @ 2017-10-27 12:01 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 27, 2017 at 09:59:47AM +0200, Maarten Lankhorst wrote:
> Originally we implemented skip_intermediate_wm to fix up garbage
> watermarks for ILK watermarks that are insane, but it makes sense
> to extend this to all platforms with 2-style watermark programming.
I don't particularly like skip_intermediate_wm. g4x/vlv/chv watermarks
get sanitized in a different way, so this is not needed unless something
is really seriously fscked up. So I think I'd rather change ILK+ to
sanitize the same way and kill skip_intermediate_wm.
If the current watermarks are total garbage (which I doubt), then I
think the safest solution would be to force a modeset at that point
rather than hoping that just smashing in new watermarks is going to save
the day. Running with bad watermarks could even mean that the pipe has
already died (at least on some platforms).
>
> We don't know what the previous contents of the watermarks are, and they
> could be something entirely garbage when the pipe is off, so computing
> them should only be based on the new state.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 13 +++----------
> drivers/gpu/drm/i915/intel_pm.c | 9 ++++++---
> 2 files changed, 9 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a369b35d044d..09313af4d64d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3571,8 +3571,7 @@ __intel_display_resume(struct drm_device *dev,
> }
>
> /* ignore any reset values/BIOS leftovers in the WM registers */
> - if (!HAS_GMCH_DISPLAY(to_i915(dev)))
> - to_intel_atomic_state(state)->skip_intermediate_wm = true;
> + to_intel_atomic_state(state)->skip_intermediate_wm = true;
>
> ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
>
> @@ -10379,7 +10378,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_crtc_state *pipe_config =
> to_intel_crtc_state(crtc_state);
> - struct drm_atomic_state *state = crtc_state->state;
> int ret;
> bool mode_changed = needs_modeset(crtc_state);
>
> @@ -10416,8 +10414,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> }
> }
>
> - if (dev_priv->display.compute_intermediate_wm &&
> - !to_intel_atomic_state(state)->skip_intermediate_wm) {
> + if (dev_priv->display.compute_intermediate_wm) {
> if (WARN_ON(!dev_priv->display.compute_pipe_wm))
> return 0;
>
> @@ -10433,9 +10430,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
> return ret;
> }
> - } else if (dev_priv->display.compute_intermediate_wm) {
> - if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
> - pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
> }
>
> if (INTEL_GEN(dev_priv) >= 9) {
> @@ -14416,8 +14410,7 @@ static void sanitize_watermarks(struct drm_device *dev)
> * intermediate watermarks (since we don't trust the current
> * watermarks).
> */
> - if (!HAS_GMCH_DISPLAY(dev_priv))
> - intel_state->skip_intermediate_wm = true;
> + intel_state->skip_intermediate_wm = true;
>
> ret = intel_atomic_check(dev, state);
> if (ret) {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a9e7683d5a0d..346c30a222cd 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1420,7 +1420,8 @@ static int g4x_compute_intermediate_wm(struct drm_device *dev,
> const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
> enum plane_id plane_id;
>
> - if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
> + if (!new_crtc_state->base.active || intel_state->skip_intermediate_wm ||
> + drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
> *intermediate = *optimal;
>
> intermediate->cxsr = false;
> @@ -2053,7 +2054,8 @@ static int vlv_compute_intermediate_wm(struct drm_device *dev,
> const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
> int level;
>
> - if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
> + if (!new_crtc_state->base.active || intel_state->skip_intermediate_wm ||
> + drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
> *intermediate = *optimal;
>
> intermediate->cxsr = false;
> @@ -3162,7 +3164,8 @@ static int ilk_compute_intermediate_wm(struct drm_device *dev,
> * and after the vblank.
> */
> *a = newstate->wm.ilk.optimal;
> - if (!newstate->base.active || drm_atomic_crtc_needs_modeset(&newstate->base))
> + if (!newstate->base.active || intel_state->skip_intermediate_wm ||
> + drm_atomic_crtc_needs_modeset(&newstate->base))
> return 0;
>
> a->pipe_enabled |= b->pipe_enabled;
> --
> 2.14.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-10-27 12:01 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-10-27 7:59 [PATCH 1/3] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3 Maarten Lankhorst
2017-10-27 7:59 ` [PATCH 2/3] drm/i915: Calculate g4x intermediate watermarks correctly Maarten Lankhorst
2017-10-27 7:59 ` [PATCH 3/3] drm/i915: Clean up skip_intermediate_wm handling Maarten Lankhorst
2017-10-27 12:01 ` Ville Syrjälä
2017-10-27 8:23 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3 Patchwork
2017-10-27 9:26 ` ✓ Fi.CI.IGT: " Patchwork
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