* [PATCH v2 2/9] drm/i915: Force the switch to the i915->kernel_context
2017-11-03 13:34 [PATCH v2 1/9] drm/i915: Define an engine class enum for the uABI Chris Wilson
@ 2017-11-03 13:34 ` Chris Wilson
2017-11-03 14:03 ` Mika Kuoppala
2017-11-03 13:34 ` [PATCH v2 3/9] drm/i915: Move GT powersaving init to i915_gem_init() Chris Wilson
` (10 subsequent siblings)
11 siblings, 1 reply; 18+ messages in thread
From: Chris Wilson @ 2017-11-03 13:34 UTC (permalink / raw)
To: intel-gfx
In the next few patches, we will have a hard requirement that we emit a
context-switch to the perma-pinned i915->kernel_context (so that we can
save the HW state using that context-switch). As the first context
itself may be classed as a kernel context, we want to be explicit in our
comparison. For an extra-layer of finesse, we can check the last
unretired context on the engine; as well as the last retired context
when idle.
v2: verbose verbosity
v3: Always force the switch, even when the engine is idle, and update
the assert that this happens before suspend.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> #v1
---
drivers/gpu/drm/i915/i915_gem.c | 10 ++++++----
drivers/gpu/drm/i915/intel_engine_cs.c | 26 ++++++++++++++++++++++++--
2 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9470ba0c1930..fe312ab3b664 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4687,14 +4687,16 @@ void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
i915_gem_object_put(obj);
}
-static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
+static void assert_kernel_context_is_current(struct drm_i915_private *i915)
{
+ struct i915_gem_context *kernel_context = i915->kernel_context;
struct intel_engine_cs *engine;
enum intel_engine_id id;
- for_each_engine(engine, dev_priv, id)
- GEM_BUG_ON(engine->last_retired_context &&
- !i915_gem_context_is_kernel(engine->last_retired_context));
+ for_each_engine(engine, i915, id) {
+ GEM_BUG_ON(__i915_gem_active_peek(&engine->timeline->last_request));
+ GEM_BUG_ON(engine->last_retired_context != kernel_context);
+ }
}
void i915_gem_sanitize(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 0987768c311d..374e398e867a 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1593,10 +1593,32 @@ bool intel_engines_are_idle(struct drm_i915_private *dev_priv)
return true;
}
+/**
+ * intel_engine_has_kernel_context:
+ * @engine: the engine
+ *
+ * Returns true if the last context to be executed on this engine, or has been
+ * executed if the engine is already idle, is the kernel context
+ * (#i915.kernel_context).
+ */
bool intel_engine_has_kernel_context(const struct intel_engine_cs *engine)
{
- return (!engine->last_retired_context ||
- i915_gem_context_is_kernel(engine->last_retired_context));
+ const struct i915_gem_context * const kernel_context =
+ engine->i915->kernel_context;
+ struct drm_i915_gem_request *rq;
+
+ lockdep_assert_held(&engine->i915->drm.struct_mutex);
+
+ /*
+ * Check the last context seen by the engine. If active, it will be
+ * the last request that remains in the timeline. When idle, it is
+ * the last executed context as tracked by retirement.
+ */
+ rq = __i915_gem_active_peek(&engine->timeline->last_request);
+ if (rq)
+ return rq->ctx == kernel_context;
+ else
+ return engine->last_retired_context == kernel_context;
}
void intel_engines_reset_default_submission(struct drm_i915_private *i915)
--
2.15.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 2/9] drm/i915: Force the switch to the i915->kernel_context
2017-11-03 13:34 ` [PATCH v2 2/9] drm/i915: Force the switch to the i915->kernel_context Chris Wilson
@ 2017-11-03 14:03 ` Mika Kuoppala
2017-11-03 14:07 ` Chris Wilson
0 siblings, 1 reply; 18+ messages in thread
From: Mika Kuoppala @ 2017-11-03 14:03 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> In the next few patches, we will have a hard requirement that we emit a
> context-switch to the perma-pinned i915->kernel_context (so that we can
> save the HW state using that context-switch). As the first context
> itself may be classed as a kernel context, we want to be explicit in our
> comparison. For an extra-layer of finesse, we can check the last
> unretired context on the engine; as well as the last retired context
> when idle.
>
> v2: verbose verbosity
> v3: Always force the switch, even when the engine is idle, and update
> the assert that this happens before suspend.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> #v1
> ---
> drivers/gpu/drm/i915/i915_gem.c | 10 ++++++----
> drivers/gpu/drm/i915/intel_engine_cs.c | 26 ++++++++++++++++++++++++--
> 2 files changed, 30 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 9470ba0c1930..fe312ab3b664 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4687,14 +4687,16 @@ void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
> i915_gem_object_put(obj);
> }
>
> -static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
> +static void assert_kernel_context_is_current(struct drm_i915_private *i915)
> {
> + struct i915_gem_context *kernel_context = i915->kernel_context;
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
>
> - for_each_engine(engine, dev_priv, id)
> - GEM_BUG_ON(engine->last_retired_context &&
> - !i915_gem_context_is_kernel(engine->last_retired_context));
> + for_each_engine(engine, i915, id) {
> + GEM_BUG_ON(__i915_gem_active_peek(&engine->timeline->last_request));
It could be that we have a active request for kernel context and we
still bail out with assert. Why?
-Mika
> + GEM_BUG_ON(engine->last_retired_context != kernel_context);
> + }
> }
>
> void i915_gem_sanitize(struct drm_i915_private *i915)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 0987768c311d..374e398e867a 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1593,10 +1593,32 @@ bool intel_engines_are_idle(struct drm_i915_private *dev_priv)
> return true;
> }
>
> +/**
> + * intel_engine_has_kernel_context:
> + * @engine: the engine
> + *
> + * Returns true if the last context to be executed on this engine, or has been
> + * executed if the engine is already idle, is the kernel context
> + * (#i915.kernel_context).
> + */
> bool intel_engine_has_kernel_context(const struct intel_engine_cs *engine)
> {
> - return (!engine->last_retired_context ||
> - i915_gem_context_is_kernel(engine->last_retired_context));
> + const struct i915_gem_context * const kernel_context =
> + engine->i915->kernel_context;
> + struct drm_i915_gem_request *rq;
> +
> + lockdep_assert_held(&engine->i915->drm.struct_mutex);
> +
> + /*
> + * Check the last context seen by the engine. If active, it will be
> + * the last request that remains in the timeline. When idle, it is
> + * the last executed context as tracked by retirement.
> + */
> + rq = __i915_gem_active_peek(&engine->timeline->last_request);
> + if (rq)
> + return rq->ctx == kernel_context;
> + else
> + return engine->last_retired_context == kernel_context;
> }
>
> void intel_engines_reset_default_submission(struct drm_i915_private *i915)
> --
> 2.15.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 2/9] drm/i915: Force the switch to the i915->kernel_context
2017-11-03 14:03 ` Mika Kuoppala
@ 2017-11-03 14:07 ` Chris Wilson
2017-11-03 14:13 ` Mika Kuoppala
0 siblings, 1 reply; 18+ messages in thread
From: Chris Wilson @ 2017-11-03 14:07 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2017-11-03 14:03:25)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > In the next few patches, we will have a hard requirement that we emit a
> > context-switch to the perma-pinned i915->kernel_context (so that we can
> > save the HW state using that context-switch). As the first context
> > itself may be classed as a kernel context, we want to be explicit in our
> > comparison. For an extra-layer of finesse, we can check the last
> > unretired context on the engine; as well as the last retired context
> > when idle.
> >
> > v2: verbose verbosity
> > v3: Always force the switch, even when the engine is idle, and update
> > the assert that this happens before suspend.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> #v1
> > ---
> > drivers/gpu/drm/i915/i915_gem.c | 10 ++++++----
> > drivers/gpu/drm/i915/intel_engine_cs.c | 26 ++++++++++++++++++++++++--
> > 2 files changed, 30 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index 9470ba0c1930..fe312ab3b664 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -4687,14 +4687,16 @@ void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
> > i915_gem_object_put(obj);
> > }
> >
> > -static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
> > +static void assert_kernel_context_is_current(struct drm_i915_private *i915)
> > {
> > + struct i915_gem_context *kernel_context = i915->kernel_context;
> > struct intel_engine_cs *engine;
> > enum intel_engine_id id;
> >
> > - for_each_engine(engine, dev_priv, id)
> > - GEM_BUG_ON(engine->last_retired_context &&
> > - !i915_gem_context_is_kernel(engine->last_retired_context));
> > + for_each_engine(engine, i915, id) {
> > + GEM_BUG_ON(__i915_gem_active_peek(&engine->timeline->last_request));
>
> It could be that we have a active request for kernel context and we
> still bail out with assert. Why?
Because we waited for the system to be idle, so we expect the timeline
to have been completely retired, which implies that
timline->last_request is now NULL.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 2/9] drm/i915: Force the switch to the i915->kernel_context
2017-11-03 14:07 ` Chris Wilson
@ 2017-11-03 14:13 ` Mika Kuoppala
0 siblings, 0 replies; 18+ messages in thread
From: Mika Kuoppala @ 2017-11-03 14:13 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2017-11-03 14:03:25)
>> Chris Wilson <chris@chris-wilson.co.uk> writes:
>>
>> > In the next few patches, we will have a hard requirement that we emit a
>> > context-switch to the perma-pinned i915->kernel_context (so that we can
>> > save the HW state using that context-switch). As the first context
>> > itself may be classed as a kernel context, we want to be explicit in our
>> > comparison. For an extra-layer of finesse, we can check the last
>> > unretired context on the engine; as well as the last retired context
>> > when idle.
>> >
>> > v2: verbose verbosity
>> > v3: Always force the switch, even when the engine is idle, and update
>> > the assert that this happens before suspend.
>> >
>> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> > Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> #v1
>> > ---
>> > drivers/gpu/drm/i915/i915_gem.c | 10 ++++++----
>> > drivers/gpu/drm/i915/intel_engine_cs.c | 26 ++++++++++++++++++++++++--
>> > 2 files changed, 30 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>> > index 9470ba0c1930..fe312ab3b664 100644
>> > --- a/drivers/gpu/drm/i915/i915_gem.c
>> > +++ b/drivers/gpu/drm/i915/i915_gem.c
>> > @@ -4687,14 +4687,16 @@ void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
>> > i915_gem_object_put(obj);
>> > }
>> >
>> > -static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
>> > +static void assert_kernel_context_is_current(struct drm_i915_private *i915)
>> > {
>> > + struct i915_gem_context *kernel_context = i915->kernel_context;
>> > struct intel_engine_cs *engine;
>> > enum intel_engine_id id;
>> >
>> > - for_each_engine(engine, dev_priv, id)
>> > - GEM_BUG_ON(engine->last_retired_context &&
>> > - !i915_gem_context_is_kernel(engine->last_retired_context));
>> > + for_each_engine(engine, i915, id) {
>> > + GEM_BUG_ON(__i915_gem_active_peek(&engine->timeline->last_request));
>>
>> It could be that we have a active request for kernel context and we
>> still bail out with assert. Why?
>
> Because we waited for the system to be idle, so we expect the timeline
> to have been completely retired, which implies that
> timline->last_request is now NULL.
Ok, the callsite did reveal this. And I did reveal being lazy for not
looking.
assert_idle_on_kernel_context()?
Regardless,
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> -Chris
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 3/9] drm/i915: Move GT powersaving init to i915_gem_init()
2017-11-03 13:34 [PATCH v2 1/9] drm/i915: Define an engine class enum for the uABI Chris Wilson
2017-11-03 13:34 ` [PATCH v2 2/9] drm/i915: Force the switch to the i915->kernel_context Chris Wilson
@ 2017-11-03 13:34 ` Chris Wilson
2017-11-03 13:34 ` [PATCH v2 4/9] drm/i915: Inline intel_modeset_gem_init() Chris Wilson
` (9 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2017-11-03 13:34 UTC (permalink / raw)
To: intel-gfx
GT powersaving is tightly coupled to the request infrastructure. To
avoid complications with the order of initialisation in the next patch
(where we want to send requests to hw during GEM init) move the
powersaving initialisation into the purview of i915_gem_init().
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 7 ++++++-
drivers/gpu/drm/i915/intel_display.c | 2 --
drivers/gpu/drm/i915/intel_pm.c | 2 --
3 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fe312ab3b664..20b3a6fc75c2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5019,6 +5019,12 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
goto out_unlock;
ret = i915_gem_init_hw(dev_priv);
+ if (ret)
+ goto out_unlock;
+
+ intel_init_gt_powersave(dev_priv);
+
+out_unlock:
if (ret == -EIO) {
/* Allow engine initialisation to fail by marking the GPU as
* wedged. But we only want to do this where the GPU is angry,
@@ -5031,7 +5037,6 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
ret = 0;
}
-out_unlock:
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
mutex_unlock(&dev_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 737de251d0f8..c3bf87c2036c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15174,8 +15174,6 @@ void intel_modeset_gem_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- intel_init_gt_powersave(dev_priv);
-
intel_setup_overlay(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 07118c0b69d3..6e1358d4e764 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7900,7 +7900,6 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
intel_runtime_pm_get(dev_priv);
}
- mutex_lock(&dev_priv->drm.struct_mutex);
mutex_lock(&dev_priv->pcu_lock);
/* Initialize RPS limits (for userspace) */
@@ -7942,7 +7941,6 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
rps->boost_freq = rps->max_freq;
mutex_unlock(&dev_priv->pcu_lock);
- mutex_unlock(&dev_priv->drm.struct_mutex);
intel_autoenable_gt_powersave(dev_priv);
}
--
2.15.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 4/9] drm/i915: Inline intel_modeset_gem_init()
2017-11-03 13:34 [PATCH v2 1/9] drm/i915: Define an engine class enum for the uABI Chris Wilson
2017-11-03 13:34 ` [PATCH v2 2/9] drm/i915: Force the switch to the i915->kernel_context Chris Wilson
2017-11-03 13:34 ` [PATCH v2 3/9] drm/i915: Move GT powersaving init to i915_gem_init() Chris Wilson
@ 2017-11-03 13:34 ` Chris Wilson
2017-11-03 14:06 ` Mika Kuoppala
2017-11-03 13:34 ` [PATCH v2 5/9] drm/i915: Mark the context state as dirty/written Chris Wilson
` (8 subsequent siblings)
11 siblings, 1 reply; 18+ messages in thread
From: Chris Wilson @ 2017-11-03 13:34 UTC (permalink / raw)
To: intel-gfx
intel_modeset_gem_init() now only sets up the legacy overlay, so let's
remove the function and call the setup directly during driver load. This
should help us find a better point in the initialisation sequence for it
later.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_display.c | 7 -------
3 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e7e9e061073b..1b440f2b90a5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -676,7 +676,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_uc;
- intel_modeset_gem_init(dev);
+ intel_setup_overlay(dev_priv);
if (INTEL_INFO(dev_priv)->num_pipes == 0)
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72bb5b51035a..593714fe5c5e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4118,7 +4118,6 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv);
/* modesetting */
extern void intel_modeset_init_hw(struct drm_device *dev);
extern int intel_modeset_init(struct drm_device *dev);
-extern void intel_modeset_gem_init(struct drm_device *dev);
extern void intel_modeset_cleanup(struct drm_device *dev);
extern int intel_connector_register(struct drm_connector *);
extern void intel_connector_unregister(struct drm_connector *);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c3bf87c2036c..5debb79540a2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15170,13 +15170,6 @@ void intel_display_resume(struct drm_device *dev)
drm_atomic_state_put(state);
}
-void intel_modeset_gem_init(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- intel_setup_overlay(dev_priv);
-}
-
int intel_connector_register(struct drm_connector *connector)
{
struct intel_connector *intel_connector = to_intel_connector(connector);
--
2.15.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 4/9] drm/i915: Inline intel_modeset_gem_init()
2017-11-03 13:34 ` [PATCH v2 4/9] drm/i915: Inline intel_modeset_gem_init() Chris Wilson
@ 2017-11-03 14:06 ` Mika Kuoppala
0 siblings, 0 replies; 18+ messages in thread
From: Mika Kuoppala @ 2017-11-03 14:06 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> intel_modeset_gem_init() now only sets up the legacy overlay, so let's
> remove the function and call the setup directly during driver load. This
> should help us find a better point in the initialisation sequence for it
> later.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 1 -
> drivers/gpu/drm/i915/intel_display.c | 7 -------
> 3 files changed, 1 insertion(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index e7e9e061073b..1b440f2b90a5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -676,7 +676,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> if (ret)
> goto cleanup_uc;
>
> - intel_modeset_gem_init(dev);
> + intel_setup_overlay(dev_priv);
>
> if (INTEL_INFO(dev_priv)->num_pipes == 0)
> return 0;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 72bb5b51035a..593714fe5c5e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -4118,7 +4118,6 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv);
> /* modesetting */
> extern void intel_modeset_init_hw(struct drm_device *dev);
> extern int intel_modeset_init(struct drm_device *dev);
> -extern void intel_modeset_gem_init(struct drm_device *dev);
> extern void intel_modeset_cleanup(struct drm_device *dev);
> extern int intel_connector_register(struct drm_connector *);
> extern void intel_connector_unregister(struct drm_connector *);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c3bf87c2036c..5debb79540a2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15170,13 +15170,6 @@ void intel_display_resume(struct drm_device *dev)
> drm_atomic_state_put(state);
> }
>
> -void intel_modeset_gem_init(struct drm_device *dev)
> -{
> - struct drm_i915_private *dev_priv = to_i915(dev);
> -
> - intel_setup_overlay(dev_priv);
> -}
> -
> int intel_connector_register(struct drm_connector *connector)
> {
> struct intel_connector *intel_connector = to_intel_connector(connector);
> --
> 2.15.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 5/9] drm/i915: Mark the context state as dirty/written
2017-11-03 13:34 [PATCH v2 1/9] drm/i915: Define an engine class enum for the uABI Chris Wilson
` (2 preceding siblings ...)
2017-11-03 13:34 ` [PATCH v2 4/9] drm/i915: Inline intel_modeset_gem_init() Chris Wilson
@ 2017-11-03 13:34 ` Chris Wilson
2017-11-03 14:29 ` Mika Kuoppala
2017-11-03 13:34 ` [PATCH v2 6/9] drm/i915: Record the default hw state after reset upon load Chris Wilson
` (7 subsequent siblings)
11 siblings, 1 reply; 18+ messages in thread
From: Chris Wilson @ 2017-11-03 13:34 UTC (permalink / raw)
To: intel-gfx
In the next few patches, we will want to both copy out of the context
image and write a valid image into a new context. To be completely safe,
we should then couple in our domain tracking to ensure that we don't
have any issues with stale data remaining in unwanted cachelines.
Historically, we omitted the .write=true from the call to set-gtt-domain
in i915_switch_context() in order to avoid a stall between every request
as we would want to wait for the previous context write from the gpu.
Since then, we limit the set-gtt-domain to only occur when we first bind
the vma, so once in use we will never stall, and we are sure to flush
the context following a load from swap.
Equally we never applied the lessons learnt from ringbuffer submission
to execlists; so time to apply the flush of the lrc after load as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 32 ++++++++++++++++++++++++--------
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++---
2 files changed, 27 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6840ec8db037..9b4e74151ace 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1060,12 +1060,34 @@ static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
spin_unlock_irq(&engine->timeline->lock);
}
+static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
+{
+ unsigned int flags;
+ int err;
+
+ /*
+ * Clear this page out of any CPU caches for coherent swap-in/out.
+ * We only want to do this on the first bind so that we do not stall
+ * on an active context (which by nature is already on the GPU).
+ */
+ if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
+ err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
+ if (err)
+ return err;
+ }
+
+ flags = PIN_GLOBAL | PIN_HIGH;
+ if (ctx->ggtt_offset_bias)
+ flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
+
+ return i915_vma_pin(vma, 0, GEN8_LR_CONTEXT_ALIGN, flags);
+}
+
static struct intel_ring *
execlists_context_pin(struct intel_engine_cs *engine,
struct i915_gem_context *ctx)
{
struct intel_context *ce = &ctx->engine[engine->id];
- unsigned int flags;
void *vaddr;
int ret;
@@ -1082,11 +1104,7 @@ execlists_context_pin(struct intel_engine_cs *engine,
}
GEM_BUG_ON(!ce->state);
- flags = PIN_GLOBAL | PIN_HIGH;
- if (ctx->ggtt_offset_bias)
- flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
-
- ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags);
+ ret = __context_pin(ctx, ce->state);
if (ret)
goto err;
@@ -1106,9 +1124,7 @@ execlists_context_pin(struct intel_engine_cs *engine,
ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
i915_ggtt_offset(ce->ring->vma);
- ce->state->obj->mm.dirty = true;
ce->state->obj->pin_global++;
-
i915_gem_context_get(ctx);
out:
return ce->ring;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 47fadf8da84e..7e2a671882fb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1363,12 +1363,13 @@ static int context_pin(struct i915_gem_context *ctx)
struct i915_vma *vma = ctx->engine[RCS].state;
int ret;
- /* Clear this page out of any CPU caches for coherent swap-in/out.
+ /*
+ * Clear this page out of any CPU caches for coherent swap-in/out.
* We only want to do this on the first bind so that we do not stall
* on an active context (which by nature is already on the GPU).
*/
if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
- ret = i915_gem_object_set_to_gtt_domain(vma->obj, false);
+ ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
if (ret)
return ret;
}
@@ -1445,7 +1446,6 @@ intel_ring_context_pin(struct intel_engine_cs *engine,
if (ret)
goto err;
- ce->state->obj->mm.dirty = true;
ce->state->obj->pin_global++;
}
--
2.15.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 5/9] drm/i915: Mark the context state as dirty/written
2017-11-03 13:34 ` [PATCH v2 5/9] drm/i915: Mark the context state as dirty/written Chris Wilson
@ 2017-11-03 14:29 ` Mika Kuoppala
0 siblings, 0 replies; 18+ messages in thread
From: Mika Kuoppala @ 2017-11-03 14:29 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> In the next few patches, we will want to both copy out of the context
> image and write a valid image into a new context. To be completely safe,
> we should then couple in our domain tracking to ensure that we don't
> have any issues with stale data remaining in unwanted cachelines.
>
> Historically, we omitted the .write=true from the call to set-gtt-domain
> in i915_switch_context() in order to avoid a stall between every request
> as we would want to wait for the previous context write from the gpu.
> Since then, we limit the set-gtt-domain to only occur when we first bind
> the vma, so once in use we will never stall, and we are sure to flush
> the context following a load from swap.
>
> Equally we never applied the lessons learnt from ringbuffer submission
> to execlists; so time to apply the flush of the lrc after load as well.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 32 ++++++++++++++++++++++++--------
> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++---
> 2 files changed, 27 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 6840ec8db037..9b4e74151ace 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1060,12 +1060,34 @@ static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
> spin_unlock_irq(&engine->timeline->lock);
> }
>
> +static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
> +{
> + unsigned int flags;
> + int err;
> +
> + /*
> + * Clear this page out of any CPU caches for coherent swap-in/out.
> + * We only want to do this on the first bind so that we do not stall
> + * on an active context (which by nature is already on the GPU).
> + */
> + if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
> + err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
> + if (err)
> + return err;
> + }
> +
> + flags = PIN_GLOBAL | PIN_HIGH;
> + if (ctx->ggtt_offset_bias)
> + flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
> +
> + return i915_vma_pin(vma, 0, GEN8_LR_CONTEXT_ALIGN, flags);
> +}
> +
> static struct intel_ring *
> execlists_context_pin(struct intel_engine_cs *engine,
> struct i915_gem_context *ctx)
> {
> struct intel_context *ce = &ctx->engine[engine->id];
> - unsigned int flags;
> void *vaddr;
> int ret;
>
> @@ -1082,11 +1104,7 @@ execlists_context_pin(struct intel_engine_cs *engine,
> }
> GEM_BUG_ON(!ce->state);
>
> - flags = PIN_GLOBAL | PIN_HIGH;
> - if (ctx->ggtt_offset_bias)
> - flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
> -
> - ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags);
> + ret = __context_pin(ctx, ce->state);
> if (ret)
> goto err;
>
> @@ -1106,9 +1124,7 @@ execlists_context_pin(struct intel_engine_cs *engine,
> ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
> i915_ggtt_offset(ce->ring->vma);
>
> - ce->state->obj->mm.dirty = true;
> ce->state->obj->pin_global++;
> -
> i915_gem_context_get(ctx);
> out:
> return ce->ring;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 47fadf8da84e..7e2a671882fb 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1363,12 +1363,13 @@ static int context_pin(struct i915_gem_context *ctx)
> struct i915_vma *vma = ctx->engine[RCS].state;
> int ret;
>
> - /* Clear this page out of any CPU caches for coherent swap-in/out.
> + /*
> + * Clear this page out of any CPU caches for coherent swap-in/out.
> * We only want to do this on the first bind so that we do not stall
> * on an active context (which by nature is already on the GPU).
> */
> if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
> - ret = i915_gem_object_set_to_gtt_domain(vma->obj, false);
> + ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
> if (ret)
> return ret;
> }
> @@ -1445,7 +1446,6 @@ intel_ring_context_pin(struct intel_engine_cs *engine,
> if (ret)
> goto err;
>
> - ce->state->obj->mm.dirty = true;
> ce->state->obj->pin_global++;
> }
>
> --
> 2.15.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 6/9] drm/i915: Record the default hw state after reset upon load
2017-11-03 13:34 [PATCH v2 1/9] drm/i915: Define an engine class enum for the uABI Chris Wilson
` (3 preceding siblings ...)
2017-11-03 13:34 ` [PATCH v2 5/9] drm/i915: Mark the context state as dirty/written Chris Wilson
@ 2017-11-03 13:34 ` Chris Wilson
2017-11-03 13:34 ` [PATCH v2 7/9] drm/i915: Report whether we have true context isolation Chris Wilson
` (6 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2017-11-03 13:34 UTC (permalink / raw)
To: intel-gfx
Take a copy of the HW state after a reset upon module loading by
executing a context switch from a blank context to the kernel context,
thus saving the default hw state over the blank context image.
We can then use the default hw state to initialise any future context,
ensuring that each starts with the default view of hw state.
v2: Unmap our default state from the GTT after stealing it from the
context. This should stop us from accidentally overwriting it via the
GTT (and frees up some precious GTT space).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/gvt/scheduler.c | 2 -
drivers/gpu/drm/i915/i915_debugfs.c | 1 -
drivers/gpu/drm/i915/i915_gem.c | 100 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_gem_context.c | 55 ++++--------------
drivers/gpu/drm/i915/i915_gem_context.h | 4 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 3 +
drivers/gpu/drm/i915/intel_lrc.c | 39 ++++++++-----
drivers/gpu/drm/i915/intel_ringbuffer.c | 45 ++++++++++----
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
9 files changed, 177 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index f6ded475bb2c..42cc61230ca7 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -723,8 +723,6 @@ int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu)
if (IS_ERR(vgpu->shadow_ctx))
return PTR_ERR(vgpu->shadow_ctx);
- vgpu->shadow_ctx->engine[RCS].initialised = true;
-
bitmap_zero(vgpu->shadow_ctx_desc_updated, I915_NUM_ENGINES);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 39883cd915db..cfcef1899da8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1974,7 +1974,6 @@ static int i915_context_status(struct seq_file *m, void *unused)
struct intel_context *ce = &ctx->engine[engine->id];
seq_printf(m, "%s: ", engine->name);
- seq_putc(m, ce->initialised ? 'I' : 'i');
if (ce->state)
describe_obj(m, ce->state->obj);
if (ce->ring)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 20b3a6fc75c2..0fa1dea7ebc0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4969,6 +4969,102 @@ bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
return true;
}
+static int __intel_engines_record_defaults(struct drm_i915_private *i915)
+{
+ struct i915_gem_context *ctx;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err;
+
+ /*
+ * As we reset the gpu during very early sanitisation, the current
+ * register state on the GPU should reflect its defaults values.
+ * We load a context onto the hw (with restore-inhibit), then switch
+ * over to a second context to save that default register state. We
+ * can then prime every new context with that state so they all start
+ * from the same default HW values.
+ */
+
+ ctx = i915_gem_context_create_kernel(i915, 0);
+ if (IS_ERR(ctx))
+ return PTR_ERR(ctx);
+
+ for_each_engine(engine, i915, id) {
+ struct drm_i915_gem_request *rq;
+
+ rq = i915_gem_request_alloc(engine, ctx);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_ctx;
+ }
+
+ err = i915_switch_context(rq);
+ if (engine->init_context)
+ err = engine->init_context(rq);
+
+ __i915_add_request(rq, true);
+ if (err)
+ goto err_active;
+ }
+
+ err = i915_gem_switch_to_kernel_context(i915);
+ if (err)
+ goto err_active;
+
+ err = i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED);
+ if (err)
+ goto err_active;
+
+ assert_kernel_context_is_current(i915);
+
+ for_each_engine(engine, i915, id) {
+ struct i915_vma *state;
+
+ state = ctx->engine[id].state;
+ if (!state)
+ continue;
+
+ /*
+ * As we will hold a reference to the logical state, it will
+ * not be torn down with the context, and importantly the
+ * object will hold onto its vma (making it possible for a
+ * stray GTT write to corrupt our defaults). Unmap the vma
+ * from the GTT to prevent such accidents and reclaim the
+ * space.
+ */
+ err = i915_vma_unbind(state);
+ if (err)
+ goto err_active;
+
+ err = i915_gem_object_set_to_cpu_domain(state->obj, false);
+ if (err)
+ goto err_active;
+
+ engine->default_state = i915_gem_object_get(state->obj);
+ }
+
+out_ctx:
+ i915_gem_context_set_closed(ctx);
+ i915_gem_context_put(ctx);
+ return err;
+
+err_active:
+ /*
+ * If we have to abandon now, we expect the engines to be idle
+ * and ready to be torn-down. First try to flush any remaining
+ * request, ensure we are pointing at the kernel context and
+ * then remove it.
+ */
+ if (WARN_ON(i915_gem_switch_to_kernel_context(i915)))
+ goto out_ctx;
+
+ if (WARN_ON(i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED)))
+ goto out_ctx;
+
+ i915_gem_contexts_lost(i915);
+ goto out_ctx;
+}
+
int i915_gem_init(struct drm_i915_private *dev_priv)
{
int ret;
@@ -5024,6 +5120,10 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_init_gt_powersave(dev_priv);
+ ret = __intel_engines_record_defaults(dev_priv);
+ if (ret)
+ goto out_unlock;
+
out_unlock:
if (ret == -EIO) {
/* Allow engine initialisation to fail by marking the GPU as
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 10affb35ac56..31ee5ec4a0a8 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -418,8 +418,8 @@ i915_gem_context_create_gvt(struct drm_device *dev)
return ctx;
}
-static struct i915_gem_context *
-create_kernel_context(struct drm_i915_private *i915, int prio)
+struct i915_gem_context *
+i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio)
{
struct i915_gem_context *ctx;
@@ -473,7 +473,7 @@ int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
ida_init(&dev_priv->contexts.hw_ida);
/* lowest priority; idle task */
- ctx = create_kernel_context(dev_priv, I915_PRIORITY_MIN);
+ ctx = i915_gem_context_create_kernel(dev_priv, I915_PRIORITY_MIN);
if (IS_ERR(ctx)) {
DRM_ERROR("Failed to create default global context\n");
err = PTR_ERR(ctx);
@@ -487,7 +487,7 @@ int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
dev_priv->kernel_context = ctx;
/* highest priority; preempting task */
- ctx = create_kernel_context(dev_priv, INT_MAX);
+ ctx = i915_gem_context_create_kernel(dev_priv, INT_MAX);
if (IS_ERR(ctx)) {
DRM_ERROR("Failed to create default preempt context\n");
err = PTR_ERR(ctx);
@@ -522,28 +522,6 @@ void i915_gem_contexts_lost(struct drm_i915_private *dev_priv)
engine->context_unpin(engine, engine->last_retired_context);
engine->last_retired_context = NULL;
}
-
- /* Force the GPU state to be restored on enabling */
- if (!i915_modparams.enable_execlists) {
- struct i915_gem_context *ctx;
-
- list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
- if (!i915_gem_context_is_default(ctx))
- continue;
-
- for_each_engine(engine, dev_priv, id)
- ctx->engine[engine->id].initialised = false;
-
- ctx->remap_slice = ALL_L3_SLICES(dev_priv);
- }
-
- for_each_engine(engine, dev_priv, id) {
- struct intel_context *kce =
- &dev_priv->kernel_context->engine[engine->id];
-
- kce->initialised = true;
- }
- }
}
void i915_gem_contexts_fini(struct drm_i915_private *i915)
@@ -718,9 +696,6 @@ static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
if (to->remap_slice)
return false;
- if (!to->engine[RCS].initialised)
- return false;
-
if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
return false;
@@ -795,11 +770,14 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
return ret;
}
- if (!to->engine[RCS].initialised || i915_gem_context_is_default(to))
- /* NB: If we inhibit the restore, the context is not allowed to
- * die because future work may end up depending on valid address
- * space. This means we must enforce that a page table load
- * occur when this occurs. */
+ if (i915_gem_context_is_kernel(to))
+ /*
+ * The kernel context(s) is treated as pure scratch and is not
+ * expected to retain any state (as we sacrifice it during
+ * suspend and on resume it may be corrupted). This is ok,
+ * as nothing actually executes using the kernel context; it
+ * is purely used for flushing user contexts.
+ */
hw_flags = MI_RESTORE_INHIBIT;
else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)
hw_flags = MI_FORCE_RESTORE;
@@ -843,15 +821,6 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
to->remap_slice &= ~(1<<i);
}
- if (!to->engine[RCS].initialised) {
- if (engine->init_context) {
- ret = engine->init_context(req);
- if (ret)
- return ret;
- }
- to->engine[RCS].initialised = true;
- }
-
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h
index 44688e22a5c2..4bfb72f8e1cb 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -157,7 +157,6 @@ struct i915_gem_context {
u32 *lrc_reg_state;
u64 lrc_desc;
int pin_count;
- bool initialised;
} engine[I915_NUM_ENGINES];
/** ring_size: size for allocating the per-engine ring buffer */
@@ -292,6 +291,9 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
+struct i915_gem_context *
+i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio);
+
static inline struct i915_gem_context *
i915_gem_context_get(struct i915_gem_context *ctx)
{
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 374e398e867a..93bacaee525b 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -687,6 +687,9 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
intel_engine_cleanup_cmd_parser(engine);
i915_gem_batch_pool_fini(&engine->batch_pool);
+ if (engine->default_state)
+ i915_gem_object_put(engine->default_state);
+
if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
engine->context_unpin(engine, engine->i915->preempt_context);
engine->context_unpin(engine, engine->i915->kernel_context);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9b4e74151ace..f96225a6a369 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1163,7 +1163,6 @@ static int execlists_request_alloc(struct drm_i915_gem_request *request)
struct intel_engine_cs *engine = request->engine;
struct intel_context *ce = &request->ctx->engine[engine->id];
u32 *cs;
- int ret;
GEM_BUG_ON(!ce->pin_count);
@@ -1177,14 +1176,6 @@ static int execlists_request_alloc(struct drm_i915_gem_request *request)
if (IS_ERR(cs))
return PTR_ERR(cs);
- if (!ce->initialised) {
- ret = engine->init_context(request);
- if (ret)
- return ret;
-
- ce->initialised = true;
- }
-
/* Note that after this point, we have committed to using
* this request as it is being used to both track the
* state of engine initialisation and liveness of the
@@ -2116,7 +2107,6 @@ static void execlists_init_reg_state(u32 *regs,
CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
- CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
(HAS_RESOURCE_STREAMER(dev_priv) ?
CTX_CTRL_RS_CTX_ENABLE : 0)));
CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
@@ -2193,6 +2183,7 @@ populate_lr_context(struct i915_gem_context *ctx,
struct intel_ring *ring)
{
void *vaddr;
+ u32 *regs;
int ret;
ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
@@ -2209,11 +2200,32 @@ populate_lr_context(struct i915_gem_context *ctx,
}
ctx_obj->mm.dirty = true;
+ if (engine->default_state) {
+ /*
+ * We only want to copy over the template context state;
+ * skipping over the headers reserved for GuC comunication,
+ * leaving those as zero.
+ */
+ const unsigned long offset = LRC_HEADER_PAGES * PAGE_SIZE;
+ void *defaults;
+
+ defaults = i915_gem_object_pin_map(engine->default_state,
+ I915_MAP_WB);
+ if (IS_ERR(defaults))
+ return PTR_ERR(defaults);
+
+ memcpy(vaddr + offset, defaults + offset, engine->context_size);
+ i915_gem_object_unpin_map(engine->default_state);
+ }
+
/* The second page of the context object contains some fields which must
* be set up prior to the first execution. */
-
- execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE,
- ctx, engine, ring);
+ regs = vaddr + LRC_STATE_PN * PAGE_SIZE;
+ execlists_init_reg_state(regs, ctx, engine, ring);
+ if (!engine->default_state) {
+ regs[CTX_CONTEXT_CONTROL+1] |=
+ _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
+ }
i915_gem_object_unpin_map(ctx_obj);
@@ -2266,7 +2278,6 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
ce->ring = ring;
ce->state = vma;
- ce->initialised |= engine->init_context == NULL;
return 0;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7e2a671882fb..464dc58af27b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1384,11 +1384,34 @@ alloc_context_vma(struct intel_engine_cs *engine)
struct drm_i915_private *i915 = engine->i915;
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
+ int err;
obj = i915_gem_object_create(i915, engine->context_size);
if (IS_ERR(obj))
return ERR_CAST(obj);
+ if (engine->default_state) {
+ void *defaults, *vaddr;
+
+ vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ goto err_obj;
+ }
+
+ defaults = i915_gem_object_pin_map(engine->default_state,
+ I915_MAP_WB);
+ if (IS_ERR(defaults)) {
+ err = PTR_ERR(defaults);
+ goto err_map;
+ }
+
+ memcpy(vaddr, defaults, engine->context_size);
+
+ i915_gem_object_unpin_map(engine->default_state);
+ i915_gem_object_unpin_map(obj);
+ }
+
/*
* Try to make the context utilize L3 as well as LLC.
*
@@ -1410,10 +1433,18 @@ alloc_context_vma(struct intel_engine_cs *engine)
}
vma = i915_vma_instance(obj, &i915->ggtt.base, NULL);
- if (IS_ERR(vma))
- i915_gem_object_put(obj);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_obj;
+ }
return vma;
+
+err_map:
+ i915_gem_object_unpin_map(obj);
+err_obj:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
}
static struct intel_ring *
@@ -1449,16 +1480,6 @@ intel_ring_context_pin(struct intel_engine_cs *engine,
ce->state->obj->pin_global++;
}
- /* The kernel context is only used as a placeholder for flushing the
- * active context. It is never used for submitting user rendering and
- * as such never requires the golden render context, and so we can skip
- * emitting it when we switch to the kernel context. This is required
- * as during eviction we cannot allocate and pin the renderstate in
- * order to initialise the context.
- */
- if (i915_gem_context_is_kernel(ctx))
- ce->initialised = true;
-
i915_gem_context_get(ctx);
out:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f3dbfe7ae6e4..0412d0434015 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -306,6 +306,7 @@ struct intel_engine_cs {
struct intel_ring *buffer;
struct intel_timeline *timeline;
+ struct drm_i915_gem_object *default_state;
struct intel_render_state *render_state;
atomic_t irq_count;
--
2.15.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 7/9] drm/i915: Report whether we have true context isolation
2017-11-03 13:34 [PATCH v2 1/9] drm/i915: Define an engine class enum for the uABI Chris Wilson
` (4 preceding siblings ...)
2017-11-03 13:34 ` [PATCH v2 6/9] drm/i915: Record the default hw state after reset upon load Chris Wilson
@ 2017-11-03 13:34 ` Chris Wilson
2017-11-03 13:34 ` [PATCH v2 8/9] drm/i915: Remove redundant intel_autoenable_gt_powersave() Chris Wilson
` (5 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2017-11-03 13:34 UTC (permalink / raw)
To: intel-gfx
Let userspace know if they can trust that new contexts are created using
HW default values; and avoid inheriting state from existing contexts.
Note: I intend to squash this into the bugfix once we agree on the uabi.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 11 +++++++++++
include/uapi/drm/i915_drm.h | 14 ++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1b440f2b90a5..fa4839bcdd63 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -406,6 +406,17 @@ static int i915_getparam(struct drm_device *dev, void *data,
*/
value = 1;
break;
+ case I915_PARAM_HAS_CONTEXT_ISOLATION:
+ {
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ value = 0;
+ for_each_engine(engine, dev_priv, id)
+ if (engine->default_state)
+ value |= BIT(engine->uabi_class);
+ }
+ break;
case I915_PARAM_SLICE_MASK:
value = INTEL_INFO(dev_priv)->sseu.slice_mask;
if (!value)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index efbed4860794..f1159cb787d5 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -459,6 +459,20 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
+/*
+ * Query whether every context (both per-file default and user created) is
+ * isolated (insofar as HW supports). If this parameter is not true, then
+ * freshly created contexts may inherit values from an existing context,
+ * rather than default HW values. If true, it also ensures (insofar as HW
+ * supports) that all state set by this context will not leak to any other
+ * context.
+ *
+ * As not every engine support contexts, the returned value reports the
+ * support of context isolation for individual engines by returning
+ * a bitmask of each HW ID set to true if that engine supports isolation.
+ */
+#define I915_PARAM_HAS_CONTEXT_ISOLATION 50
+
typedef struct drm_i915_getparam {
__s32 param;
/*
--
2.15.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 8/9] drm/i915: Remove redundant intel_autoenable_gt_powersave()
2017-11-03 13:34 [PATCH v2 1/9] drm/i915: Define an engine class enum for the uABI Chris Wilson
` (5 preceding siblings ...)
2017-11-03 13:34 ` [PATCH v2 7/9] drm/i915: Report whether we have true context isolation Chris Wilson
@ 2017-11-03 13:34 ` Chris Wilson
2017-11-03 13:34 ` [PATCH v2 9/9] drm/i915: Stop caching the "golden" renderstate Chris Wilson
` (4 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2017-11-03 13:34 UTC (permalink / raw)
To: intel-gfx
Now that we always execute a context switch upon module load, there is
no need to queue a delayed task for doing so. The purpose of the delayed
task is to enable GT powersaving, for which we need the HW state to be
valid (i.e. having loaded a context and initialised basic state). We
used to defer this operation as historically it was slow (due to slow
register polling, fixed with commit 1758b90e38f5 ("drm/i915: Use a hybrid
scheme for fast register waits")) but now we have a requirement to save
the default HW state.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 --
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_drv.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 66 ----------------------------------------
4 files changed, 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fa4839bcdd63..ba54bf1e806f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1754,8 +1754,6 @@ static int i915_drm_resume(struct drm_device *dev)
intel_opregion_notify_adapter(dev_priv, PCI_D0);
- intel_autoenable_gt_powersave(dev_priv);
-
enable_rpm_wakeref_asserts(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 593714fe5c5e..466ee055030b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1388,7 +1388,6 @@ struct intel_gen6_power_mgmt {
struct intel_rps rps;
struct intel_rc6 rc6;
struct intel_llc_pstate llc_pstate;
- struct delayed_work autoenable_work;
};
/* defined intel_pm.c */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 00b488688042..76b12fb1a35f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1881,7 +1881,6 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
-void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
void gen6_rps_busy(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6e1358d4e764..308439dd89d4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7941,8 +7941,6 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
rps->boost_freq = rps->max_freq;
mutex_unlock(&dev_priv->pcu_lock);
-
- intel_autoenable_gt_powersave(dev_priv);
}
void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
@@ -7967,9 +7965,6 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) < 6)
return;
- if (cancel_delayed_work_sync(&dev_priv->gt_pm.autoenable_work))
- intel_runtime_pm_put(dev_priv);
-
/* gen6_rps_idle() will be called later to disable interrupts */
}
@@ -8128,65 +8123,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
mutex_unlock(&dev_priv->pcu_lock);
}
-static void __intel_autoenable_gt_powersave(struct work_struct *work)
-{
- struct drm_i915_private *dev_priv =
- container_of(work,
- typeof(*dev_priv),
- gt_pm.autoenable_work.work);
- struct intel_engine_cs *rcs;
- struct drm_i915_gem_request *req;
-
- rcs = dev_priv->engine[RCS];
- if (rcs->last_retired_context)
- goto out;
-
- if (!rcs->init_context)
- goto out;
-
- mutex_lock(&dev_priv->drm.struct_mutex);
-
- req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
- if (IS_ERR(req))
- goto unlock;
-
- if (!i915_modparams.enable_execlists && i915_switch_context(req) == 0)
- rcs->init_context(req);
-
- /* Mark the device busy, calling intel_enable_gt_powersave() */
- i915_add_request(req);
-
-unlock:
- mutex_unlock(&dev_priv->drm.struct_mutex);
-out:
- intel_runtime_pm_put(dev_priv);
-}
-
-void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
-{
- if (IS_IRONLAKE_M(dev_priv)) {
- ironlake_enable_drps(dev_priv);
- intel_init_emon(dev_priv);
- } else if (INTEL_INFO(dev_priv)->gen >= 6) {
- /*
- * PCU communication is slow and this doesn't need to be
- * done at any specific time, so do this out of our fast path
- * to make resume and init faster.
- *
- * We depend on the HW RC6 power context save/restore
- * mechanism when entering D3 through runtime PM suspend. So
- * disable RPM until RPS/RC6 is properly setup. We can only
- * get here via the driver load/system resume/runtime resume
- * paths, so the _noresume version is enough (and in case of
- * runtime resume it's necessary).
- */
- if (queue_delayed_work(dev_priv->wq,
- &dev_priv->gt_pm.autoenable_work,
- round_jiffies_up_relative(HZ)))
- intel_runtime_pm_get_noresume(dev_priv);
- }
-}
-
static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
{
/*
@@ -9443,8 +9379,6 @@ void intel_pm_setup(struct drm_i915_private *dev_priv)
{
mutex_init(&dev_priv->pcu_lock);
- INIT_DELAYED_WORK(&dev_priv->gt_pm.autoenable_work,
- __intel_autoenable_gt_powersave);
atomic_set(&dev_priv->gt_pm.rps.num_waiters, 0);
dev_priv->runtime_pm.suspended = false;
--
2.15.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 9/9] drm/i915: Stop caching the "golden" renderstate
2017-11-03 13:34 [PATCH v2 1/9] drm/i915: Define an engine class enum for the uABI Chris Wilson
` (6 preceding siblings ...)
2017-11-03 13:34 ` [PATCH v2 8/9] drm/i915: Remove redundant intel_autoenable_gt_powersave() Chris Wilson
@ 2017-11-03 13:34 ` Chris Wilson
2017-11-03 14:01 ` ✗ Fi.CI.BAT: warning for series starting with [v2,1/9] drm/i915: Define an engine class enum for the uABI Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2017-11-03 13:34 UTC (permalink / raw)
To: intel-gfx
As we now record the default HW state and so only emit the "golden"
renderstate once to prepare the HW, there is no advantage in keeping the
renderstate batch around as it will never be used again.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gem_render_state.c | 135 +++++++++------------------
drivers/gpu/drm/i915/i915_gem_render_state.h | 4 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 9 +-
drivers/gpu/drm/i915/intel_lrc.c | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 -
7 files changed, 51 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 466ee055030b..71747131c444 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -67,7 +67,6 @@
#include "i915_gem_fence_reg.h"
#include "i915_gem_object.h"
#include "i915_gem_gtt.h"
-#include "i915_gem_render_state.h"
#include "i915_gem_request.h"
#include "i915_gem_timeline.h"
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 3703dc91eeda..69621d887975 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -26,10 +26,12 @@
*/
#include "i915_drv.h"
+#include "i915_gem_render_state.h"
#include "intel_renderstate.h"
struct intel_render_state {
const struct intel_renderstate_rodata *rodata;
+ struct drm_i915_gem_object *obj;
struct i915_vma *vma;
u32 batch_offset;
u32 batch_size;
@@ -74,17 +76,16 @@ static int render_state_setup(struct intel_render_state *so,
struct drm_i915_private *i915)
{
const struct intel_renderstate_rodata *rodata = so->rodata;
- struct drm_i915_gem_object *obj = so->vma->obj;
unsigned int i = 0, reloc_index = 0;
unsigned int needs_clflush;
u32 *d;
int ret;
- ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
+ ret = i915_gem_obj_prepare_shmem_write(so->obj, &needs_clflush);
if (ret)
return ret;
- d = kmap_atomic(i915_gem_object_get_dirty_page(obj, 0));
+ d = kmap_atomic(i915_gem_object_get_dirty_page(so->obj, 0));
while (i < rodata->batch_items) {
u32 s = rodata->batch[i];
@@ -112,7 +113,7 @@ static int render_state_setup(struct intel_render_state *so,
goto err;
}
- so->batch_offset = so->vma->node.start;
+ so->batch_offset = i915_ggtt_offset(so->vma);
so->batch_size = rodata->batch_items * sizeof(u32);
while (i % CACHELINE_DWORDS)
@@ -160,9 +161,9 @@ static int render_state_setup(struct intel_render_state *so,
drm_clflush_virt_range(d, i * sizeof(u32));
kunmap_atomic(d);
- ret = i915_gem_object_set_to_gtt_domain(obj, false);
+ ret = i915_gem_object_set_to_gtt_domain(so->obj, false);
out:
- i915_gem_obj_finish_shmem_access(obj);
+ i915_gem_obj_finish_shmem_access(so->obj);
return ret;
err:
@@ -173,112 +174,64 @@ static int render_state_setup(struct intel_render_state *so,
#undef OUT_BATCH
-int i915_gem_render_state_init(struct intel_engine_cs *engine)
+int i915_gem_render_state_emit(struct drm_i915_gem_request *rq)
{
- struct intel_render_state *so;
- const struct intel_renderstate_rodata *rodata;
- struct drm_i915_gem_object *obj;
- int ret;
+ struct intel_engine_cs *engine = rq->engine;
+ struct intel_render_state so;
+ int err;
if (engine->id != RCS)
return 0;
- rodata = render_state_get_rodata(engine);
- if (!rodata)
+ so.rodata = render_state_get_rodata(engine);
+ if (!so.rodata)
return 0;
- if (rodata->batch_items * 4 > PAGE_SIZE)
+ if (so.rodata->batch_items * 4 > PAGE_SIZE)
return -EINVAL;
- so = kmalloc(sizeof(*so), GFP_KERNEL);
- if (!so)
- return -ENOMEM;
+ so.obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
+ if (IS_ERR(so.obj))
+ return PTR_ERR(so.obj);
- obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
- if (IS_ERR(obj)) {
- ret = PTR_ERR(obj);
- goto err_free;
- }
-
- so->vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
- if (IS_ERR(so->vma)) {
- ret = PTR_ERR(so->vma);
+ so.vma = i915_vma_instance(so.obj, &engine->i915->ggtt.base, NULL);
+ if (IS_ERR(so.vma)) {
+ err = PTR_ERR(so.vma);
goto err_obj;
}
- so->rodata = rodata;
- engine->render_state = so;
- return 0;
-
-err_obj:
- i915_gem_object_put(obj);
-err_free:
- kfree(so);
- return ret;
-}
-
-int i915_gem_render_state_emit(struct drm_i915_gem_request *req)
-{
- struct intel_render_state *so;
- int ret;
-
- lockdep_assert_held(&req->i915->drm.struct_mutex);
+ err = i915_vma_pin(so.vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
+ if (err)
+ goto err_vma;
- so = req->engine->render_state;
- if (!so)
- return 0;
-
- /* Recreate the page after shrinking */
- if (!i915_gem_object_has_pages(so->vma->obj))
- so->batch_offset = -1;
-
- ret = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
- if (ret)
- return ret;
-
- if (so->vma->node.start != so->batch_offset) {
- ret = render_state_setup(so, req->i915);
- if (ret)
- goto err_unpin;
- }
+ err = render_state_setup(&so, rq->i915);
+ if (err)
+ goto err_unpin;
- ret = req->engine->emit_flush(req, EMIT_INVALIDATE);
- if (ret)
+ err = engine->emit_flush(rq, EMIT_INVALIDATE);
+ if (err)
goto err_unpin;
- ret = req->engine->emit_bb_start(req,
- so->batch_offset, so->batch_size,
- I915_DISPATCH_SECURE);
- if (ret)
+ err = engine->emit_bb_start(rq,
+ so.batch_offset, so.batch_size,
+ I915_DISPATCH_SECURE);
+ if (err)
goto err_unpin;
- if (so->aux_size > 8) {
- ret = req->engine->emit_bb_start(req,
- so->aux_offset, so->aux_size,
- I915_DISPATCH_SECURE);
- if (ret)
+ if (so.aux_size > 8) {
+ err = engine->emit_bb_start(rq,
+ so.aux_offset, so.aux_size,
+ I915_DISPATCH_SECURE);
+ if (err)
goto err_unpin;
}
- i915_vma_move_to_active(so->vma, req, 0);
+ i915_vma_move_to_active(so.vma, rq, 0);
err_unpin:
- i915_vma_unpin(so->vma);
- return ret;
-}
-
-void i915_gem_render_state_fini(struct intel_engine_cs *engine)
-{
- struct intel_render_state *so;
- struct drm_i915_gem_object *obj;
-
- so = fetch_and_zero(&engine->render_state);
- if (!so)
- return;
-
- obj = so->vma->obj;
-
- i915_vma_close(so->vma);
- __i915_gem_object_release_unless_active(obj);
-
- kfree(so);
+ i915_vma_unpin(so.vma);
+err_vma:
+ i915_vma_close(so.vma);
+err_obj:
+ __i915_gem_object_release_unless_active(so.obj);
+ return err;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.h b/drivers/gpu/drm/i915/i915_gem_render_state.h
index 87481845799d..86369520482e 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.h
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.h
@@ -26,8 +26,6 @@
struct drm_i915_gem_request;
-int i915_gem_render_state_init(struct intel_engine_cs *engine);
-int i915_gem_render_state_emit(struct drm_i915_gem_request *req);
-void i915_gem_render_state_fini(struct intel_engine_cs *engine);
+int i915_gem_render_state_emit(struct drm_i915_gem_request *rq);
#endif /* _I915_GEM_RENDER_STATE_H_ */
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 93bacaee525b..993d6ba87e84 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -641,21 +641,15 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
if (ret)
goto err_unpin_preempt;
- ret = i915_gem_render_state_init(engine);
- if (ret)
- goto err_breadcrumbs;
-
if (HWS_NEEDS_PHYSICAL(engine->i915))
ret = init_phys_status_page(engine);
else
ret = init_status_page(engine);
if (ret)
- goto err_rs_fini;
+ goto err_breadcrumbs;
return 0;
-err_rs_fini:
- i915_gem_render_state_fini(engine);
err_breadcrumbs:
intel_engine_fini_breadcrumbs(engine);
err_unpin_preempt:
@@ -682,7 +676,6 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
else
cleanup_status_page(engine);
- i915_gem_render_state_fini(engine);
intel_engine_fini_breadcrumbs(engine);
intel_engine_cleanup_cmd_parser(engine);
i915_gem_batch_pool_fini(&engine->batch_pool);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f96225a6a369..9a2cf6938f55 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -136,6 +136,7 @@
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_gem_render_state.h"
#include "intel_mocs.h"
#define RING_EXECLIST_QFULL (1 << 0x2)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 464dc58af27b..3321b801e77d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -28,9 +28,12 @@
*/
#include <linux/log2.h>
+
#include <drm/drmP.h>
-#include "i915_drv.h"
#include <drm/i915_drm.h>
+
+#include "i915_drv.h"
+#include "i915_gem_render_state.h"
#include "i915_trace.h"
#include "intel_drv.h"
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 0412d0434015..9ad6ac18766b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -165,7 +165,6 @@ struct i915_ctx_workarounds {
};
struct drm_i915_gem_request;
-struct intel_render_state;
/*
* Engine IDs definitions.
@@ -307,7 +306,6 @@ struct intel_engine_cs {
struct intel_timeline *timeline;
struct drm_i915_gem_object *default_state;
- struct intel_render_state *render_state;
atomic_t irq_count;
unsigned long irq_posted;
--
2.15.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* ✗ Fi.CI.BAT: warning for series starting with [v2,1/9] drm/i915: Define an engine class enum for the uABI
2017-11-03 13:34 [PATCH v2 1/9] drm/i915: Define an engine class enum for the uABI Chris Wilson
` (7 preceding siblings ...)
2017-11-03 13:34 ` [PATCH v2 9/9] drm/i915: Stop caching the "golden" renderstate Chris Wilson
@ 2017-11-03 14:01 ` Patchwork
2017-11-03 14:08 ` [PATCH v3] " Chris Wilson
` (2 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2017-11-03 14:01 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/9] drm/i915: Define an engine class enum for the uABI
URL : https://patchwork.freedesktop.org/series/33126/
State : warning
== Summary ==
Series 33126v1 series starting with [v2,1/9] drm/i915: Define an engine class enum for the uABI
https://patchwork.freedesktop.org/api/1.0/series/33126/revisions/1/mbox/
Test chamelium:
Subgroup dp-crc-fast:
incomplete -> FAIL (fi-kbl-7500u) fdo#102514
Test gem_ctx_basic:
pass -> DMESG-WARN (fi-bsw-n3050)
fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:448s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:453s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:381s
fi-bsw-n3050 total:289 pass:242 dwarn:1 dfail:0 fail:0 skip:46 time:536s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:276s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:507s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:501s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:508s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:493s
fi-cfl-s total:289 pass:254 dwarn:3 dfail:0 fail:0 skip:32 time:546s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:432s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:264s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:584s
fi-glk-dsi total:289 pass:258 dwarn:0 dfail:0 fail:1 skip:30 time:499s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:425s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:426s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:424s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:471s
fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:486s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:576s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:477s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:586s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:571s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:453s
fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:594s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:651s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:523s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:505s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:460s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:565s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:421s
2f945d948d05de1dd4bd1ca14eac40ff563d9d77 drm-tip: 2017y-11m-03d-09h-28m-20s UTC integration manifest
b7572ccc9c6b drm/i915: Stop caching the "golden" renderstate
8f725a680ec8 drm/i915: Remove redundant intel_autoenable_gt_powersave()
d603949c4d90 drm/i915: Report whether we have true context isolation
d1651ce7aa25 drm/i915: Record the default hw state after reset upon load
da3d4addbc12 drm/i915: Mark the context state as dirty/written
6a3433e0f9e8 drm/i915: Inline intel_modeset_gem_init()
abb3f126c154 drm/i915: Move GT powersaving init to i915_gem_init()
cf64f9f10746 drm/i915: Force the switch to the i915->kernel_context
11687a55318a drm/i915: Define an engine class enum for the uABI
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6939/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH v3] drm/i915: Define an engine class enum for the uABI
2017-11-03 13:34 [PATCH v2 1/9] drm/i915: Define an engine class enum for the uABI Chris Wilson
` (8 preceding siblings ...)
2017-11-03 14:01 ` ✗ Fi.CI.BAT: warning for series starting with [v2,1/9] drm/i915: Define an engine class enum for the uABI Patchwork
@ 2017-11-03 14:08 ` Chris Wilson
2017-11-03 14:58 ` ✓ Fi.CI.BAT: success for series starting with [v3] drm/i915: Define an engine class enum for the uABI (rev2) Patchwork
2017-11-03 18:06 ` ✗ Fi.CI.IGT: failure " Patchwork
11 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2017-11-03 14:08 UTC (permalink / raw)
To: intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
We want to be able to report back to userspace details about an engine's
class, and in return for userspace to be able to request actions
regarding certain classes of engines. To isolate the uABI from any
variations between hw generations, we define an abstract class for the
engines and internally map onto the hw.
v2: Remove MAX from the uABI; keep it internal if we need it, but don't
let userspace make the mistake of using it themselves.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 10 +++++++++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++++-
include/uapi/drm/i915_drm.h | 15 +++++++++++++++
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index ddbe5c9bf45a..0987768c311d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -50,6 +50,8 @@ struct engine_class_info {
const char *name;
int (*init_legacy)(struct intel_engine_cs *engine);
int (*init_execlists)(struct intel_engine_cs *engine);
+
+ u8 uabi_class;
};
static const struct engine_class_info intel_engine_classes[] = {
@@ -57,21 +59,25 @@ static const struct engine_class_info intel_engine_classes[] = {
.name = "rcs",
.init_execlists = logical_render_ring_init,
.init_legacy = intel_init_render_ring_buffer,
+ .uabi_class = I915_ENGINE_CLASS_RENDER,
},
[COPY_ENGINE_CLASS] = {
.name = "bcs",
.init_execlists = logical_xcs_ring_init,
.init_legacy = intel_init_blt_ring_buffer,
+ .uabi_class = I915_ENGINE_CLASS_COPY,
},
[VIDEO_DECODE_CLASS] = {
.name = "vcs",
.init_execlists = logical_xcs_ring_init,
.init_legacy = intel_init_bsd_ring_buffer,
+ .uabi_class = I915_ENGINE_CLASS_VIDEO,
},
[VIDEO_ENHANCEMENT_CLASS] = {
.name = "vecs",
.init_execlists = logical_xcs_ring_init,
.init_legacy = intel_init_vebox_ring_buffer,
+ .uabi_class = I915_ENGINE_CLASS_VIDEO_ENHANCE,
},
};
@@ -213,13 +219,15 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s%u",
class_info->name, info->instance) >=
sizeof(engine->name));
- engine->uabi_id = info->uabi_id;
engine->hw_id = engine->guc_id = info->hw_id;
engine->mmio_base = info->mmio_base;
engine->irq_shift = info->irq_shift;
engine->class = info->class;
engine->instance = info->instance;
+ engine->uabi_id = info->uabi_id;
+ engine->uabi_class = class_info->uabi_class;
+
engine->context_size = __intel_engine_context_size(dev_priv,
engine->class);
if (WARN_ON(engine->context_size > BIT(20)))
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 69ad875fd011..f3dbfe7ae6e4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -289,11 +289,14 @@ struct intel_engine_execlists {
struct intel_engine_cs {
struct drm_i915_private *i915;
char name[INTEL_ENGINE_CS_MAX_NAME];
+
enum intel_engine_id id;
- unsigned int uabi_id;
unsigned int hw_id;
unsigned int guc_id;
+ u8 uabi_id;
+ u8 uabi_class;
+
u8 class;
u8 instance;
u32 context_size;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index ac3c6503ca27..65d06da62599 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -86,6 +86,21 @@ enum i915_mocs_table_index {
I915_MOCS_CACHED,
};
+/*
+ * Different engines serve different roles, and there may be more than one
+ * engine serving each role. enum drm_i915_gem_engine_class provides a
+ * classification of the role of the engine, which may be used when requesting
+ * operations to be performed on a certain subset of engines, or for providing
+ * information about that group.
+ */
+enum drm_i915_gem_engine_class {
+ I915_ENGINE_CLASS_OTHER = 0,
+ I915_ENGINE_CLASS_RENDER = 1,
+ I915_ENGINE_CLASS_COPY = 2,
+ I915_ENGINE_CLASS_VIDEO = 3,
+ I915_ENGINE_CLASS_VIDEO_ENHANCE = 4,
+};
+
/* Each region is a minimum of 16k, and there are at most 255 of them.
*/
#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
--
2.15.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [v3] drm/i915: Define an engine class enum for the uABI (rev2)
2017-11-03 13:34 [PATCH v2 1/9] drm/i915: Define an engine class enum for the uABI Chris Wilson
` (9 preceding siblings ...)
2017-11-03 14:08 ` [PATCH v3] " Chris Wilson
@ 2017-11-03 14:58 ` Patchwork
2017-11-03 18:06 ` ✗ Fi.CI.IGT: failure " Patchwork
11 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2017-11-03 14:58 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3] drm/i915: Define an engine class enum for the uABI (rev2)
URL : https://patchwork.freedesktop.org/series/33126/
State : success
== Summary ==
Series 33126v2 series starting with [v3] drm/i915: Define an engine class enum for the uABI
https://patchwork.freedesktop.org/api/1.0/series/33126/revisions/2/mbox/
Test gem_exec_flush:
Subgroup basic-wb-set-default:
incomplete -> PASS (fi-glk-dsi)
Test gem_exec_reloc:
Subgroup basic-write-gtt-active:
fail -> PASS (fi-gdg-551) fdo#102582
Test kms_busy:
Subgroup basic-flip-b:
fail -> PASS (fi-bwr-2160)
Test drv_module_reload:
Subgroup basic-no-display:
fail -> PASS (fi-hsw-4770r) fdo#103534
fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#103534 https://bugs.freedesktop.org/show_bug.cgi?id=103534
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:450s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:453s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:381s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:550s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:276s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:511s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:509s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:507s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:494s
fi-cfl-s total:289 pass:254 dwarn:3 dfail:0 fail:0 skip:32 time:557s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:432s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:261s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:592s
fi-glk-dsi total:289 pass:258 dwarn:0 dfail:0 fail:1 skip:30 time:491s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:432s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:433s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:425s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:491s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:461s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:491s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:573s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:479s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:573s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:456s
fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:594s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:655s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:519s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:500s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:460s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:570s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:417s
de359919ae463cdaef6bc6890156df84e19dee2a drm-tip: 2017y-11m-03d-14h-00m-37s UTC integration manifest
5212a26f9347 drm/i915: Stop caching the "golden" renderstate
487541f6719d drm/i915: Remove redundant intel_autoenable_gt_powersave()
4c78fcebc2a4 drm/i915: Report whether we have true context isolation
f252a2305dc3 drm/i915: Record the default hw state after reset upon load
5a4daa465e8e drm/i915: Mark the context state as dirty/written
221f5015aa7d drm/i915: Inline intel_modeset_gem_init()
412e87887b69 drm/i915: Move GT powersaving init to i915_gem_init()
de4168ba7608 drm/i915: Force the switch to the i915->kernel_context
a695d588d8ed drm/i915: Define an engine class enum for the uABI
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6940/
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^ permalink raw reply [flat|nested] 18+ messages in thread* ✗ Fi.CI.IGT: failure for series starting with [v3] drm/i915: Define an engine class enum for the uABI (rev2)
2017-11-03 13:34 [PATCH v2 1/9] drm/i915: Define an engine class enum for the uABI Chris Wilson
` (10 preceding siblings ...)
2017-11-03 14:58 ` ✓ Fi.CI.BAT: success for series starting with [v3] drm/i915: Define an engine class enum for the uABI (rev2) Patchwork
@ 2017-11-03 18:06 ` Patchwork
11 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2017-11-03 18:06 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3] drm/i915: Define an engine class enum for the uABI (rev2)
URL : https://patchwork.freedesktop.org/series/33126/
State : failure
== Summary ==
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-B:
pass -> DMESG-WARN (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test pm_rpm:
Subgroup i2c:
pass -> FAIL (shard-hsw)
Subgroup system-suspend-modeset:
pass -> FAIL (shard-hsw)
Subgroup cursor:
pass -> FAIL (shard-hsw)
Subgroup debugfs-forcewake-user:
pass -> FAIL (shard-hsw)
Subgroup gem-pread:
pass -> FAIL (shard-hsw)
Subgroup gem-execbuf:
pass -> FAIL (shard-hsw)
Subgroup system-suspend-execbuf:
pass -> DMESG-FAIL (shard-hsw)
Subgroup drm-resources-equal:
pass -> FAIL (shard-hsw)
Subgroup dpms-mode-unset-non-lpsp:
pass -> FAIL (shard-hsw)
Subgroup gem-idle:
pass -> FAIL (shard-hsw)
Subgroup system-suspend:
pass -> DMESG-FAIL (shard-hsw)
Subgroup dpms-mode-unset-lpsp:
skip -> FAIL (shard-hsw)
Subgroup cursor-dpms:
pass -> FAIL (shard-hsw)
Subgroup basic-pci-d3-state:
pass -> FAIL (shard-hsw)
Subgroup universal-planes:
pass -> FAIL (shard-hsw)
Subgroup dpms-lpsp:
skip -> FAIL (shard-hsw)
Subgroup modeset-stress-extra-wait:
pass -> FAIL (shard-hsw)
Subgroup legacy-planes-dpms:
pass -> FAIL (shard-hsw)
Subgroup modeset-lpsp-stress:
skip -> FAIL (shard-hsw)
Subgroup modeset-non-lpsp:
pass -> FAIL (shard-hsw)
Subgroup gem-evict-pwrite:
pass -> FAIL (shard-hsw)
Test kms_flip:
Subgroup vblank-vs-modeset-rpm:
pass -> FAIL (shard-hsw)
Subgroup vblank-vs-dpms-rpm-interruptible:
pass -> FAIL (shard-hsw)
Subgroup vblank-vs-suspend-interruptible:
pass -> DMESG-WARN (shard-hsw) fdo#100368
Subgroup vblank-vs-dpms-suspend:
pass -> DMESG-WARN (shard-hsw)
Subgroup vblank-vs-dpms-rpm:
pass -> FAIL (shard-hsw)
Subgroup vblank-vs-modeset-rpm-interruptible:
pass -> FAIL (shard-hsw)
Test kms_cursor_crc:
Subgroup cursor-256x256-suspend:
pass -> DMESG-WARN (shard-hsw)
Subgroup cursor-64x64-suspend:
pass -> DMESG-WARN (shard-hsw)
Test drv_suspend:
Subgroup fence-restore-untiled-hibernate:
dmesg-fail -> FAIL (shard-hsw) fdo#103375
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
shard-hsw total:2539 pass:1407 dwarn:5 dfail:2 fail:31 skip:1094 time:9101s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6940/shards.html
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^ permalink raw reply [flat|nested] 18+ messages in thread