From: Michal Wajdeczko <michal.wajdeczko@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v4 4/5] drm/i915/guc: Simplify programming of GUC_SHIM_CONTROL
Date: Fri, 3 Nov 2017 15:18:15 +0000 [thread overview]
Message-ID: <20171103151816.62048-4-michal.wajdeczko@intel.com> (raw)
In-Reply-To: <20171103151816.62048-1-michal.wajdeczko@intel.com>
We can program GUC_SHIM_CONTROL register with all expected
bits without use of extra macro defined in fwif.h
v2: rebased without pre-prod code
v3: fixed typo
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/i915_guc_reg.h | 7 -------
drivers/gpu/drm/i915/intel_guc_fw.c | 9 +++++++--
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 35cf991..bc1ae7d 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -102,13 +102,6 @@
#define GUC_ENABLE_MIA_CLOCK_GATING (1<<15)
#define GUC_GEN10_SHIM_WC_ENABLE (1<<21)
-#define GUC_SHIM_CONTROL_VALUE (GUC_DISABLE_SRAM_INIT_TO_ZEROES | \
- GUC_ENABLE_READ_CACHE_LOGIC | \
- GUC_ENABLE_MIA_CACHING | \
- GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | \
- GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | \
- GUC_ENABLE_MIA_CLOCK_GATING)
-
#define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
#define GUC_SEND_TRIGGER (1<<0)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index a63b5cf..69ba015 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -101,8 +101,13 @@ static void guc_prepare_xfer(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
- /* Enable MIA caching. GuC clock gating is disabled. */
- I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
+ /* Must program this register before loading the ucode with DMA */
+ I915_WRITE(GUC_SHIM_CONTROL, GUC_DISABLE_SRAM_INIT_TO_ZEROES |
+ GUC_ENABLE_READ_CACHE_LOGIC |
+ GUC_ENABLE_MIA_CACHING |
+ GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
+ GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
+ GUC_ENABLE_MIA_CLOCK_GATING);
if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
--
2.7.4
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next prev parent reply other threads:[~2017-11-03 15:19 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-03 15:18 [PATCH v4 1/5] drm/i915/guc: Split GuC firmware xfer function into clear steps Michal Wajdeczko
2017-11-03 15:18 ` [PATCH v4 2/5] drm/i915/guc: Wait for ucode DMA transfer completion Michal Wajdeczko
2017-11-08 20:36 ` Chris Wilson
2017-11-08 21:17 ` Michal Wajdeczko
2017-11-08 21:26 ` Chris Wilson
2017-11-03 15:18 ` [PATCH v4 3/5] drm/i915/guc: Drop legacy workarounds from guc_prepare_xfer Michal Wajdeczko
2017-11-03 16:17 ` Sagar Arun Kamble
2017-11-03 15:18 ` Michal Wajdeczko [this message]
2017-11-03 16:20 ` [PATCH v4 4/5] drm/i915/guc: Simplify programming of GUC_SHIM_CONTROL Sagar Arun Kamble
2017-11-03 15:18 ` [PATCH v4 5/5] HAX enable GuC submission for CI Michal Wajdeczko
2017-11-03 15:52 ` ✓ Fi.CI.BAT: success for series starting with [v4,1/5] drm/i915/guc: Split GuC firmware xfer function into clear steps Patchwork
2017-11-08 21:48 ` Chris Wilson
2017-11-03 18:16 ` ✗ Fi.CI.IGT: warning " Patchwork
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