Re: [PATCH 1/7] drm/i915/cnl: Remove spurious central_freq.

[Manasi Navare <manasi.d.navare@intel.com>]

Verified this from the Bspec that central frequency should
be left at default at 8400MHz which is value 3 in cfgcr1.central_freq.
Looks good to me.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

On Tue, Nov 14, 2017 at 11:47:53AM -0800, Rodrigo Vivi wrote:
> "Display software must leave this field at the default value.
> It no longer needs to be configured as part of PLL programming."
> 
> We respect this already and we are setting up the default
> one line below: "DPLL_CFGCR1_CENTRAL_FREQ".
> 
> Also we don't touch anywhere else this central_freq for cnl.
> So let's remove from the final write.
> 
> No functional change. Only a clean-up patch.
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index be74d4767c8a..61c684ac47af 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2265,7 +2265,6 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
>  		DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) |
>  		DPLL_CFGCR1_KDIV(wrpll_params.kdiv) |
>  		DPLL_CFGCR1_PDIV(wrpll_params.pdiv) |
> -		wrpll_params.central_freq |
>  		DPLL_CFGCR1_CENTRAL_FREQ;
>  
>  	memset(&crtc_state->dpll_hw_state, 0,
> -- 
> 2.13.6
> 
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