* [PATCH 1/7] drm/i915/cnl: Remove spurious central_freq.
2017-11-14 19:47 [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
@ 2017-11-14 19:47 ` Rodrigo Vivi
2017-11-14 20:40 ` Manasi Navare
2017-11-14 19:47 ` [PATCH 2/7] drm/i915/cnl: Remove useless conversion Rodrigo Vivi
` (12 subsequent siblings)
13 siblings, 1 reply; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-14 19:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
"Display software must leave this field at the default value.
It no longer needs to be configured as part of PLL programming."
We respect this already and we are setting up the default
one line below: "DPLL_CFGCR1_CENTRAL_FREQ".
Also we don't touch anywhere else this central_freq for cnl.
So let's remove from the final write.
No functional change. Only a clean-up patch.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index be74d4767c8a..61c684ac47af 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2265,7 +2265,6 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) |
DPLL_CFGCR1_KDIV(wrpll_params.kdiv) |
DPLL_CFGCR1_PDIV(wrpll_params.pdiv) |
- wrpll_params.central_freq |
DPLL_CFGCR1_CENTRAL_FREQ;
memset(&crtc_state->dpll_hw_state, 0,
--
2.13.6
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 1/7] drm/i915/cnl: Remove spurious central_freq.
2017-11-14 19:47 ` [PATCH 1/7] drm/i915/cnl: Remove spurious central_freq Rodrigo Vivi
@ 2017-11-14 20:40 ` Manasi Navare
0 siblings, 0 replies; 43+ messages in thread
From: Manasi Navare @ 2017-11-14 20:40 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
Verified this from the Bspec that central frequency should
be left at default at 8400MHz which is value 3 in cfgcr1.central_freq.
Looks good to me.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
On Tue, Nov 14, 2017 at 11:47:53AM -0800, Rodrigo Vivi wrote:
> "Display software must leave this field at the default value.
> It no longer needs to be configured as part of PLL programming."
>
> We respect this already and we are setting up the default
> one line below: "DPLL_CFGCR1_CENTRAL_FREQ".
>
> Also we don't touch anywhere else this central_freq for cnl.
> So let's remove from the final write.
>
> No functional change. Only a clean-up patch.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index be74d4767c8a..61c684ac47af 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2265,7 +2265,6 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
> DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) |
> DPLL_CFGCR1_KDIV(wrpll_params.kdiv) |
> DPLL_CFGCR1_PDIV(wrpll_params.pdiv) |
> - wrpll_params.central_freq |
> DPLL_CFGCR1_CENTRAL_FREQ;
>
> memset(&crtc_state->dpll_hw_state, 0,
> --
> 2.13.6
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 2/7] drm/i915/cnl: Remove useless conversion.
2017-11-14 19:47 [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
2017-11-14 19:47 ` [PATCH 1/7] drm/i915/cnl: Remove spurious central_freq Rodrigo Vivi
@ 2017-11-14 19:47 ` Rodrigo Vivi
2017-11-14 20:56 ` Manasi Navare
2017-11-14 19:47 ` [PATCH 3/7] drm/i915/cnl: Fix, simplify and unify wrpll variable sizes Rodrigo Vivi
` (11 subsequent siblings)
13 siblings, 1 reply; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-14 19:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
No functional change. Just starting the wrpll fixes
with a clean-up to make units a bit more clear.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 61c684ac47af..db7afd314462 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2198,11 +2198,11 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params, uint32_t
}
static bool
-cnl_ddi_calculate_wrpll(int clock /* in Hz */,
+cnl_ddi_calculate_wrpll(int clock,
struct drm_i915_private *dev_priv,
struct skl_wrpll_params *wrpll_params)
{
- uint64_t afe_clock = clock * 5 / KHz(1); /* clocks in kHz */
+ uint64_t afe_clock = clock * 5;
unsigned int dco_min = 7998 * KHz(1);
unsigned int dco_max = 10000 * KHz(1);
unsigned int dco_mid = (dco_min + dco_max) / 2;
@@ -2255,7 +2255,7 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
- if (!cnl_ddi_calculate_wrpll(clock * 1000, dev_priv, &wrpll_params))
+ if (!cnl_ddi_calculate_wrpll(clock, dev_priv, &wrpll_params))
return false;
cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
--
2.13.6
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 2/7] drm/i915/cnl: Remove useless conversion.
2017-11-14 19:47 ` [PATCH 2/7] drm/i915/cnl: Remove useless conversion Rodrigo Vivi
@ 2017-11-14 20:56 ` Manasi Navare
2017-11-15 12:52 ` Jani Nikula
0 siblings, 1 reply; 43+ messages in thread
From: Manasi Navare @ 2017-11-14 20:56 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Nov 14, 2017 at 11:47:54AM -0800, Rodrigo Vivi wrote:
> No functional change. Just starting the wrpll fixes
> with a clean-up to make units a bit more clear.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 61c684ac47af..db7afd314462 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2198,11 +2198,11 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params, uint32_t
> }
>
> static bool
> -cnl_ddi_calculate_wrpll(int clock /* in Hz */,
Now the clock sent is already in KHz, should we have that in the comment either
in the argument or afe_clock calculation?
Apart from this nitpick, looks good.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> +cnl_ddi_calculate_wrpll(int clock,
> struct drm_i915_private *dev_priv,
> struct skl_wrpll_params *wrpll_params)
> {
> - uint64_t afe_clock = clock * 5 / KHz(1); /* clocks in kHz */
> + uint64_t afe_clock = clock * 5;
> unsigned int dco_min = 7998 * KHz(1);
> unsigned int dco_max = 10000 * KHz(1);
> unsigned int dco_mid = (dco_min + dco_max) / 2;
> @@ -2255,7 +2255,7 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
>
> cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
>
> - if (!cnl_ddi_calculate_wrpll(clock * 1000, dev_priv, &wrpll_params))
> + if (!cnl_ddi_calculate_wrpll(clock, dev_priv, &wrpll_params))
> return false;
>
> cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
> --
> 2.13.6
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 2/7] drm/i915/cnl: Remove useless conversion.
2017-11-14 20:56 ` Manasi Navare
@ 2017-11-15 12:52 ` Jani Nikula
0 siblings, 0 replies; 43+ messages in thread
From: Jani Nikula @ 2017-11-15 12:52 UTC (permalink / raw)
To: Manasi Navare, Rodrigo Vivi; +Cc: intel-gfx
On Tue, 14 Nov 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> On Tue, Nov 14, 2017 at 11:47:54AM -0800, Rodrigo Vivi wrote:
>> No functional change. Just starting the wrpll fixes
>> with a clean-up to make units a bit more clear.
>>
>> Cc: Mika Kahola <mika.kahola@intel.com>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: James Ausmus <james.ausmus@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> index 61c684ac47af..db7afd314462 100644
>> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> @@ -2198,11 +2198,11 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params, uint32_t
>> }
>>
>> static bool
>> -cnl_ddi_calculate_wrpll(int clock /* in Hz */,
>
> Now the clock sent is already in KHz, should we have that in the comment either
> in the argument or afe_clock calculation?
> Apart from this nitpick, looks good.
We use kHz for clocks all over the place, IMO only any deviation from
that needs to be documented.
BR,
Jani.
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>
>> +cnl_ddi_calculate_wrpll(int clock,
>> struct drm_i915_private *dev_priv,
>> struct skl_wrpll_params *wrpll_params)
>> {
>> - uint64_t afe_clock = clock * 5 / KHz(1); /* clocks in kHz */
>> + uint64_t afe_clock = clock * 5;
>> unsigned int dco_min = 7998 * KHz(1);
>> unsigned int dco_max = 10000 * KHz(1);
>> unsigned int dco_mid = (dco_min + dco_max) / 2;
>> @@ -2255,7 +2255,7 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
>>
>> cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
>>
>> - if (!cnl_ddi_calculate_wrpll(clock * 1000, dev_priv, &wrpll_params))
>> + if (!cnl_ddi_calculate_wrpll(clock, dev_priv, &wrpll_params))
>> return false;
>>
>> cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
>> --
>> 2.13.6
>>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 3/7] drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.
2017-11-14 19:47 [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
2017-11-14 19:47 ` [PATCH 1/7] drm/i915/cnl: Remove spurious central_freq Rodrigo Vivi
2017-11-14 19:47 ` [PATCH 2/7] drm/i915/cnl: Remove useless conversion Rodrigo Vivi
@ 2017-11-14 19:47 ` Rodrigo Vivi
2017-11-14 21:09 ` Manasi Navare
2017-11-14 19:47 ` [PATCH 4/7] drm/i915/cnl: Fix wrpll math for higher freqs Rodrigo Vivi
` (10 subsequent siblings)
13 siblings, 1 reply; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-14 19:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
- 64 bits is not needed for afe_clock now we don't convert
that to Hz.
- 16 bits is not enough for all dco stuff.
- unsigned is not relevant/needed for all divisors values.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 30 ++++++++++++------------------
1 file changed, 12 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index db7afd314462..fba969cbda37 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2110,10 +2110,8 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
return ret;
}
-static void cnl_wrpll_get_multipliers(unsigned int bestdiv,
- unsigned int *pdiv,
- unsigned int *qdiv,
- unsigned int *kdiv)
+static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv,
+ int *qdiv, int *kdiv)
{
/* even dividers */
if (bestdiv % 2 == 0) {
@@ -2151,9 +2149,9 @@ static void cnl_wrpll_get_multipliers(unsigned int bestdiv,
}
}
-static void cnl_wrpll_params_populate(struct skl_wrpll_params *params, uint32_t dco_freq,
- uint32_t ref_freq, uint32_t pdiv, uint32_t qdiv,
- uint32_t kdiv)
+static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
+ u32 dco_freq, u32 ref_freq,
+ int pdiv, int qdiv, int kdiv)
{
switch (kdiv) {
case 1:
@@ -2202,23 +2200,19 @@ cnl_ddi_calculate_wrpll(int clock,
struct drm_i915_private *dev_priv,
struct skl_wrpll_params *wrpll_params)
{
- uint64_t afe_clock = clock * 5;
- unsigned int dco_min = 7998 * KHz(1);
- unsigned int dco_max = 10000 * KHz(1);
- unsigned int dco_mid = (dco_min + dco_max) / 2;
-
+ u32 afe_clock = clock * 5;
+ u32 dco_min = 7998 * KHz(1);
+ u32 dco_max = 10000 * KHz(1);
+ u32 dco_mid = (dco_min + dco_max) / 2;
static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
18, 20, 24, 28, 30, 32, 36, 40,
42, 44, 48, 50, 52, 54, 56, 60,
64, 66, 68, 70, 72, 76, 78, 80,
84, 88, 90, 92, 96, 98, 100, 102,
3, 5, 7, 9, 15, 21 };
- unsigned int d, dco;
- unsigned int dco_centrality = 0;
- unsigned int best_dco_centrality = 999999;
- unsigned int best_div = 0;
- unsigned int best_dco = 0;
- unsigned int pdiv = 0, qdiv = 0, kdiv = 0;
+ u32 dco, best_dco = 0, dco_centrality = 0;
+ u32 best_dco_centrality = 999999;
+ int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
for (d = 0; d < ARRAY_SIZE(dividers); d++) {
dco = afe_clock * dividers[d];
--
2.13.6
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 3/7] drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.
2017-11-14 19:47 ` [PATCH 3/7] drm/i915/cnl: Fix, simplify and unify wrpll variable sizes Rodrigo Vivi
@ 2017-11-14 21:09 ` Manasi Navare
0 siblings, 0 replies; 43+ messages in thread
From: Manasi Navare @ 2017-11-14 21:09 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Nov 14, 2017 at 11:47:55AM -0800, Rodrigo Vivi wrote:
> - 64 bits is not needed for afe_clock now we don't convert
> that to Hz.
> - 16 bits is not enough for all dco stuff.
> - unsigned is not relevant/needed for all divisors values.
>
Yup great catch, DCO stuff needs 3 bytes so we need to define it as
u32.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 30 ++++++++++++------------------
> 1 file changed, 12 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index db7afd314462..fba969cbda37 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2110,10 +2110,8 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
> return ret;
> }
>
> -static void cnl_wrpll_get_multipliers(unsigned int bestdiv,
> - unsigned int *pdiv,
> - unsigned int *qdiv,
> - unsigned int *kdiv)
> +static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv,
> + int *qdiv, int *kdiv)
> {
> /* even dividers */
> if (bestdiv % 2 == 0) {
> @@ -2151,9 +2149,9 @@ static void cnl_wrpll_get_multipliers(unsigned int bestdiv,
> }
> }
>
> -static void cnl_wrpll_params_populate(struct skl_wrpll_params *params, uint32_t dco_freq,
> - uint32_t ref_freq, uint32_t pdiv, uint32_t qdiv,
> - uint32_t kdiv)
> +static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
> + u32 dco_freq, u32 ref_freq,
> + int pdiv, int qdiv, int kdiv)
> {
> switch (kdiv) {
> case 1:
> @@ -2202,23 +2200,19 @@ cnl_ddi_calculate_wrpll(int clock,
> struct drm_i915_private *dev_priv,
> struct skl_wrpll_params *wrpll_params)
> {
> - uint64_t afe_clock = clock * 5;
> - unsigned int dco_min = 7998 * KHz(1);
> - unsigned int dco_max = 10000 * KHz(1);
> - unsigned int dco_mid = (dco_min + dco_max) / 2;
> -
> + u32 afe_clock = clock * 5;
> + u32 dco_min = 7998 * KHz(1);
> + u32 dco_max = 10000 * KHz(1);
> + u32 dco_mid = (dco_min + dco_max) / 2;
> static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
> 18, 20, 24, 28, 30, 32, 36, 40,
> 42, 44, 48, 50, 52, 54, 56, 60,
> 64, 66, 68, 70, 72, 76, 78, 80,
> 84, 88, 90, 92, 96, 98, 100, 102,
> 3, 5, 7, 9, 15, 21 };
> - unsigned int d, dco;
> - unsigned int dco_centrality = 0;
> - unsigned int best_dco_centrality = 999999;
> - unsigned int best_div = 0;
> - unsigned int best_dco = 0;
> - unsigned int pdiv = 0, qdiv = 0, kdiv = 0;
> + u32 dco, best_dco = 0, dco_centrality = 0;
> + u32 best_dco_centrality = 999999;
> + int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
>
> for (d = 0; d < ARRAY_SIZE(dividers); d++) {
> dco = afe_clock * dividers[d];
> --
> 2.13.6
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 4/7] drm/i915/cnl: Fix wrpll math for higher freqs.
2017-11-14 19:47 [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
` (2 preceding siblings ...)
2017-11-14 19:47 ` [PATCH 3/7] drm/i915/cnl: Fix, simplify and unify wrpll variable sizes Rodrigo Vivi
@ 2017-11-14 19:47 ` Rodrigo Vivi
2017-11-14 20:00 ` Ville Syrjälä
2017-11-15 8:06 ` [PATCH 4/7] " Mika Kahola
2017-11-14 19:47 ` [PATCH 5/7] drm/i915/cnl: Don't blindly replace qdiv Rodrigo Vivi
` (9 subsequent siblings)
13 siblings, 2 replies; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-14 19:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Spec describe all values in MHz. We handle our
clocks in KHz. This includes the best_dco_centrality that was
forgot in the same unity as spec. Consequently we couldn't
get a good divider for high frequenies. Hence HDMI 2.0 wasn't
working.
This patch also replaces the use of "* KHz(1)" with the values
directly on KHz to avoid future confusion.
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index fba969cbda37..53f650f56148 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2201,8 +2201,8 @@ cnl_ddi_calculate_wrpll(int clock,
struct skl_wrpll_params *wrpll_params)
{
u32 afe_clock = clock * 5;
- u32 dco_min = 7998 * KHz(1);
- u32 dco_max = 10000 * KHz(1);
+ u32 dco_min = 7998000;
+ u32 dco_max = 10000000;
u32 dco_mid = (dco_min + dco_max) / 2;
static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
18, 20, 24, 28, 30, 32, 36, 40,
@@ -2211,7 +2211,7 @@ cnl_ddi_calculate_wrpll(int clock,
84, 88, 90, 92, 96, 98, 100, 102,
3, 5, 7, 9, 15, 21 };
u32 dco, best_dco = 0, dco_centrality = 0;
- u32 best_dco_centrality = 999999;
+ u32 best_dco_centrality = 999999000;
int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
for (d = 0; d < ARRAY_SIZE(dividers); d++) {
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 4/7] drm/i915/cnl: Fix wrpll math for higher freqs.
2017-11-14 19:47 ` [PATCH 4/7] drm/i915/cnl: Fix wrpll math for higher freqs Rodrigo Vivi
@ 2017-11-14 20:00 ` Ville Syrjälä
2017-11-14 20:09 ` Rodrigo Vivi
2017-11-14 23:42 ` [PATCH] " Rodrigo Vivi
2017-11-15 8:06 ` [PATCH 4/7] " Mika Kahola
1 sibling, 2 replies; 43+ messages in thread
From: Ville Syrjälä @ 2017-11-14 20:00 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Nov 14, 2017 at 11:47:56AM -0800, Rodrigo Vivi wrote:
> Spec describe all values in MHz. We handle our
> clocks in KHz. This includes the best_dco_centrality that was
> forgot in the same unity as spec. Consequently we couldn't
> get a good divider for high frequenies. Hence HDMI 2.0 wasn't
> working.
>
> This patch also replaces the use of "* KHz(1)" with the values
> directly on KHz to avoid future confusion.
>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index fba969cbda37..53f650f56148 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2201,8 +2201,8 @@ cnl_ddi_calculate_wrpll(int clock,
> struct skl_wrpll_params *wrpll_params)
> {
> u32 afe_clock = clock * 5;
> - u32 dco_min = 7998 * KHz(1);
> - u32 dco_max = 10000 * KHz(1);
> + u32 dco_min = 7998000;
> + u32 dco_max = 10000000;
> u32 dco_mid = (dco_min + dco_max) / 2;
> static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
> 18, 20, 24, 28, 30, 32, 36, 40,
> @@ -2211,7 +2211,7 @@ cnl_ddi_calculate_wrpll(int clock,
> 84, 88, 90, 92, 96, 98, 100, 102,
> 3, 5, 7, 9, 15, 21 };
> u32 dco, best_dco = 0, dco_centrality = 0;
> - u32 best_dco_centrality = 999999;
> + u32 best_dco_centrality = 999999000;
UINT_MAX, -1, or ~0 maybe?
> int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
>
> for (d = 0; d < ARRAY_SIZE(dividers); d++) {
> --
> 2.13.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 4/7] drm/i915/cnl: Fix wrpll math for higher freqs.
2017-11-14 20:00 ` Ville Syrjälä
@ 2017-11-14 20:09 ` Rodrigo Vivi
2017-11-14 20:26 ` Ville Syrjälä
2017-11-14 23:42 ` [PATCH] " Rodrigo Vivi
1 sibling, 1 reply; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-14 20:09 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Nov 14, 2017 at 08:00:31PM +0000, Ville Syrjälä wrote:
> On Tue, Nov 14, 2017 at 11:47:56AM -0800, Rodrigo Vivi wrote:
> > Spec describe all values in MHz. We handle our
> > clocks in KHz. This includes the best_dco_centrality that was
> > forgot in the same unity as spec. Consequently we couldn't
> > get a good divider for high frequenies. Hence HDMI 2.0 wasn't
> > working.
> >
> > This patch also replaces the use of "* KHz(1)" with the values
> > directly on KHz to avoid future confusion.
> >
> > Cc: Shashank Sharma <shashank.sharma@intel.com>
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index fba969cbda37..53f650f56148 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -2201,8 +2201,8 @@ cnl_ddi_calculate_wrpll(int clock,
> > struct skl_wrpll_params *wrpll_params)
> > {
> > u32 afe_clock = clock * 5;
> > - u32 dco_min = 7998 * KHz(1);
> > - u32 dco_max = 10000 * KHz(1);
> > + u32 dco_min = 7998000;
> > + u32 dco_max = 10000000;
> > u32 dco_mid = (dco_min + dco_max) / 2;
> > static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
> > 18, 20, 24, 28, 30, 32, 36, 40,
> > @@ -2211,7 +2211,7 @@ cnl_ddi_calculate_wrpll(int clock,
> > 84, 88, 90, 92, 96, 98, 100, 102,
> > 3, 5, 7, 9, 15, 21 };
> > u32 dco, best_dco = 0, dco_centrality = 0;
> > - u32 best_dco_centrality = 999999;
> > + u32 best_dco_centrality = 999999000;
>
> UINT_MAX, -1, or ~0 maybe?
yeap, I considered the max macros, but I didn't want to deviate
from spec...
>
> > int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
> >
> > for (d = 0; d < ARRAY_SIZE(dividers); d++) {
> > --
> > 2.13.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 4/7] drm/i915/cnl: Fix wrpll math for higher freqs.
2017-11-14 20:09 ` Rodrigo Vivi
@ 2017-11-14 20:26 ` Ville Syrjälä
0 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjälä @ 2017-11-14 20:26 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Nov 14, 2017 at 12:09:39PM -0800, Rodrigo Vivi wrote:
> On Tue, Nov 14, 2017 at 08:00:31PM +0000, Ville Syrjälä wrote:
> > On Tue, Nov 14, 2017 at 11:47:56AM -0800, Rodrigo Vivi wrote:
> > > Spec describe all values in MHz. We handle our
> > > clocks in KHz. This includes the best_dco_centrality that was
> > > forgot in the same unity as spec. Consequently we couldn't
> > > get a good divider for high frequenies. Hence HDMI 2.0 wasn't
> > > working.
> > >
> > > This patch also replaces the use of "* KHz(1)" with the values
> > > directly on KHz to avoid future confusion.
> > >
> > > Cc: Shashank Sharma <shashank.sharma@intel.com>
> > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > > Cc: James Ausmus <james.ausmus@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
> > > 1 file changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > index fba969cbda37..53f650f56148 100644
> > > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > @@ -2201,8 +2201,8 @@ cnl_ddi_calculate_wrpll(int clock,
> > > struct skl_wrpll_params *wrpll_params)
> > > {
> > > u32 afe_clock = clock * 5;
> > > - u32 dco_min = 7998 * KHz(1);
> > > - u32 dco_max = 10000 * KHz(1);
> > > + u32 dco_min = 7998000;
> > > + u32 dco_max = 10000000;
> > > u32 dco_mid = (dco_min + dco_max) / 2;
> > > static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
> > > 18, 20, 24, 28, 30, 32, 36, 40,
> > > @@ -2211,7 +2211,7 @@ cnl_ddi_calculate_wrpll(int clock,
> > > 84, 88, 90, 92, 96, 98, 100, 102,
> > > 3, 5, 7, 9, 15, 21 };
> > > u32 dco, best_dco = 0, dco_centrality = 0;
> > > - u32 best_dco_centrality = 999999;
> > > + u32 best_dco_centrality = 999999000;
> >
> > UINT_MAX, -1, or ~0 maybe?
>
> yeap, I considered the max macros, but I didn't want to deviate
> from spec...
Always bothers me to see some kind of 999... decimal max value pulled
out from someone's hat when they obvious thing clearly is just "max
representable value". Feels like someone wasn't thinking 100% when
they wrote the spec :)
Maybe just extend the 9's all the way to the end then? Dunno. I think
I'll just move on from the DDI DPLL code (that apporach has worked
pretty well thus far ;)
>
> >
> > > int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
> > >
> > > for (d = 0; d < ARRAY_SIZE(dividers); d++) {
> > > --
> > > 2.13.6
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel OTC
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH] drm/i915/cnl: Fix wrpll math for higher freqs.
2017-11-14 20:00 ` Ville Syrjälä
2017-11-14 20:09 ` Rodrigo Vivi
@ 2017-11-14 23:42 ` Rodrigo Vivi
2017-11-16 12:47 ` Ville Syrjälä
1 sibling, 1 reply; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-14 23:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Spec describe all values in MHz. We handle our
clocks in KHz. This includes the best_dco_centrality that was
forgot in the same unity as spec. Consequently we couldn't
get a good divider for high frequenies. Hence HDMI 2.0 wasn't
working.
Spec tells 999999 for initial best_dco_centrality meaning the
max value in MHz.
Since we convert dco from MHz to KHz we also need to convert
this initial best_doc_centrality to 999999000 or 999999999
or even better, to the max that its variable allow.
This patch also replaces the use of "* KHz(1)" with the values
directly on KHz to avoid future confusion.
v2: Use U32_MAX instead of random 99999 as spec tells. (Ville).
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index fba969cbda37..6cc12abdd39e 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2201,8 +2201,8 @@ cnl_ddi_calculate_wrpll(int clock,
struct skl_wrpll_params *wrpll_params)
{
u32 afe_clock = clock * 5;
- u32 dco_min = 7998 * KHz(1);
- u32 dco_max = 10000 * KHz(1);
+ u32 dco_min = 7998000;
+ u32 dco_max = 10000000;
u32 dco_mid = (dco_min + dco_max) / 2;
static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
18, 20, 24, 28, 30, 32, 36, 40,
@@ -2211,7 +2211,7 @@ cnl_ddi_calculate_wrpll(int clock,
84, 88, 90, 92, 96, 98, 100, 102,
3, 5, 7, 9, 15, 21 };
u32 dco, best_dco = 0, dco_centrality = 0;
- u32 best_dco_centrality = 999999;
+ u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
for (d = 0; d < ARRAY_SIZE(dividers); d++) {
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH] drm/i915/cnl: Fix wrpll math for higher freqs.
2017-11-14 23:42 ` [PATCH] " Rodrigo Vivi
@ 2017-11-16 12:47 ` Ville Syrjälä
0 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjälä @ 2017-11-16 12:47 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Nov 14, 2017 at 03:42:23PM -0800, Rodrigo Vivi wrote:
> Spec describe all values in MHz. We handle our
> clocks in KHz. This includes the best_dco_centrality that was
> forgot in the same unity as spec. Consequently we couldn't
> get a good divider for high frequenies. Hence HDMI 2.0 wasn't
> working.
>
> Spec tells 999999 for initial best_dco_centrality meaning the
> max value in MHz.
> Since we convert dco from MHz to KHz we also need to convert
> this initial best_doc_centrality to 999999000 or 999999999
> or even better, to the max that its variable allow.
>
> This patch also replaces the use of "* KHz(1)" with the values
> directly on KHz to avoid future confusion.
>
> v2: Use U32_MAX instead of random 99999 as spec tells. (Ville).
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index fba969cbda37..6cc12abdd39e 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2201,8 +2201,8 @@ cnl_ddi_calculate_wrpll(int clock,
> struct skl_wrpll_params *wrpll_params)
> {
> u32 afe_clock = clock * 5;
> - u32 dco_min = 7998 * KHz(1);
> - u32 dco_max = 10000 * KHz(1);
> + u32 dco_min = 7998000;
> + u32 dco_max = 10000000;
> u32 dco_mid = (dco_min + dco_max) / 2;
> static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
> 18, 20, 24, 28, 30, 32, 36, 40,
> @@ -2211,7 +2211,7 @@ cnl_ddi_calculate_wrpll(int clock,
> 84, 88, 90, 92, 96, 98, 100, 102,
> 3, 5, 7, 9, 15, 21 };
> u32 dco, best_dco = 0, dco_centrality = 0;
> - u32 best_dco_centrality = 999999;
> + u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
> int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
>
> for (d = 0; d < ARRAY_SIZE(dividers); d++) {
> --
> 2.13.6
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 4/7] drm/i915/cnl: Fix wrpll math for higher freqs.
2017-11-14 19:47 ` [PATCH 4/7] drm/i915/cnl: Fix wrpll math for higher freqs Rodrigo Vivi
2017-11-14 20:00 ` Ville Syrjälä
@ 2017-11-15 8:06 ` Mika Kahola
2017-11-15 18:04 ` Rodrigo Vivi
1 sibling, 1 reply; 43+ messages in thread
From: Mika Kahola @ 2017-11-15 8:06 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx
On Tue, 2017-11-14 at 11:47 -0800, Rodrigo Vivi wrote:
> Spec describe all values in MHz. We handle our
> clocks in KHz. This includes the best_dco_centrality that was
> forgot in the same unity as spec. Consequently we couldn't
> get a good divider for high frequenies. Hence HDMI 2.0 wasn't
> working.
>
> This patch also replaces the use of "* KHz(1)" with the values
> directly on KHz to avoid future confusion.
>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index fba969cbda37..53f650f56148 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2201,8 +2201,8 @@ cnl_ddi_calculate_wrpll(int clock,
> struct skl_wrpll_params *wrpll_params)
> {
> u32 afe_clock = clock * 5;
> - u32 dco_min = 7998 * KHz(1);
> - u32 dco_max = 10000 * KHz(1);
> + u32 dco_min = 7998000;
> + u32 dco_max = 10000000;
> u32 dco_mid = (dco_min + dco_max) / 2;
> static const int dividers[] = { 2, 4, 6, 8, 10,
> 12, 14, 16,
> 18, 20, 24, 28, 30,
> 32, 36, 40,
> @@ -2211,7 +2211,7 @@ cnl_ddi_calculate_wrpll(int clock,
> 84, 88, 90, 92, 96, 98,
> 100, 102,
> 3, 5, 7, 9, 15, 21 };
> u32 dco, best_dco = 0, dco_centrality = 0;
> - u32 best_dco_centrality = 999999;
> + u32 best_dco_centrality = 999999000;
> int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
>
> for (d = 0; d < ARRAY_SIZE(dividers); d++) {
--
Mika Kahola - Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 4/7] drm/i915/cnl: Fix wrpll math for higher freqs.
2017-11-15 8:06 ` [PATCH 4/7] " Mika Kahola
@ 2017-11-15 18:04 ` Rodrigo Vivi
2017-11-16 10:52 ` Mika Kahola
0 siblings, 1 reply; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-15 18:04 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
On Wed, Nov 15, 2017 at 08:06:16AM +0000, Mika Kahola wrote:
> On Tue, 2017-11-14 at 11:47 -0800, Rodrigo Vivi wrote:
> > Spec describe all values in MHz. We handle our
> > clocks in KHz. This includes the best_dco_centrality that was
> > forgot in the same unity as spec. Consequently we couldn't
> > get a good divider for high frequenies. Hence HDMI 2.0 wasn't
> > working.
> >
> > This patch also replaces the use of "* KHz(1)" with the values
> > directly on KHz to avoid future confusion.
> >
> > Cc: Shashank Sharma <shashank.sharma@intel.com>
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> Reviewed-by: Mika Kahola <mika.kahola@intel.com>
999999000 or U32_MAX?
>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index fba969cbda37..53f650f56148 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -2201,8 +2201,8 @@ cnl_ddi_calculate_wrpll(int clock,
> > struct skl_wrpll_params *wrpll_params)
> > {
> > u32 afe_clock = clock * 5;
> > - u32 dco_min = 7998 * KHz(1);
> > - u32 dco_max = 10000 * KHz(1);
> > + u32 dco_min = 7998000;
> > + u32 dco_max = 10000000;
> > u32 dco_mid = (dco_min + dco_max) / 2;
> > static const int dividers[] = { 2, 4, 6, 8, 10,
> > 12, 14, 16,
> > 18, 20, 24, 28, 30,
> > 32, 36, 40,
> > @@ -2211,7 +2211,7 @@ cnl_ddi_calculate_wrpll(int clock,
> > 84, 88, 90, 92, 96, 98,
> > 100, 102,
> > 3, 5, 7, 9, 15, 21 };
> > u32 dco, best_dco = 0, dco_centrality = 0;
> > - u32 best_dco_centrality = 999999;
> > + u32 best_dco_centrality = 999999000;
> > int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
> >
> > for (d = 0; d < ARRAY_SIZE(dividers); d++) {
> --
> Mika Kahola - Intel OTC
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 4/7] drm/i915/cnl: Fix wrpll math for higher freqs.
2017-11-15 18:04 ` Rodrigo Vivi
@ 2017-11-16 10:52 ` Mika Kahola
0 siblings, 0 replies; 43+ messages in thread
From: Mika Kahola @ 2017-11-16 10:52 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Wed, 2017-11-15 at 10:04 -0800, Rodrigo Vivi wrote:
> On Wed, Nov 15, 2017 at 08:06:16AM +0000, Mika Kahola wrote:
> >
> > On Tue, 2017-11-14 at 11:47 -0800, Rodrigo Vivi wrote:
> > >
> > > Spec describe all values in MHz. We handle our
> > > clocks in KHz. This includes the best_dco_centrality that was
> > > forgot in the same unity as spec. Consequently we couldn't
> > > get a good divider for high frequenies. Hence HDMI 2.0 wasn't
> > > working.
> > >
> > > This patch also replaces the use of "* KHz(1)" with the values
> > > directly on KHz to avoid future confusion.
> > >
> > > Cc: Shashank Sharma <shashank.sharma@intel.com>
> > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > > Cc: James Ausmus <james.ausmus@intel.com>
> > Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> 999999000 or U32_MAX?
The BSpec seems to favor 999999000 so I would follow the spec here.
>
> >
> >
> > >
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
> > > 1 file changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > index fba969cbda37..53f650f56148 100644
> > > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > @@ -2201,8 +2201,8 @@ cnl_ddi_calculate_wrpll(int clock,
> > > struct skl_wrpll_params *wrpll_params)
> > > {
> > > u32 afe_clock = clock * 5;
> > > - u32 dco_min = 7998 * KHz(1);
> > > - u32 dco_max = 10000 * KHz(1);
> > > + u32 dco_min = 7998000;
> > > + u32 dco_max = 10000000;
> > > u32 dco_mid = (dco_min + dco_max) / 2;
> > > static const int dividers[] = { 2, 4, 6, 8, 10,
> > > 12, 14, 16,
> > > 18, 20, 24, 28, 30,
> > > 32, 36, 40,
> > > @@ -2211,7 +2211,7 @@ cnl_ddi_calculate_wrpll(int clock,
> > > 84, 88, 90, 92, 96, 98,
> > > 100, 102,
> > > 3, 5, 7, 9, 15, 21
> > > };
> > > u32 dco, best_dco = 0, dco_centrality = 0;
> > > - u32 best_dco_centrality = 999999;
> > > + u32 best_dco_centrality = 999999000;
> > > int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
> > >
> > > for (d = 0; d < ARRAY_SIZE(dividers); d++) {
--
Mika Kahola - Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 5/7] drm/i915/cnl: Don't blindly replace qdiv.
2017-11-14 19:47 [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
` (3 preceding siblings ...)
2017-11-14 19:47 ` [PATCH 4/7] drm/i915/cnl: Fix wrpll math for higher freqs Rodrigo Vivi
@ 2017-11-14 19:47 ` Rodrigo Vivi
2017-11-14 23:34 ` Manasi Navare
2017-11-14 19:47 ` [PATCH 6/7] drm/i915/cnl: Write dco_fraction calculation as spec Rodrigo Vivi
` (8 subsequent siblings)
13 siblings, 1 reply; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-14 19:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Accordingly to spec "If Kdiv != 2, then Qdiv must be 1."
but we already handle qdiv values properly and this case here
should be spurious. But instead of blindly replacing let's
warn loudly instead. Because it means something was really
wrong on initial setup.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 53f650f56148..bd608f7f2399 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2184,8 +2184,7 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
WARN(1, "Incorrect PDiv\n");
}
- if (kdiv != 2)
- qdiv = 1;
+ WARN_ON(kdiv != 2 && qdiv != 1);
params->qdiv_ratio = qdiv;
params->qdiv_mode = (qdiv == 1) ? 0 : 1;
--
2.13.6
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 5/7] drm/i915/cnl: Don't blindly replace qdiv.
2017-11-14 19:47 ` [PATCH 5/7] drm/i915/cnl: Don't blindly replace qdiv Rodrigo Vivi
@ 2017-11-14 23:34 ` Manasi Navare
0 siblings, 0 replies; 43+ messages in thread
From: Manasi Navare @ 2017-11-14 23:34 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Nov 14, 2017 at 11:47:57AM -0800, Rodrigo Vivi wrote:
> Accordingly to spec "If Kdiv != 2, then Qdiv must be 1."
> but we already handle qdiv values properly and this case here
> should be spurious. But instead of blindly replacing let's
> warn loudly instead. Because it means something was really
> wrong on initial setup.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 53f650f56148..bd608f7f2399 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2184,8 +2184,7 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
> WARN(1, "Incorrect PDiv\n");
> }
>
> - if (kdiv != 2)
> - qdiv = 1;
> + WARN_ON(kdiv != 2 && qdiv != 1);
>
> params->qdiv_ratio = qdiv;
> params->qdiv_mode = (qdiv == 1) ? 0 : 1;
> --
> 2.13.6
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 6/7] drm/i915/cnl: Write dco_fraction calculation as spec.
2017-11-14 19:47 [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
` (4 preceding siblings ...)
2017-11-14 19:47 ` [PATCH 5/7] drm/i915/cnl: Don't blindly replace qdiv Rodrigo Vivi
@ 2017-11-14 19:47 ` Rodrigo Vivi
2017-11-14 20:22 ` Ville Syrjälä
2017-11-14 19:47 ` [PATCH 7/7] drm/i915/cnl: Extend HDMI 2.0 support to CNL Rodrigo Vivi
` (7 subsequent siblings)
13 siblings, 1 reply; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-14 19:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
I confess I never fully understood that previous calculation,
so maybe this is cannot be called a "fix". But let's follow
the math that is written on Spec so we have get more confident
this is what hardware expect.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index bd608f7f2399..ee690d2f6e54 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2190,8 +2190,8 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
params->qdiv_mode = (qdiv == 1) ? 0 : 1;
params->dco_integer = div_u64(dco_freq, ref_freq);
- params->dco_fraction = div_u64((div_u64((uint64_t)dco_freq<<15, (uint64_t)ref_freq) -
- ((uint64_t)params->dco_integer<<15)) * 0x8000, 0x8000);
+ params->dco_fraction = (DIV_ROUND_UP_ULL(dco_freq, ref_freq) -
+ params->dco_integer) * (1 << 15);
}
static bool
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 6/7] drm/i915/cnl: Write dco_fraction calculation as spec.
2017-11-14 19:47 ` [PATCH 6/7] drm/i915/cnl: Write dco_fraction calculation as spec Rodrigo Vivi
@ 2017-11-14 20:22 ` Ville Syrjälä
2017-11-14 20:43 ` Rodrigo Vivi
2017-11-14 20:46 ` Ville Syrjälä
0 siblings, 2 replies; 43+ messages in thread
From: Ville Syrjälä @ 2017-11-14 20:22 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Nov 14, 2017 at 11:47:58AM -0800, Rodrigo Vivi wrote:
> I confess I never fully understood that previous calculation,
> so maybe this is cannot be called a "fix". But let's follow
> the math that is written on Spec so we have get more confident
> this is what hardware expect.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index bd608f7f2399..ee690d2f6e54 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2190,8 +2190,8 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
> params->qdiv_mode = (qdiv == 1) ? 0 : 1;
>
> params->dco_integer = div_u64(dco_freq, ref_freq);
> - params->dco_fraction = div_u64((div_u64((uint64_t)dco_freq<<15, (uint64_t)ref_freq) -
> - ((uint64_t)params->dco_integer<<15)) * 0x8000, 0x8000);
> + params->dco_fraction = (DIV_ROUND_UP_ULL(dco_freq, ref_freq) -
> + params->dco_integer) * (1 << 15);
Is dco_freq in khz here? Or hz?
If khz, the following should work... I think:
unsigned int dco = div_u64((u64)dco_freq << 15, ref_freq * 1000);
dco_int = dco >> 15;
dco_frac = dco & 0x7fff;
> }
>
> static bool
> --
> 2.13.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 6/7] drm/i915/cnl: Write dco_fraction calculation as spec.
2017-11-14 20:22 ` Ville Syrjälä
@ 2017-11-14 20:43 ` Rodrigo Vivi
2017-11-14 20:46 ` Ville Syrjälä
1 sibling, 0 replies; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-14 20:43 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Nov 14, 2017 at 08:22:27PM +0000, Ville Syrjälä wrote:
> On Tue, Nov 14, 2017 at 11:47:58AM -0800, Rodrigo Vivi wrote:
> > I confess I never fully understood that previous calculation,
> > so maybe this is cannot be called a "fix". But let's follow
> > the math that is written on Spec so we have get more confident
> > this is what hardware expect.
> >
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index bd608f7f2399..ee690d2f6e54 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -2190,8 +2190,8 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
> > params->qdiv_mode = (qdiv == 1) ? 0 : 1;
> >
> > params->dco_integer = div_u64(dco_freq, ref_freq);
> > - params->dco_fraction = div_u64((div_u64((uint64_t)dco_freq<<15, (uint64_t)ref_freq) -
> > - ((uint64_t)params->dco_integer<<15)) * 0x8000, 0x8000);
> > + params->dco_fraction = (DIV_ROUND_UP_ULL(dco_freq, ref_freq) -
> > + params->dco_integer) * (1 << 15);
>
> Is dco_freq in khz here? Or hz?
>
> If khz, the following should work... I think:
khz
>
> unsigned int dco = div_u64((u64)dco_freq << 15, ref_freq * 1000);
why to convert ref_freq? isn't this in khz as well already?
> dco_int = dco >> 15;
> dco_frac = dco & 0x7fff;
wow! my first thought was that was more complicated, but eureka,
this should be the right way to go...
Clearly better than spec... like that maximum in the other patch ;)
>
> > }
> >
> > static bool
> > --
> > 2.13.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 6/7] drm/i915/cnl: Write dco_fraction calculation as spec.
2017-11-14 20:22 ` Ville Syrjälä
2017-11-14 20:43 ` Rodrigo Vivi
@ 2017-11-14 20:46 ` Ville Syrjälä
2017-11-14 21:29 ` Rodrigo Vivi
2017-11-14 23:51 ` [PATCH] drm/i915/cnl: Simplify dco_fraction calculation Rodrigo Vivi
1 sibling, 2 replies; 43+ messages in thread
From: Ville Syrjälä @ 2017-11-14 20:46 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Nov 14, 2017 at 10:22:27PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 14, 2017 at 11:47:58AM -0800, Rodrigo Vivi wrote:
> > I confess I never fully understood that previous calculation,
> > so maybe this is cannot be called a "fix". But let's follow
> > the math that is written on Spec so we have get more confident
> > this is what hardware expect.
> >
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index bd608f7f2399..ee690d2f6e54 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -2190,8 +2190,8 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
> > params->qdiv_mode = (qdiv == 1) ? 0 : 1;
> >
> > params->dco_integer = div_u64(dco_freq, ref_freq);
> > - params->dco_fraction = div_u64((div_u64((uint64_t)dco_freq<<15, (uint64_t)ref_freq) -
> > - ((uint64_t)params->dco_integer<<15)) * 0x8000, 0x8000);
> > + params->dco_fraction = (DIV_ROUND_UP_ULL(dco_freq, ref_freq) -
> > + params->dco_integer) * (1 << 15);
>
> Is dco_freq in khz here? Or hz?
>
> If khz, the following should work... I think:
>
> unsigned int dco = div_u64((u64)dco_freq << 15, ref_freq * 1000);
Actually w/o the *1000 I suppose, for khz.
> dco_int = dco >> 15;
> dco_frac = dco & 0x7fff;
>
> > }
> >
> > static bool
> > --
> > 2.13.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 6/7] drm/i915/cnl: Write dco_fraction calculation as spec.
2017-11-14 20:46 ` Ville Syrjälä
@ 2017-11-14 21:29 ` Rodrigo Vivi
2017-11-14 23:25 ` Rodrigo Vivi
2017-11-14 23:51 ` [PATCH] drm/i915/cnl: Simplify dco_fraction calculation Rodrigo Vivi
1 sibling, 1 reply; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-14 21:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Nov 14, 2017 at 08:46:38PM +0000, Ville Syrjälä wrote:
> On Tue, Nov 14, 2017 at 10:22:27PM +0200, Ville Syrjälä wrote:
> > On Tue, Nov 14, 2017 at 11:47:58AM -0800, Rodrigo Vivi wrote:
> > > I confess I never fully understood that previous calculation,
> > > so maybe this is cannot be called a "fix". But let's follow
> > > the math that is written on Spec so we have get more confident
> > > this is what hardware expect.
> > >
> > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > > Cc: James Ausmus <james.ausmus@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > index bd608f7f2399..ee690d2f6e54 100644
> > > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > @@ -2190,8 +2190,8 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
> > > params->qdiv_mode = (qdiv == 1) ? 0 : 1;
> > >
> > > params->dco_integer = div_u64(dco_freq, ref_freq);
> > > - params->dco_fraction = div_u64((div_u64((uint64_t)dco_freq<<15, (uint64_t)ref_freq) -
> > > - ((uint64_t)params->dco_integer<<15)) * 0x8000, 0x8000);
> > > + params->dco_fraction = (DIV_ROUND_UP_ULL(dco_freq, ref_freq) -
> > > + params->dco_integer) * (1 << 15);
> >
> > Is dco_freq in khz here? Or hz?
> >
> > If khz, the following should work... I think:
> >
> > unsigned int dco = div_u64((u64)dco_freq << 15, ref_freq * 1000);
>
> Actually w/o the *1000 I suppose, for khz.
On python it works apparently:
* (7998750 << 15)/24000
10920960 #"dco"
* ((7998750 << 15)/24000)>>15
333 #int
* ((7998750 << 15)/24000)&0x7ffff
435200 #frac
while on our code we get
dco = 4584
so int = 0
and frac = 4584...
div_u64 not working in float?
also this shows me that while this python gives us the frac 435200
my current code that follows spec gives frac 32768
and previous code was giving frac 9216
:/
more thoughts?
>
> > dco_int = dco >> 15;
> > dco_frac = dco & 0x7fff;
> >
> > > }
> > >
> > > static bool
> > > --
> > > 2.13.6
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel OTC
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 6/7] drm/i915/cnl: Write dco_fraction calculation as spec.
2017-11-14 21:29 ` Rodrigo Vivi
@ 2017-11-14 23:25 ` Rodrigo Vivi
0 siblings, 0 replies; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-14 23:25 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Nov 14, 2017 at 09:29:57PM +0000, Rodrigo Vivi wrote:
> On Tue, Nov 14, 2017 at 08:46:38PM +0000, Ville Syrjälä wrote:
> > On Tue, Nov 14, 2017 at 10:22:27PM +0200, Ville Syrjälä wrote:
> > > On Tue, Nov 14, 2017 at 11:47:58AM -0800, Rodrigo Vivi wrote:
> > > > I confess I never fully understood that previous calculation,
> > > > so maybe this is cannot be called a "fix". But let's follow
> > > > the math that is written on Spec so we have get more confident
> > > > this is what hardware expect.
> > > >
> > > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > > > Cc: James Ausmus <james.ausmus@intel.com>
> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 ++--
> > > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > > index bd608f7f2399..ee690d2f6e54 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > > @@ -2190,8 +2190,8 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
> > > > params->qdiv_mode = (qdiv == 1) ? 0 : 1;
> > > >
> > > > params->dco_integer = div_u64(dco_freq, ref_freq);
> > > > - params->dco_fraction = div_u64((div_u64((uint64_t)dco_freq<<15, (uint64_t)ref_freq) -
> > > > - ((uint64_t)params->dco_integer<<15)) * 0x8000, 0x8000);
> > > > + params->dco_fraction = (DIV_ROUND_UP_ULL(dco_freq, ref_freq) -
> > > > + params->dco_integer) * (1 << 15);
> > >
> > > Is dco_freq in khz here? Or hz?
> > >
> > > If khz, the following should work... I think:
> > >
>
> > > unsigned int dco = div_u64((u64)dco_freq << 15, ref_freq * 1000);
> >
> > Actually w/o the *1000 I suppose, for khz.
>
> On python it works apparently:
> * (7998750 << 15)/24000
> 10920960 #"dco"
> * ((7998750 << 15)/24000)>>15
> 333 #int
> * ((7998750 << 15)/24000)&0x7ffff
> 435200 #frac
>
> while on our code we get
> dco = 4584
> so int = 0
> and frac = 4584...
>
> div_u64 not working in float?
oh! u32 << 15 was the issue...
So, with this code:
u64 dco = dco_freq;
dco = div_u64(dco << 15, ref_freq);
params->dco_integer = dco >> 15;
params->dco_fraction = dco & 0x7fff;
we have int 333 as expected and frac 92116 as the orig code.
So it seems the orig code was better after all. Although I'd
still want to clean it up.
But what bothers me now is that python gives a different frac
and also calculator shows this division as 333.28125
nothing seems to make us to get this 28125...
:/
but now that I know how it is all my attempts here lead me to 92116
and it works...
Thanks,
Rodrigo.
>
> also this shows me that while this python gives us the frac 435200
> my current code that follows spec gives frac 32768
> and previous code was giving frac 9216
>
> :/
>
> more thoughts?
>
> >
> > > dco_int = dco >> 15;
> > > dco_frac = dco & 0x7fff;
> > >
> > > > }
> > > >
> > > > static bool
> > > > --
> > > > 2.13.6
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
> > > --
> > > Ville Syrjälä
> > > Intel OTC
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH] drm/i915/cnl: Simplify dco_fraction calculation.
2017-11-14 20:46 ` Ville Syrjälä
2017-11-14 21:29 ` Rodrigo Vivi
@ 2017-11-14 23:51 ` Rodrigo Vivi
2017-11-15 11:09 ` Ville Syrjälä
1 sibling, 1 reply; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-14 23:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
I confess I never fully understood that previous calculation,
so this is not a "fix". But let's simplify this math
so poor brains like mine can read and make some sense of
it in the future.
v2: Don't follow the spec since that gives invalid
values and it is also confusing. This Ville's
version is much simpler.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 361b7102b602..f9651accecc9 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2153,6 +2153,8 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
u32 dco_freq, u32 ref_freq,
int pdiv, int qdiv, int kdiv)
{
+ u64 dco;
+
switch (kdiv) {
case 1:
params->kdiv = 1;
@@ -2189,9 +2191,10 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
params->qdiv_ratio = qdiv;
params->qdiv_mode = (qdiv == 1) ? 0 : 1;
- params->dco_integer = div_u64(dco_freq, ref_freq);
- params->dco_fraction = div_u64((div_u64((uint64_t)dco_freq<<15, (uint64_t)ref_freq) -
- ((uint64_t)params->dco_integer<<15)) * 0x8000, 0x8000);
+ dco = dco_freq;
+ dco = div_u64(dco << 15, ref_freq);
+ params->dco_integer = dco >> 15;
+ params->dco_fraction = dco & 0x7fff;
}
static bool
--
2.13.6
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH] drm/i915/cnl: Simplify dco_fraction calculation.
2017-11-14 23:51 ` [PATCH] drm/i915/cnl: Simplify dco_fraction calculation Rodrigo Vivi
@ 2017-11-15 11:09 ` Ville Syrjälä
0 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjälä @ 2017-11-15 11:09 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Nov 14, 2017 at 03:51:26PM -0800, Rodrigo Vivi wrote:
> I confess I never fully understood that previous calculation,
> so this is not a "fix". But let's simplify this math
> so poor brains like mine can read and make some sense of
> it in the future.
>
> v2: Don't follow the spec since that gives invalid
> values and it is also confusing. This Ville's
> version is much simpler.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 361b7102b602..f9651accecc9 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2153,6 +2153,8 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
> u32 dco_freq, u32 ref_freq,
> int pdiv, int qdiv, int kdiv)
> {
> + u64 dco;
> +
> switch (kdiv) {
> case 1:
> params->kdiv = 1;
> @@ -2189,9 +2191,10 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
> params->qdiv_ratio = qdiv;
> params->qdiv_mode = (qdiv == 1) ? 0 : 1;
>
> - params->dco_integer = div_u64(dco_freq, ref_freq);
> - params->dco_fraction = div_u64((div_u64((uint64_t)dco_freq<<15, (uint64_t)ref_freq) -
> - ((uint64_t)params->dco_integer<<15)) * 0x8000, 0x8000);
> + dco = dco_freq;
> + dco = div_u64(dco << 15, ref_freq);
A bit wasteful putting the result into a u64. The cast I had in my
earlier proposal should do.
> + params->dco_integer = dco >> 15;
> + params->dco_fraction = dco & 0x7fff;
> }
>
> static bool
> --
> 2.13.6
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 7/7] drm/i915/cnl: Extend HDMI 2.0 support to CNL.
2017-11-14 19:47 [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
` (5 preceding siblings ...)
2017-11-14 19:47 ` [PATCH 6/7] drm/i915/cnl: Write dco_fraction calculation as spec Rodrigo Vivi
@ 2017-11-14 19:47 ` Rodrigo Vivi
[not found] ` <20171115111448.GZ10981@intel.com>
2017-11-14 20:47 ` ✗ Fi.CI.BAT: failure for WRPLL fixes for HDMI 2.0 on Cannonlake Patchwork
` (6 subsequent siblings)
13 siblings, 1 reply; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-14 19:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
Starting on GLK we support HDMI 2.0. So this patch only
extend the work Shashank has made to GLK to CNL.
v2: The version that compiles :/
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 2d95db64cdf2..96c314a6170a 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1235,7 +1235,7 @@ static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
&dev_priv->vbt.ddi_port_info[encoder->port];
int max_tmds_clock;
- if (IS_GEMINILAKE(dev_priv))
+ if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
max_tmds_clock = 594000;
else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
max_tmds_clock = 300000;
@@ -1511,7 +1511,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
pipe_config->lane_count = 4;
- if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) {
+ if (scdc->scrambling.supported && (IS_GEMINILAKE(dev_priv) ||
+ INTEL_GEN(dev_priv) >= 10)) {
if (scdc->scrambling.low_rates)
pipe_config->hdmi_scrambling = true;
@@ -2033,7 +2034,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
connector->doublescan_allowed = 0;
connector->stereo_allowed = 1;
- if (IS_GEMINILAKE(dev_priv))
+ if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
connector->ycbcr_420_allowed = true;
intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
--
2.13.6
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 43+ messages in thread* ✗ Fi.CI.BAT: failure for WRPLL fixes for HDMI 2.0 on Cannonlake.
2017-11-14 19:47 [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
` (6 preceding siblings ...)
2017-11-14 19:47 ` [PATCH 7/7] drm/i915/cnl: Extend HDMI 2.0 support to CNL Rodrigo Vivi
@ 2017-11-14 20:47 ` Patchwork
2017-11-15 0:05 ` ✓ Fi.CI.BAT: success for WRPLL fixes for HDMI 2.0 on Cannonlake. (rev2) Patchwork
` (5 subsequent siblings)
13 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2017-11-14 20:47 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: WRPLL fixes for HDMI 2.0 on Cannonlake.
URL : https://patchwork.freedesktop.org/series/33823/
State : failure
== Summary ==
Series 33823v1 WRPLL fixes for HDMI 2.0 on Cannonlake.
https://patchwork.freedesktop.org/api/1.0/series/33823/revisions/1/mbox/
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass -> FAIL (fi-blb-e6850)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> INCOMPLETE (fi-snb-2520m)
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:440s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:455s
fi-blb-e6850 total:289 pass:222 dwarn:1 dfail:0 fail:1 skip:65 time:377s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:544s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:276s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:502s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:506s
fi-byt-j1900 total:289 pass:254 dwarn:0 dfail:0 fail:0 skip:35 time:507s
fi-byt-n2820 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:497s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:432s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:263s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:544s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:430s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:435s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:425s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:485s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:463s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:485s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:529s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:471s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:529s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:568s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:452s
fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:541s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:566s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:517s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:494s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:459s
fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:425s
Blacklisted hosts:
fi-cfl-s total:289 pass:254 dwarn:3 dfail:0 fail:0 skip:32 time:522s
fi-cnl-y total:289 pass:261 dwarn:0 dfail:0 fail:1 skip:27 time:571s
fi-glk-dsi total:289 pass:257 dwarn:0 dfail:0 fail:2 skip:30 time:510s
c46476e24d6432b5792ef63596a985848d122d50 drm-tip: 2017y-11m-14d-17h-03m-32s UTC integration manifest
6dfe31a79aca drm/i915/cnl: Extend HDMI 2.0 support to CNL.
4f1e96fbf6cc drm/i915/cnl: Write dco_fraction calculation as spec.
67cfd7f598c5 drm/i915/cnl: Don't blindly replace qdiv.
5ebe12a24b29 drm/i915/cnl: Fix wrpll math for higher freqs.
303af54b1923 drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.
03436c82428a drm/i915/cnl: Remove useless conversion.
0e0c097b31c7 drm/i915/cnl: Remove spurious central_freq.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7129/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread* ✓ Fi.CI.BAT: success for WRPLL fixes for HDMI 2.0 on Cannonlake. (rev2)
2017-11-14 19:47 [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
` (7 preceding siblings ...)
2017-11-14 20:47 ` ✗ Fi.CI.BAT: failure for WRPLL fixes for HDMI 2.0 on Cannonlake Patchwork
@ 2017-11-15 0:05 ` Patchwork
2017-11-15 0:23 ` ✓ Fi.CI.BAT: success for WRPLL fixes for HDMI 2.0 on Cannonlake. (rev3) Patchwork
` (4 subsequent siblings)
13 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2017-11-15 0:05 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: WRPLL fixes for HDMI 2.0 on Cannonlake. (rev2)
URL : https://patchwork.freedesktop.org/series/33823/
State : success
== Summary ==
Series 33823v2 WRPLL fixes for HDMI 2.0 on Cannonlake.
https://patchwork.freedesktop.org/api/1.0/series/33823/revisions/2/mbox/
Test chamelium:
Subgroup dp-crc-fast:
fail -> PASS (fi-kbl-7500u) fdo#102514
Test kms_busy:
Subgroup basic-flip-a:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-b:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-c:
skip -> PASS (fi-hsw-4770r)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-busy-flip-before-cursor-legacy:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-after-cursor-atomic:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-after-cursor-legacy:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-after-cursor-varying-size:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-before-cursor-atomic:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-before-cursor-legacy:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-before-cursor-varying-size:
skip -> PASS (fi-hsw-4770r)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-vs-modeset:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-vs-wf_vblank:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-plain-flip:
skip -> PASS (fi-hsw-4770r)
Test kms_frontbuffer_tracking:
Subgroup basic:
skip -> PASS (fi-hsw-4770r)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
skip -> PASS (fi-hsw-4770r)
Subgroup hang-read-crc-pipe-b:
skip -> PASS (fi-hsw-4770r)
Subgroup hang-read-crc-pipe-c:
skip -> PASS (fi-hsw-4770r)
Subgroup nonblocking-crc-pipe-a:
skip -> PASS (fi-hsw-4770r)
Subgroup nonblocking-crc-pipe-a-frame-sequence:
skip -> PASS (fi-hsw-4770r)
Subgroup nonblocking-crc-pipe-b:
skip -> PASS (fi-hsw-4770r)
Subgroup nonblocking-crc-pipe-b-frame-sequence:
skip -> PASS (fi-hsw-4770r)
Subgroup nonblocking-crc-pipe-c:
skip -> PASS (fi-hsw-4770r)
Subgroup nonblocking-crc-pipe-c-frame-sequence:
skip -> PASS (fi-hsw-4770r)
Subgroup read-crc-pipe-a:
skip -> PASS (fi-hsw-4770r)
Subgroup read-crc-pipe-a-frame-sequence:
skip -> PASS (fi-hsw-4770r)
Subgroup read-crc-pipe-b:
skip -> PASS (fi-hsw-4770r)
Subgroup read-crc-pipe-b-frame-sequence:
skip -> PASS (fi-hsw-4770r) fdo#102332
Subgroup read-crc-pipe-c:
skip -> PASS (fi-hsw-4770r)
Subgroup read-crc-pipe-c-frame-sequence:
skip -> PASS (fi-hsw-4770r)
Subgroup suspend-read-crc-pipe-a:
skip -> PASS (fi-hsw-4770r)
Subgroup suspend-read-crc-pipe-b:
skip -> PASS (fi-hsw-4770r)
Subgroup suspend-read-crc-pipe-c:
skip -> PASS (fi-hsw-4770r)
Test pm_rpm:
Subgroup basic-pci-d3-state:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-rte:
skip -> PASS (fi-hsw-4770r)
Test prime_vgem:
Subgroup basic-fence-flip:
skip -> PASS (fi-hsw-4770r)
fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#102332 https://bugs.freedesktop.org/show_bug.cgi?id=102332
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:444s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:462s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:379s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:542s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:275s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:505s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:509s
fi-byt-j1900 total:289 pass:254 dwarn:0 dfail:0 fail:0 skip:35 time:498s
fi-byt-n2820 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:495s
WARNING: Long output truncated
5f7fd97a513ac1f0b84c61fae3fc83d4432e602c drm-tip: 2017y-11m-14d-21h-04m-27s UTC integration manifest
94f2ba88d3fc drm/i915/cnl: Extend HDMI 2.0 support to CNL.
e1ed8641aef8 drm/i915/cnl: Write dco_fraction calculation as spec.
85c74e286241 drm/i915/cnl: Don't blindly replace qdiv.
3a2b63d54558 drm/i915/cnl: Fix wrpll math for higher freqs.
e45282f23fc4 drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.
a66dcfc4e889 drm/i915/cnl: Remove useless conversion.
8e5c84fc60c1 drm/i915/cnl: Remove spurious central_freq.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7134/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread* ✓ Fi.CI.BAT: success for WRPLL fixes for HDMI 2.0 on Cannonlake. (rev3)
2017-11-14 19:47 [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
` (8 preceding siblings ...)
2017-11-15 0:05 ` ✓ Fi.CI.BAT: success for WRPLL fixes for HDMI 2.0 on Cannonlake. (rev2) Patchwork
@ 2017-11-15 0:23 ` Patchwork
2017-11-15 3:27 ` ✗ Fi.CI.IGT: warning " Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2017-11-15 0:23 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: WRPLL fixes for HDMI 2.0 on Cannonlake. (rev3)
URL : https://patchwork.freedesktop.org/series/33823/
State : success
== Summary ==
Series 33823v3 WRPLL fixes for HDMI 2.0 on Cannonlake.
https://patchwork.freedesktop.org/api/1.0/series/33823/revisions/3/mbox/
Test chamelium:
Subgroup dp-crc-fast:
fail -> PASS (fi-kbl-7500u) fdo#102514
Test kms_busy:
Subgroup basic-flip-a:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-b:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-c:
skip -> PASS (fi-hsw-4770r)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-busy-flip-before-cursor-legacy:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-after-cursor-atomic:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-after-cursor-legacy:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-after-cursor-varying-size:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-before-cursor-atomic:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-before-cursor-legacy:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-before-cursor-varying-size:
skip -> PASS (fi-hsw-4770r)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-vs-modeset:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-flip-vs-wf_vblank:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-plain-flip:
skip -> PASS (fi-hsw-4770r)
Test kms_frontbuffer_tracking:
Subgroup basic:
skip -> PASS (fi-hsw-4770r)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
skip -> PASS (fi-hsw-4770r)
Subgroup hang-read-crc-pipe-b:
skip -> PASS (fi-hsw-4770r)
Subgroup hang-read-crc-pipe-c:
skip -> PASS (fi-hsw-4770r)
Subgroup nonblocking-crc-pipe-a:
skip -> PASS (fi-hsw-4770r)
Subgroup nonblocking-crc-pipe-a-frame-sequence:
skip -> PASS (fi-hsw-4770r)
Subgroup nonblocking-crc-pipe-b:
skip -> PASS (fi-hsw-4770r)
Subgroup nonblocking-crc-pipe-b-frame-sequence:
skip -> PASS (fi-hsw-4770r)
Subgroup nonblocking-crc-pipe-c:
skip -> PASS (fi-hsw-4770r)
Subgroup nonblocking-crc-pipe-c-frame-sequence:
skip -> PASS (fi-hsw-4770r)
Subgroup read-crc-pipe-a:
skip -> PASS (fi-hsw-4770r)
Subgroup read-crc-pipe-a-frame-sequence:
skip -> PASS (fi-hsw-4770r)
Subgroup read-crc-pipe-b:
skip -> PASS (fi-hsw-4770r)
Subgroup read-crc-pipe-b-frame-sequence:
skip -> PASS (fi-hsw-4770r) fdo#102332
Subgroup read-crc-pipe-c:
skip -> PASS (fi-hsw-4770r)
Subgroup read-crc-pipe-c-frame-sequence:
skip -> PASS (fi-hsw-4770r)
Subgroup suspend-read-crc-pipe-a:
skip -> PASS (fi-hsw-4770r)
Subgroup suspend-read-crc-pipe-b:
skip -> PASS (fi-hsw-4770r)
Subgroup suspend-read-crc-pipe-c:
skip -> PASS (fi-hsw-4770r)
Test pm_rpm:
Subgroup basic-pci-d3-state:
skip -> PASS (fi-hsw-4770r)
Subgroup basic-rte:
skip -> PASS (fi-hsw-4770r)
Test prime_vgem:
Subgroup basic-fence-flip:
skip -> PASS (fi-hsw-4770r)
fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#102332 https://bugs.freedesktop.org/show_bug.cgi?id=102332
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:438s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:453s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:381s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:540s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:274s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:502s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:504s
fi-byt-j1900 total:289 pass:254 dwarn:0 dfail:0 fail:0 skip:35 time:494s
fi-byt-n2820 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:492s
WARNING: Long output truncated
5f7fd97a513ac1f0b84c61fae3fc83d4432e602c drm-tip: 2017y-11m-14d-21h-04m-27s UTC integration manifest
71d63dabce03 drm/i915/cnl: Extend HDMI 2.0 support to CNL.
e92fc1d84a33 drm/i915/cnl: Simplify dco_fraction calculation.
273b1c316fd3 drm/i915/cnl: Don't blindly replace qdiv.
19da69173ecc drm/i915/cnl: Fix wrpll math for higher freqs.
7df18769b1e0 drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.
a8bd63dc30f1 drm/i915/cnl: Remove useless conversion.
87b2a9f0a43b drm/i915/cnl: Remove spurious central_freq.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7135/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread* ✗ Fi.CI.IGT: warning for WRPLL fixes for HDMI 2.0 on Cannonlake. (rev3)
2017-11-14 19:47 [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
` (9 preceding siblings ...)
2017-11-15 0:23 ` ✓ Fi.CI.BAT: success for WRPLL fixes for HDMI 2.0 on Cannonlake. (rev3) Patchwork
@ 2017-11-15 3:27 ` Patchwork
2017-11-16 17:02 ` ✓ Fi.CI.BAT: success for WRPLL fixes for HDMI 2.0 on Cannonlake. (rev4) Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2017-11-15 3:27 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: WRPLL fixes for HDMI 2.0 on Cannonlake. (rev3)
URL : https://patchwork.freedesktop.org/series/33823/
State : warning
== Summary ==
Test kms_cursor_legacy:
Subgroup cursora-vs-flipa-legacy:
pass -> SKIP (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
pass -> SKIP (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
Test drv_module_reload:
Subgroup basic-reload-inject:
dmesg-warn -> PASS (shard-hsw) fdo#102707
Test kms_flip:
Subgroup vblank-vs-dpms-suspend:
skip -> PASS (shard-hsw)
Test kms_draw_crc:
Subgroup draw-method-xrgb2101010-mmap-gtt-untiled:
skip -> PASS (shard-hsw)
Subgroup draw-method-rgb565-blt-xtiled:
skip -> PASS (shard-hsw)
Test kms_cursor_crc:
Subgroup cursor-128x42-random:
skip -> PASS (shard-hsw)
Test kms_busy:
Subgroup extended-modeset-hang-newfb-with-reset-render-a:
pass -> DMESG-WARN (shard-hsw) fdo#102249
Test kms_universal_plane:
Subgroup universal-plane-pipe-a-sanity:
skip -> PASS (shard-hsw)
Test kms_chv_cursor_fail:
Subgroup pipe-c-128x128-left-edge:
skip -> PASS (shard-hsw)
Test perf:
Subgroup oa-exponents:
fail -> PASS (shard-hsw) fdo#102254
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
shard-hsw total:2584 pass:1469 dwarn:3 dfail:1 fail:10 skip:1101 time:9445s
Blacklisted hosts:
shard-apl total:2584 pass:1619 dwarn:3 dfail:1 fail:24 skip:936 time:13075s
shard-kbl total:2565 pass:1703 dwarn:7 dfail:0 fail:25 skip:829 time:10603s
shard-snb total:2567 pass:1184 dwarn:1 dfail:0 fail:12 skip:1369 time:7569s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7135/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread* ✓ Fi.CI.BAT: success for WRPLL fixes for HDMI 2.0 on Cannonlake. (rev4)
2017-11-14 19:47 [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
` (10 preceding siblings ...)
2017-11-15 3:27 ` ✗ Fi.CI.IGT: warning " Patchwork
@ 2017-11-16 17:02 ` Patchwork
2017-11-16 17:51 ` ✓ Fi.CI.IGT: " Patchwork
2017-11-16 17:53 ` [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
13 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2017-11-16 17:02 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: WRPLL fixes for HDMI 2.0 on Cannonlake. (rev4)
URL : https://patchwork.freedesktop.org/series/33823/
State : success
== Summary ==
Series 33823v4 WRPLL fixes for HDMI 2.0 on Cannonlake.
https://patchwork.freedesktop.org/api/1.0/series/33823/revisions/4/mbox/
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:448s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:383s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:535s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:277s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:512s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:511s
fi-byt-j1900 total:289 pass:254 dwarn:0 dfail:0 fail:0 skip:35 time:500s
fi-byt-n2820 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:496s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:433s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:266s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:543s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:429s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:436s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:427s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:473s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:466s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:487s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:532s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:476s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:533s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:577s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:461s
fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:543s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:569s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:512s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:495s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:465s
fi-snb-2520m total:246 pass:212 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:423s
Blacklisted hosts:
fi-cnl-y total:216 pass:195 dwarn:0 dfail:0 fail:0 skip:20
1fc4fe8ac97eee86a4fe2dc1239a350aa3f13371 drm-tip: 2017y-11m-16d-12h-57m-10s UTC integration manifest
7484ce150d2c drm/i915/cnl: Extend HDMI 2.0 support to CNL.
c8b6992b7f7c drm/i915/cnl: Simplify dco_fraction calculation.
7ee6c6f3682a drm/i915/cnl: Don't blindly replace qdiv.
7591bc02cd94 drm/i915/cnl: Fix wrpll math for higher freqs.
890b9013c560 drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.
fb457f5b2b19 drm/i915/cnl: Remove useless conversion.
874fa2bcab3b drm/i915/cnl: Remove spurious central_freq.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7160/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread* ✓ Fi.CI.IGT: success for WRPLL fixes for HDMI 2.0 on Cannonlake. (rev4)
2017-11-14 19:47 [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
` (11 preceding siblings ...)
2017-11-16 17:02 ` ✓ Fi.CI.BAT: success for WRPLL fixes for HDMI 2.0 on Cannonlake. (rev4) Patchwork
@ 2017-11-16 17:51 ` Patchwork
2017-11-16 17:53 ` [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
13 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2017-11-16 17:51 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: WRPLL fixes for HDMI 2.0 on Cannonlake. (rev4)
URL : https://patchwork.freedesktop.org/series/33823/
State : success
== Summary ==
Test drv_selftest:
Subgroup mock_sanitycheck:
pass -> DMESG-WARN (shard-snb) fdo#103717
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail -> PASS (shard-snb) fdo#101623 +1
Test kms_flip:
Subgroup vblank-vs-suspend-interruptible:
pass -> DMESG-WARN (shard-snb) fdo#100368
fdo#103717 https://bugs.freedesktop.org/show_bug.cgi?id=103717
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
shard-hsw total:2584 pass:1473 dwarn:1 dfail:1 fail:10 skip:1099 time:9532s
shard-snb total:2584 pass:1258 dwarn:3 dfail:1 fail:11 skip:1311 time:8012s
Blacklisted hosts:
shard-apl total:2565 pass:1598 dwarn:2 dfail:1 fail:26 skip:937 time:12996s
shard-kbl total:2526 pass:1673 dwarn:10 dfail:4 fail:23 skip:813 time:10125s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7160/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake.
2017-11-14 19:47 [PATCH 0/7] WRPLL fixes for HDMI 2.0 on Cannonlake Rodrigo Vivi
` (12 preceding siblings ...)
2017-11-16 17:51 ` ✓ Fi.CI.IGT: " Patchwork
@ 2017-11-16 17:53 ` Rodrigo Vivi
13 siblings, 0 replies; 43+ messages in thread
From: Rodrigo Vivi @ 2017-11-16 17:53 UTC (permalink / raw)
To: intel-gfx
Merged to dinq. Thanks for all reviews and comments.
On Tue, Nov 14, 2017 at 07:47:52PM +0000, Rodrigo Vivi wrote:
> With these fixes and clean-ups around wrpll plus
> extending HDMI 2.0 from GLK to CNL we could finally
> get a functional HDMI 2.0 display with 4k60Hz.
>
> Thanks,
> Rodrigo.
>
> Rodrigo Vivi (7):
> drm/i915/cnl: Remove spurious central_freq.
> drm/i915/cnl: Remove useless conversion.
> drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.
> drm/i915/cnl: Fix wrpll math for higher freqs.
> drm/i915/cnl: Don't blindly replace qdiv.
> drm/i915/cnl: Write dco_fraction calculation as spec.
> drm/i915/cnl: Extend HDMI 2.0 support to CNL.
>
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 42 ++++++++++++++---------------------
> drivers/gpu/drm/i915/intel_hdmi.c | 7 +++---
> 2 files changed, 21 insertions(+), 28 deletions(-)
>
> --
> 2.13.6
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 43+ messages in thread