From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH i-g-t 5/5] tools/intel_watermark: Right justify register names
Date: Wed, 29 Nov 2017 16:31:16 +0200 [thread overview]
Message-ID: <20171129143116.GZ10981@intel.com> (raw)
In-Reply-To: <1511395524.15890.0.camel@dk-H97M-D3H>
On Wed, Nov 22, 2017 at 11:44:32PM +0000, Pandiyan, Dhinakaran wrote:
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> for the
> series.
Series pushed. Thanks for the review.
>
>
> On Tue, 2017-11-21 at 20:49 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > I think the dump is a more legible when the register names
> > are right justified. That way the register name and its value
> > are right next to each other.
> >
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > tools/intel_watermark.c | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> > index 3c70f4ec54fb..308e351dcd2f 100644
> > --- a/tools/intel_watermark.c
> > +++ b/tools/intel_watermark.c
> > @@ -248,7 +248,7 @@ static void skl_wm_dump(void)
> > }
> >
> > for (pipe = 0; pipe < num_pipes; pipe++) {
> > - printf("%-18s 0x%08x\t",
> > + printf("%18s 0x%08x\t",
> > skl_wm_linetime_reg_name(pipe),
> > wm_linetime[pipe]);
> > }
> > @@ -260,7 +260,7 @@ static void skl_wm_dump(void)
> > if (plane >= skl_num_planes(devid, pipe))
> > break;
> >
> > - printf("%-18s 0x%08x\t" ,
> > + printf("%18s 0x%08x\t" ,
> > skl_wm_reg_name(pipe, plane, level),
> > wm[level][pipe][plane]);
> > }
> > @@ -274,7 +274,7 @@ static void skl_wm_dump(void)
> > if (plane >= skl_num_planes(devid, pipe))
> > break;
> >
> > - printf("%-18s 0x%08x\t",
> > + printf("%18s 0x%08x\t",
> > skl_wm_trans_reg_name(pipe, plane),
> > wm_trans[pipe][plane]);
> > }
> > @@ -287,7 +287,7 @@ static void skl_wm_dump(void)
> > if (plane >= skl_num_planes(devid, pipe))
> > break;
> >
> > - printf("%-18s 0x%08x\t",
> > + printf("%18s 0x%08x\t",
> > skl_buf_cfg_reg_name(pipe, plane),
> > buf_cfg[pipe][plane]);
> > }
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2017-11-29 14:31 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-21 18:49 [PATCH i-g-t 1/5] tools/intel_watermark: Silence gcc7 snprintf() warnings Ville Syrjala
2017-11-21 18:49 ` [PATCH i-g-t 2/5] tools/intel_watermark: Refactor reg name stuff Ville Syrjala
2017-11-21 18:49 ` [PATCH i-g-t 3/5] tools/intel_watermark: Clean up SKL plane names Ville Syrjala
2017-11-21 18:49 ` [PATCH i-g-t 4/5] tools/intel_watermark: Clean up formatting Ville Syrjala
2017-11-21 18:49 ` [PATCH i-g-t 5/5] tools/intel_watermark: Right justify register names Ville Syrjala
2017-11-22 23:44 ` Pandiyan, Dhinakaran
2017-11-29 14:31 ` Ville Syrjälä [this message]
2017-11-21 19:45 ` [PATCH i-g-t 1/5] tools/intel_watermark: Silence gcc7 snprintf() warnings Tvrtko Ursulin
2017-11-22 10:09 ` ✓ Fi.CI.BAT: success for series starting with [1/5] " Patchwork
2017-11-22 10:49 ` Patchwork
2017-11-22 11:55 ` ✗ Fi.CI.IGT: warning " Patchwork
2017-11-23 12:02 ` ✓ Fi.CI.BAT: success " Patchwork
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