[PATCH] drm/i915/icl: remove port A/E lane sharing limitation.

[PATCH] drm/i915/icl: remove port A/E lane sharing limitation.

[Mahesh Kumar]

From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>

Platforms before Gen11 were sharing lanes between port-A & port-E.
This limitation is no more there.

Changes since V1:
 - optimize the code (Shashank/Jani)
 - create helper function to get max lanes (ville)

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 43 +++++++++++++++++-----------------------
 1 file changed, 18 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e51559be2e3b..4bde742a8ff4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2842,6 +2842,23 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
 	return false;
 }
 
+static int
+intel_ddi_max_lanes(struct drm_i915_private *dev_priv, enum port port)
+{
+	if (INTEL_GEN(dev_priv) >= 11)
+		return 4;
+
+	if (port == PORT_A || port == PORT_E) {
+		if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
+			return port == PORT_A ? 4 : 0;
+		else
+			/* Both A and E share 2 lanes */
+			return 2;
+	}
+
+	return 4;
+}
+
 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 {
 	struct intel_digital_port *intel_dig_port;
@@ -2850,31 +2867,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	bool init_hdmi, init_dp, init_lspcon = false;
 	int max_lanes;
 
-	if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
-		switch (port) {
-		case PORT_A:
-			max_lanes = 4;
-			break;
-		case PORT_E:
-			max_lanes = 0;
-			break;
-		default:
-			max_lanes = 4;
-			break;
-		}
-	} else {
-		switch (port) {
-		case PORT_A:
-			max_lanes = 2;
-			break;
-		case PORT_E:
-			max_lanes = 2;
-			break;
-		default:
-			max_lanes = 4;
-			break;
-		}
-	}
+	max_lanes = intel_ddi_max_lanes(dev_priv, port);
 
 	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
 		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
-- 
2.14.1

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✓ Fi.CI.BAT: success for drm/i915/icl: remove port A/E lane sharing limitation.

[Patchwork]

== Series Details ==

Series: drm/i915/icl: remove port A/E lane sharing limitation.
URL   : https://patchwork.freedesktop.org/series/37325/
State : success

== Summary ==

Series 37325v1 drm/i915/icl: remove port A/E lane sharing limitation.
https://patchwork.freedesktop.org/api/1.0/series/37325/revisions/1/mbox/

Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                fail       -> PASS       (fi-skl-guc) fdo#103191 +1

fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:429s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:425s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:371s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:281s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:480s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:482s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:465s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:568s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:390s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:399s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:413s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:456s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:414s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:460s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:495s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:455s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:501s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:579s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:427s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:512s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:528s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:489s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:481s
fi-skl-guc       total:288  pass:259  dwarn:0   dfail:0   fail:1   skip:28  time:398s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:431s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:398s
Blacklisted hosts:
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:469s
fi-bdw-5557u failed to connect after reboot
fi-bdw-gvtdvm failed to connect after reboot
fi-bsw-n3050 failed to connect after reboot
fi-bwr-2160 failed to connect after reboot
fi-bxt-dsi failed to connect after reboot
fi-bxt-j4205 failed to connect after reboot
fi-byt-j1900 failed to connect after reboot
fi-byt-n2820 failed to connect after reboot
fi-cfl-s2 failed to connect after reboot
fi-elk-e7500 failed to connect after reboot
fi-gdg-551 failed to connect after reboot
fi-glk-1 failed to connect after reboot
fi-glk-dsi failed to connect after reboot
fi-hsw-4770 failed to connect after reboot
fi-hsw-4770r failed to connect after reboot
fi-ilk-650 failed to connect after reboot
fi-ivb-3520m failed to connect after reboot
fi-ivb-3770 failed to connect after reboot
fi-kbl-7500u failed to connect after reboot
fi-kbl-7560u failed to connect after reboot
fi-kbl-7567u failed to connect after reboot
fi-kbl-r failed to connect after reboot
fi-pnv-d510 failed to connect after reboot
fi-skl-6260u failed to connect after reboot
fi-skl-6600u failed to connect after reboot
fi-skl-6700hq failed to connect after reboot
fi-skl-6700k2 failed to connect after reboot
fi-skl-6770hq failed to connect after reboot
fi-skl-guc failed to connect after reboot
fi-skl-gvtdvm failed to connect after reboot
fi-snb-2520m failed to connect after reboot
fi-snb-2600 failed to connect after reboot

d0eb027422f612e32f5b78983bd25fcbc80c70fc drm-tip: 2018y-01m-30d-10h-47m-29s UTC integration manifest
3e99d14e002b drm/i915/icl: remove port A/E lane sharing limitation.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7814/issues.html
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✓ Fi.CI.IGT: success for drm/i915/icl: remove port A/E lane sharing limitation.

[Patchwork]

== Series Details ==

Series: drm/i915/icl: remove port A/E lane sharing limitation.
URL   : https://patchwork.freedesktop.org/series/37325/
State : success

== Summary ==

Warning: bzip CI_DRM_3697/shard-glkb6/results1.json.bz2 wasn't in correct JSON format
Test kms_sysfs_edid_timing:
                warn       -> PASS       (shard-apl) fdo#100047
Test kms_flip:
        Subgroup wf_vblank-ts-check-interruptible:
                incomplete -> PASS       (shard-snb) fdo#100368
Test perf:
        Subgroup oa-exponents:
                pass       -> FAIL       (shard-apl) fdo#102254
        Subgroup buffer-fill:
                fail       -> PASS       (shard-apl) fdo#103755
Test kms_vblank:
        Subgroup pipe-b-query-idle-hang:
                incomplete -> PASS       (shard-apl)
Test kms_chv_cursor_fail:
        Subgroup pipe-a-128x128-bottom-edge:
                incomplete -> PASS       (shard-apl)
Test drv_selftest:
        Subgroup live_gtt:
                incomplete -> PASS       (shard-apl) fdo#103927
Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-primscrn-shrfb-pgflip-blt:
                pass       -> DMESG-WARN (shard-apl) fdo#101623
Test gem_exec_parallel:
        Subgroup render:
                incomplete -> PASS       (shard-snb)

fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623

shard-apl        total:2838 pass:1749 dwarn:2   dfail:0   fail:23  skip:1064 time:12604s
shard-hsw        total:2838 pass:1734 dwarn:1   dfail:0   fail:12  skip:1090 time:12019s
shard-snb        total:2838 pass:1327 dwarn:1   dfail:0   fail:12  skip:1498 time:6591s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7814/shards.html
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✓ Fi.CI.BAT: success for drm/i915/icl: remove port A/E lane sharing limitation.

[Patchwork]

== Series Details ==

Series: drm/i915/icl: remove port A/E lane sharing limitation.
URL   : https://patchwork.freedesktop.org/series/37325/
State : success

== Summary ==

Series 37325v1 drm/i915/icl: remove port A/E lane sharing limitation.
https://patchwork.freedesktop.org/api/1.0/series/37325/revisions/1/mbox/

Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                fail       -> PASS       (fi-gdg-551) fdo#102575
Test gem_ringfill:
        Subgroup basic-default:
                skip       -> PASS       (fi-bsw-n3050)

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:421s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:424s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:372s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:485s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:280s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:481s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:481s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:468s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:452s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:575s
fi-elk-e7500     total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551       total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 time:279s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:509s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:390s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:402s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:413s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:461s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:417s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:458s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:500s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:452s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:502s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:425s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:511s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:529s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:491s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:479s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:414s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:432s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:524s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:398s
Blacklisted hosts:
fi-glk-dsi       total:151  pass:137  dwarn:0   dfail:0   fail:0   skip:13 

cded8ee063487cfcf4dd7f850d96ed91ddd73bd4 drm-tip: 2018y-01m-30d-14h-46m-36s UTC integration manifest
26425d01c651 drm/i915/icl: remove port A/E lane sharing limitation.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7819/issues.html
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✗ Fi.CI.IGT: warning for drm/i915/icl: remove port A/E lane sharing limitation.

[Patchwork]

== Series Details ==

Series: drm/i915/icl: remove port A/E lane sharing limitation.
URL   : https://patchwork.freedesktop.org/series/37325/
State : warning

== Summary ==

Test perf:
        Subgroup enable-disable:
                fail       -> PASS       (shard-apl) fdo#103715
        Subgroup blocking:
                pass       -> FAIL       (shard-hsw) fdo#102252
        Subgroup oa-exponents:
                fail       -> PASS       (shard-apl) fdo#102254
Test kms_chv_cursor_fail:
        Subgroup pipe-a-256x256-right-edge:
                pass       -> SKIP       (shard-snb)
Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-primscrn-cur-indfb-onoff:
                pass       -> SKIP       (shard-snb) fdo#103167 +1
        Subgroup fbc-1p-offscren-pri-shrfb-draw-mmap-cpu:
                pass       -> FAIL       (shard-apl) fdo#101623
Test kms_atomic_transition:
        Subgroup 1x-modeset-transitions-fencing:
                pass       -> SKIP       (shard-snb)
Test kms_cursor_legacy:
        Subgroup cursor-vs-flip-toggle:
                pass       -> SKIP       (shard-snb)
Test gem_eio:
        Subgroup in-flight-contexts:
                incomplete -> DMESG-WARN (shard-snb) fdo#104058
Test kms_sysfs_edid_timing:
                pass       -> WARN       (shard-apl) fdo#100047
Test kms_flip:
        Subgroup 2x-plain-flip-fb-recreate:
                pass       -> FAIL       (shard-hsw) fdo#100368 +1
Test kms_setmode:
        Subgroup basic:
                fail       -> PASS       (shard-hsw) fdo#99912

fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-apl        total:2838 pass:1749 dwarn:1   dfail:0   fail:23  skip:1064 time:12593s
shard-hsw        total:2838 pass:1733 dwarn:1   dfail:0   fail:13  skip:1090 time:11963s
shard-snb        total:2838 pass:1323 dwarn:2   dfail:0   fail:12  skip:1501 time:6632s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7819/shards.html
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Re: [PATCH] drm/i915/icl: remove port A/E lane sharing limitation.

[Pandiyan, Dhinakaran]

On Tue, 2018-01-30 at 14:51 +0530, Mahesh Kumar wrote:
> From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>
> 
> Platforms before Gen11 were sharing lanes between port-A & port-E.
> This limitation is no more there.
> 
> Changes since V1:
>  - optimize the code (Shashank/Jani)
>  - create helper function to get max lanes (ville)
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 43 +++++++++++++++++-----------------------
>  1 file changed, 18 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index e51559be2e3b..4bde742a8ff4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2842,6 +2842,23 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
>  	return false;
>  }
>  
> +static int
> +intel_ddi_max_lanes(struct drm_i915_private *dev_priv, enum port port)
> +{
> +	if (INTEL_GEN(dev_priv) >= 11)
> +		return 4;
> +
> +	if (port == PORT_A || port == PORT_E) {
> +		if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)


Is the expectation that bios has already written the correct value
depending on the board?

The patch itself looks correct 
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>



> +			return port == PORT_A ? 4 : 0;
> +		else
> +			/* Both A and E share 2 lanes */
> +			return 2;
> +	}
> +
> +	return 4;
> +}
> +
>  void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>  {
>  	struct intel_digital_port *intel_dig_port;
> @@ -2850,31 +2867,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>  	bool init_hdmi, init_dp, init_lspcon = false;
>  	int max_lanes;
>  
> -	if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
> -		switch (port) {
> -		case PORT_A:
> -			max_lanes = 4;
> -			break;
> -		case PORT_E:
> -			max_lanes = 0;
> -			break;
> -		default:
> -			max_lanes = 4;
> -			break;
> -		}
> -	} else {
> -		switch (port) {
> -		case PORT_A:
> -			max_lanes = 2;
> -			break;
> -		case PORT_E:
> -			max_lanes = 2;
> -			break;
> -		default:
> -			max_lanes = 4;
> -			break;
> -		}
> -	}
> +	max_lanes = intel_ddi_max_lanes(dev_priv, port);
>  
>  	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
>  		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
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Re: [PATCH] drm/i915/icl: remove port A/E lane sharing limitation.

[Ville Syrjälä]

On Tue, Jan 30, 2018 at 07:52:14PM +0000, Pandiyan, Dhinakaran wrote:
> 
> On Tue, 2018-01-30 at 14:51 +0530, Mahesh Kumar wrote:
> > From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>
> > 
> > Platforms before Gen11 were sharing lanes between port-A & port-E.
> > This limitation is no more there.
> > 
> > Changes since V1:
> >  - optimize the code (Shashank/Jani)
> >  - create helper function to get max lanes (ville)
> > 
> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c | 43 +++++++++++++++++-----------------------
> >  1 file changed, 18 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index e51559be2e3b..4bde742a8ff4 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2842,6 +2842,23 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
> >  	return false;
> >  }
> >  
> > +static int
> > +intel_ddi_max_lanes(struct drm_i915_private *dev_priv, enum port port)
> > +{
> > +	if (INTEL_GEN(dev_priv) >= 11)
> > +		return 4;
> > +
> > +	if (port == PORT_A || port == PORT_E) {
> > +		if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
> 
> 
> Is the expectation that bios has already written the correct value
> depending on the board?

We have a fixup later on for BIOS fails. Might be nice to try and
pull that in as well so that we would have all the logic in one
clear place.

> 
> The patch itself looks correct 
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> 
> 
> > +			return port == PORT_A ? 4 : 0;
> > +		else
> > +			/* Both A and E share 2 lanes */
> > +			return 2;
> > +	}
> > +
> > +	return 4;
> > +}
> > +
> >  void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> >  {
> >  	struct intel_digital_port *intel_dig_port;
> > @@ -2850,31 +2867,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> >  	bool init_hdmi, init_dp, init_lspcon = false;
> >  	int max_lanes;
> >  
> > -	if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
> > -		switch (port) {
> > -		case PORT_A:
> > -			max_lanes = 4;
> > -			break;
> > -		case PORT_E:
> > -			max_lanes = 0;
> > -			break;
> > -		default:
> > -			max_lanes = 4;
> > -			break;
> > -		}
> > -	} else {
> > -		switch (port) {
> > -		case PORT_A:
> > -			max_lanes = 2;
> > -			break;
> > -		case PORT_E:
> > -			max_lanes = 2;
> > -			break;
> > -		default:
> > -			max_lanes = 4;
> > -			break;
> > -		}
> > -	}
> > +	max_lanes = intel_ddi_max_lanes(dev_priv, port);
> >  
> >  	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
> >  		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[PATCH] drm/i915/icl: remove port A/E lane sharing limitation.

[Mahesh Kumar]

Platforms before Gen11 were sharing lanes between port-A & port-E.
This limitation is no more there.

Changes since V1:
 - optimize the code (Shashank/Jani)
 - create helper function to get max lanes (ville)
Changes since V2:
 - Include BIOS fail fix-up in same helper function (ville)

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 71 +++++++++++++++++++---------------------
 1 file changed, 33 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cfcd9cb37d5d..ee9ba78d19c8 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2842,39 +2842,44 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
 	return false;
 }
 
+static int
+intel_ddi_max_lanes(struct drm_i915_private *dev_priv,
+		    struct intel_digital_port *intel_dig_port)
+{
+	enum port port = intel_dig_port->base.port;
+	int max_lanes = 4;
+
+	if (INTEL_GEN(dev_priv) >= 11) {
+		return 4;
+	} else if (port == PORT_A || port == PORT_E) {
+		if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
+			max_lanes = port == PORT_A ? 4 : 0;
+		else
+			/* Both A and E share 2 lanes */
+			max_lanes = 2;
+	}
+
+	/*
+	 * Some BIOS might fail to set this bit on port A if eDP
+	 * wasn't lit up at boot.  Force this bit set when needed
+	 * so we use the proper lane count for our calculations.
+	 */
+	if (intel_ddi_a_force_4_lanes(intel_dig_port)) {
+		DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
+		intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
+		max_lanes = 4;
+	}
+
+	return max_lanes;
+}
+
 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 {
 	struct intel_digital_port *intel_dig_port;
 	struct intel_encoder *intel_encoder;
 	struct drm_encoder *encoder;
 	bool init_hdmi, init_dp, init_lspcon = false;
-	int max_lanes;
 
-	if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
-		switch (port) {
-		case PORT_A:
-			max_lanes = 4;
-			break;
-		case PORT_E:
-			max_lanes = 0;
-			break;
-		default:
-			max_lanes = 4;
-			break;
-		}
-	} else {
-		switch (port) {
-		case PORT_A:
-			max_lanes = 2;
-			break;
-		case PORT_E:
-			max_lanes = 2;
-			break;
-		default:
-			max_lanes = 4;
-			break;
-		}
-	}
 
 	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
 		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
@@ -2954,19 +2959,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 		MISSING_CASE(port);
 	}
 
-	/*
-	 * Some BIOS might fail to set this bit on port A if eDP
-	 * wasn't lit up at boot.  Force this bit set when needed
-	 * so we use the proper lane count for our calculations.
-	 */
-	if (intel_ddi_a_force_4_lanes(intel_dig_port)) {
-		DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
-		intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
-		max_lanes = 4;
-	}
-
 	intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
-	intel_dig_port->max_lanes = max_lanes;
 
 	intel_encoder->type = INTEL_OUTPUT_DDI;
 	intel_encoder->power_domain = intel_port_to_power_domain(port);
@@ -2974,6 +2967,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 	intel_encoder->cloneable = 0;
 
+	intel_dig_port->max_lanes = intel_ddi_max_lanes(dev_priv,
+							intel_dig_port);
 	intel_infoframe_init(intel_dig_port);
 
 	if (init_dp) {
-- 
2.14.1

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Re: [PATCH] drm/i915/icl: remove port A/E lane sharing limitation.

[Jani Nikula]

On Fri, 02 Feb 2018, Mahesh Kumar <mahesh1.kumar@intel.com> wrote:
> Platforms before Gen11 were sharing lanes between port-A & port-E.
> This limitation is no more there.
>
> Changes since V1:
>  - optimize the code (Shashank/Jani)
>  - create helper function to get max lanes (ville)
> Changes since V2:
>  - Include BIOS fail fix-up in same helper function (ville)
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 71 +++++++++++++++++++---------------------
>  1 file changed, 33 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cfcd9cb37d5d..ee9ba78d19c8 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2842,39 +2842,44 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
>  	return false;
>  }
>  
> +static int
> +intel_ddi_max_lanes(struct drm_i915_private *dev_priv,
> +		    struct intel_digital_port *intel_dig_port)
> +{

Please ditch the dev_priv parameter and add:

	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);

> +	enum port port = intel_dig_port->base.port;
> +	int max_lanes = 4;

Unnecessary initialization.

> +
> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		return 4;

Please either set max_lanes = 4 here, or remove the else. On early
returns, you don't need the else. Having both is confusing.

> +	} else if (port == PORT_A || port == PORT_E) {
> +		if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
> +			max_lanes = port == PORT_A ? 4 : 0;
> +		else
> +			/* Both A and E share 2 lanes */
> +			max_lanes = 2;
> +	}
> +
> +	/*
> +	 * Some BIOS might fail to set this bit on port A if eDP
> +	 * wasn't lit up at boot.  Force this bit set when needed
> +	 * so we use the proper lane count for our calculations.
> +	 */
> +	if (intel_ddi_a_force_4_lanes(intel_dig_port)) {
> +		DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
> +		intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> +		max_lanes = 4;
> +	}
> +
> +	return max_lanes;
> +}
> +
>  void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>  {
>  	struct intel_digital_port *intel_dig_port;
>  	struct intel_encoder *intel_encoder;
>  	struct drm_encoder *encoder;
>  	bool init_hdmi, init_dp, init_lspcon = false;
> -	int max_lanes;
>  
> -	if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
> -		switch (port) {
> -		case PORT_A:
> -			max_lanes = 4;
> -			break;
> -		case PORT_E:
> -			max_lanes = 0;
> -			break;
> -		default:
> -			max_lanes = 4;
> -			break;
> -		}
> -	} else {
> -		switch (port) {
> -		case PORT_A:
> -			max_lanes = 2;
> -			break;
> -		case PORT_E:
> -			max_lanes = 2;
> -			break;
> -		default:
> -			max_lanes = 4;
> -			break;
> -		}
> -	}
>  
>  	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
>  		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
> @@ -2954,19 +2959,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>  		MISSING_CASE(port);
>  	}
>  
> -	/*
> -	 * Some BIOS might fail to set this bit on port A if eDP
> -	 * wasn't lit up at boot.  Force this bit set when needed
> -	 * so we use the proper lane count for our calculations.
> -	 */
> -	if (intel_ddi_a_force_4_lanes(intel_dig_port)) {
> -		DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
> -		intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> -		max_lanes = 4;
> -	}
> -
>  	intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
> -	intel_dig_port->max_lanes = max_lanes;
>  
>  	intel_encoder->type = INTEL_OUTPUT_DDI;
>  	intel_encoder->power_domain = intel_port_to_power_domain(port);
> @@ -2974,6 +2967,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>  	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>  	intel_encoder->cloneable = 0;
>  
> +	intel_dig_port->max_lanes = intel_ddi_max_lanes(dev_priv,
> +							intel_dig_port);

Please keep this at the original location above.

BR,
Jani.

>  	intel_infoframe_init(intel_dig_port);
>  
>  	if (init_dp) {

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH] drm/i915/icl: remove port A/E lane sharing limitation.

[Kumar, Mahesh]

Hi,


On 2/2/2018 6:26 PM, Jani Nikula wrote:
> On Fri, 02 Feb 2018, Mahesh Kumar <mahesh1.kumar@intel.com> wrote:
>> Platforms before Gen11 were sharing lanes between port-A & port-E.
>> This limitation is no more there.
>>
>> Changes since V1:
>>   - optimize the code (Shashank/Jani)
>>   - create helper function to get max lanes (ville)
>> Changes since V2:
>>   - Include BIOS fail fix-up in same helper function (ville)
>>
>> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
>> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_ddi.c | 71 +++++++++++++++++++---------------------
>>   1 file changed, 33 insertions(+), 38 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index cfcd9cb37d5d..ee9ba78d19c8 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -2842,39 +2842,44 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
>>   	return false;
>>   }
>>   
>> +static int
>> +intel_ddi_max_lanes(struct drm_i915_private *dev_priv,
>> +		    struct intel_digital_port *intel_dig_port)
>> +{
> Please ditch the dev_priv parameter and add:
>
> 	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
ok, sure.
>
>> +	enum port port = intel_dig_port->base.port;
>> +	int max_lanes = 4;
> Unnecessary initialization.
for ports other than PORT_A/E will have max_lanes=4 that's the reason 
initializing it here, will fix the usages.
>
>> +
>> +	if (INTEL_GEN(dev_priv) >= 11) {
>> +		return 4;
> Please either set max_lanes = 4 here, or remove the else. On early
> returns, you don't need the else. Having both is confusing.
yes, agree, will remove the else
>
>> +	} else if (port == PORT_A || port == PORT_E) {
>> +		if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
>> +			max_lanes = port == PORT_A ? 4 : 0;
>> +		else
>> +			/* Both A and E share 2 lanes */
>> +			max_lanes = 2;
>> +	}
>> +
>> +	/*
>> +	 * Some BIOS might fail to set this bit on port A if eDP
>> +	 * wasn't lit up at boot.  Force this bit set when needed
>> +	 * so we use the proper lane count for our calculations.
>> +	 */
>> +	if (intel_ddi_a_force_4_lanes(intel_dig_port)) {
>> +		DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
>> +		intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
>> +		max_lanes = 4;
>> +	}
>> +
>> +	return max_lanes;
>> +}
>> +
>>   void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>>   {
>>   	struct intel_digital_port *intel_dig_port;
>>   	struct intel_encoder *intel_encoder;
>>   	struct drm_encoder *encoder;
>>   	bool init_hdmi, init_dp, init_lspcon = false;
>> -	int max_lanes;
>>   
>> -	if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
>> -		switch (port) {
>> -		case PORT_A:
>> -			max_lanes = 4;
>> -			break;
>> -		case PORT_E:
>> -			max_lanes = 0;
>> -			break;
>> -		default:
>> -			max_lanes = 4;
>> -			break;
>> -		}
>> -	} else {
>> -		switch (port) {
>> -		case PORT_A:
>> -			max_lanes = 2;
>> -			break;
>> -		case PORT_E:
>> -			max_lanes = 2;
>> -			break;
>> -		default:
>> -			max_lanes = 4;
>> -			break;
>> -		}
>> -	}
>>   
>>   	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
>>   		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
>> @@ -2954,19 +2959,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>>   		MISSING_CASE(port);
>>   	}
>>   
>> -	/*
>> -	 * Some BIOS might fail to set this bit on port A if eDP
>> -	 * wasn't lit up at boot.  Force this bit set when needed
>> -	 * so we use the proper lane count for our calculations.
>> -	 */
>> -	if (intel_ddi_a_force_4_lanes(intel_dig_port)) {
>> -		DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
>> -		intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
>> -		max_lanes = 4;
>> -	}
>> -
>>   	intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
>> -	intel_dig_port->max_lanes = max_lanes;
>>   
>>   	intel_encoder->type = INTEL_OUTPUT_DDI;
>>   	intel_encoder->power_domain = intel_port_to_power_domain(port);
>> @@ -2974,6 +2967,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>>   	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>>   	intel_encoder->cloneable = 0;
>>   
>> +	intel_dig_port->max_lanes = intel_ddi_max_lanes(dev_priv,
>> +							intel_dig_port);
> Please keep this at the original location above.
I moved this here because intel_encoder->port was not initialized in 
original location, will pass port along with intel_dig_port & move it to 
original location.
Thanks for review.

-Mahesh
>
> BR,
> Jani.
>
>>   	intel_infoframe_init(intel_dig_port);
>>   
>>   	if (init_dp) {

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Re: [PATCH] drm/i915/icl: remove port A/E lane sharing limitation.

[Jani Nikula]

On Mon, 05 Feb 2018, "Kumar, Mahesh" <mahesh1.kumar@intel.com> wrote:
> Hi,
>
>
> On 2/2/2018 6:26 PM, Jani Nikula wrote:
>> On Fri, 02 Feb 2018, Mahesh Kumar <mahesh1.kumar@intel.com> wrote:
>>> Platforms before Gen11 were sharing lanes between port-A & port-E.
>>> This limitation is no more there.
>>>
>>> Changes since V1:
>>>   - optimize the code (Shashank/Jani)
>>>   - create helper function to get max lanes (ville)
>>> Changes since V2:
>>>   - Include BIOS fail fix-up in same helper function (ville)
>>>
>>> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
>>> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/intel_ddi.c | 71 +++++++++++++++++++---------------------
>>>   1 file changed, 33 insertions(+), 38 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>>> index cfcd9cb37d5d..ee9ba78d19c8 100644
>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>>> @@ -2842,39 +2842,44 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
>>>   	return false;
>>>   }
>>>   
>>> +static int
>>> +intel_ddi_max_lanes(struct drm_i915_private *dev_priv,
>>> +		    struct intel_digital_port *intel_dig_port)
>>> +{
>> Please ditch the dev_priv parameter and add:
>>
>> 	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
> ok, sure.
>>
>>> +	enum port port = intel_dig_port->base.port;
>>> +	int max_lanes = 4;
>> Unnecessary initialization.
> for ports other than PORT_A/E will have max_lanes=4 that's the reason 
> initializing it here, will fix the usages.
>>
>>> +
>>> +	if (INTEL_GEN(dev_priv) >= 11) {
>>> +		return 4;
>> Please either set max_lanes = 4 here, or remove the else. On early
>> returns, you don't need the else. Having both is confusing.
> yes, agree, will remove the else
>>
>>> +	} else if (port == PORT_A || port == PORT_E) {
>>> +		if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
>>> +			max_lanes = port == PORT_A ? 4 : 0;
>>> +		else
>>> +			/* Both A and E share 2 lanes */
>>> +			max_lanes = 2;
>>> +	}
>>> +
>>> +	/*
>>> +	 * Some BIOS might fail to set this bit on port A if eDP
>>> +	 * wasn't lit up at boot.  Force this bit set when needed
>>> +	 * so we use the proper lane count for our calculations.
>>> +	 */
>>> +	if (intel_ddi_a_force_4_lanes(intel_dig_port)) {
>>> +		DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
>>> +		intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
>>> +		max_lanes = 4;
>>> +	}
>>> +
>>> +	return max_lanes;
>>> +}
>>> +
>>>   void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>>>   {
>>>   	struct intel_digital_port *intel_dig_port;
>>>   	struct intel_encoder *intel_encoder;
>>>   	struct drm_encoder *encoder;
>>>   	bool init_hdmi, init_dp, init_lspcon = false;
>>> -	int max_lanes;
>>>   
>>> -	if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
>>> -		switch (port) {
>>> -		case PORT_A:
>>> -			max_lanes = 4;
>>> -			break;
>>> -		case PORT_E:
>>> -			max_lanes = 0;
>>> -			break;
>>> -		default:
>>> -			max_lanes = 4;
>>> -			break;
>>> -		}
>>> -	} else {
>>> -		switch (port) {
>>> -		case PORT_A:
>>> -			max_lanes = 2;
>>> -			break;
>>> -		case PORT_E:
>>> -			max_lanes = 2;
>>> -			break;
>>> -		default:
>>> -			max_lanes = 4;
>>> -			break;
>>> -		}
>>> -	}
>>>   
>>>   	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
>>>   		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
>>> @@ -2954,19 +2959,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>>>   		MISSING_CASE(port);
>>>   	}
>>>   
>>> -	/*
>>> -	 * Some BIOS might fail to set this bit on port A if eDP
>>> -	 * wasn't lit up at boot.  Force this bit set when needed
>>> -	 * so we use the proper lane count for our calculations.
>>> -	 */
>>> -	if (intel_ddi_a_force_4_lanes(intel_dig_port)) {
>>> -		DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
>>> -		intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
>>> -		max_lanes = 4;
>>> -	}
>>> -
>>>   	intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
>>> -	intel_dig_port->max_lanes = max_lanes;
>>>   
>>>   	intel_encoder->type = INTEL_OUTPUT_DDI;
>>>   	intel_encoder->power_domain = intel_port_to_power_domain(port);
>>> @@ -2974,6 +2967,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>>>   	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>>>   	intel_encoder->cloneable = 0;
>>>   
>>> +	intel_dig_port->max_lanes = intel_ddi_max_lanes(dev_priv,
>>> +							intel_dig_port);
>> Please keep this at the original location above.
> I moved this here because intel_encoder->port was not initialized in 
> original location, will pass port along with intel_dig_port & move it to 
> original location.

Right, so alternatively you could move all the intel_dig_port init to
the same place.

BR,
Jani.

> Thanks for review.
>
> -Mahesh
>>
>> BR,
>> Jani.
>>
>>>   	intel_infoframe_init(intel_dig_port);
>>>   
>>>   	if (init_dp) {
>

-- 
Jani Nikula, Intel Open Source Technology Center
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