Re: [PATCH 17/20] drm/i915/icl: Add configuring MOCS in new Icelake engines

Michel Thierry
2018-02-13T18:13:02Z

On 13/02/18 08:37, Mika Kuoppala wrote:
> From: Tomasz Lis <tomasz.lis@intel.com>
>
> In Icelake, there are more engines on which Memory Object Control States need
> to be configured. Besides adding Icelake under Skylake config, the patch makes
> sure MOCS register addresses for the new engines are properly defined.
>
> Additional patch might be need later, in case the specification will
> propose different MOCS config values for Icelake than in previous gens.
>
> v2: Restricted comments to gen11, updated description, renamed defines.
>
> v3: Used proper engine indexes for gen11.
>
> v4: Removed engines which are not part of gen11.0
>
> v5: Style fixes (proposed by mwajdeczko)
>
> BSpec: 19405
> BSpec: 21140
> Cc: Oscar Mateo Lozano <oscar.mateo@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_mocs.c | 5 ++++-
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 38824a6e5d05..ffe48e530b8d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9785,6 +9785,8 @@ enum skl_power_gate {
> #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
> #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
> #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
> +/* Media decoder 2 MOCS registers */
> +#define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4)
>
> /* gamt regs */
> #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index abb7a8c1e340..2d75666537b3 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -178,7 +178,8 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
> {
> bool result = false;
>
> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> + if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
> + IS_ICELAKE(dev_priv)) {
> table->size = ARRAY_SIZE(skylake_mocs_table);
> table->table = skylake_mocs_table;
> result = true;
> @@ -217,6 +218,8 @@ static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index)
> return GEN9_VEBOX_MOCS(index);
> case VCS2:
> return GEN9_MFX1_MOCS(index);
> + case VCS3:
> + return GEN11_MFX2_MOCS(index);
> default:
> MISSING_CASE(engine_id);
> return INVALID_MMIO_REG;
> --
> 2.14.1
>

Reviewed-by: Michel Thierry <michel.thierry@intel.com>