Re: [PATCH 5/5] drm/i915/psr: Display WA #1130: bxt, glk

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 5/5] drm/i915/psr: Display WA #1130: bxt, glk
Date: Mon, 26 Feb 2018 15:05:28 -0800	[thread overview]
Message-ID: <20180226230528.GB2294@intel.com> (raw)
In-Reply-To: <1519434246.14651.38.camel@dk-H97M-D3H>

On Fri, Feb 23, 2018 at 04:40:38PM -0800, Pandiyan, Dhinakaran wrote:
> On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> > Host/Render modifications do not trigger PSR exit
> > or Wireless quick capture exit correctly.
> > 
> 
> I don't get this workaround either. The wording indicates frontbuffer
> modifications are expected to trigger PSR exit in HW. But we rely on the
> driver's frontbuffer tracking to do that for us.

With us moving more towards more HW tracking I believe it is good
to have hw tracking Wa related in place just in case.

> 
> 
> 
> > WA: Set MMIO register 0x4653C bit 31 = 1b.
> > 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 1 +
> >  drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
> >  2 files changed, 8 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 0f423cd52983..8a4cd8b4bd7c 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3924,6 +3924,7 @@ enum {
> >  #define   PWM1_GATING_DIS		(1 << 13)
> >  
> >  #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
> > +#define   BXT_DCIPH_GATING_DIS		(1 << 31)
> >  #define   BXT_GMBUS_GATING_DIS		(1 << 14)
> >  
> >  #define _CLKGATE_DIS_PSL_A		0x46520
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 7e15b261821d..a0a6b4b7c47b 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -114,6 +114,10 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
> >  	 */
> >  	I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
> >  		   PWM1_GATING_DIS | PWM2_GATING_DIS);
> > +
> > +	/* Display WA #1130:bxt */
> > +	I915_WRITE(GEN9_CLKGATE_DIS_4, I915_READ(GEN9_CLKGATE_DIS_4) |
> > +		   BXT_DCIPH_GATING_DIS);
> >  }
> >  
> >  static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
> > @@ -137,6 +141,9 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
> >  		I915_WRITE(CHICKEN_MISC_2, val);
> >  	}
> >  
> > +	/* Display WA #1130:glk */
> > +	I915_WRITE(GEN9_CLKGATE_DIS_4, I915_READ(GEN9_CLKGATE_DIS_4) |
> > +		   BXT_DCIPH_GATING_DIS);
> >  }
> >  
> >  static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
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