* ✓ Fi.CI.BAT: success for drm/i915/dp: move link rate arrays where they're used
2018-02-27 10:59 [RFC] drm/i915/dp: move link rate arrays where they're used Jani Nikula
@ 2018-02-27 13:27 ` Patchwork
2018-02-27 18:05 ` [RFC] " Pandiyan, Dhinakaran
` (6 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-02-27 13:27 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dp: move link rate arrays where they're used
URL : https://patchwork.freedesktop.org/series/39032/
State : success
== Summary ==
Series 39032v1 drm/i915/dp: move link rate arrays where they're used
https://patchwork.freedesktop.org/api/1.0/series/39032/revisions/1/mbox/
---- Possible new issues:
Test kms_force_connector_basic:
Subgroup force-connector-state:
skip -> PASS (fi-ivb-3520m)
Subgroup force-edid:
skip -> PASS (fi-ivb-3520m)
Subgroup force-load-detect:
skip -> PASS (fi-ivb-3520m)
Subgroup prune-stale-modes:
skip -> PASS (fi-ivb-3520m)
---- Known issues:
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass -> FAIL (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-bdw-5557u) fdo#104162
Subgroup suspend-read-crc-pipe-c:
incomplete -> PASS (fi-bxt-dsi) fdo#103927
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fi-bdw-5557u total:245 pass:227 dwarn:0 dfail:0 fail:0 skip:17
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:421s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:372s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:486s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:285s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:472s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:484s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:468s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:457s
fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:392s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:569s
fi-cnl-y3 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:581s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:413s
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:285s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:507s
fi-hsw-4770 total:288 pass:259 dwarn:0 dfail:0 fail:2 skip:27 time:410s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:411s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:459s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:419s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:453s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:489s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:449s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:498s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:582s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:424s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:502s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:520s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:495s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:496s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:406s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:426s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:522s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:391s
aea43a430276951b4e164501e2cf8da77f6b2171 drm-tip: 2018y-02m-27d-10h-49m-38s UTC integration manifest
bea5d9a1cb45 drm/i915/dp: move link rate arrays where they're used
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8171/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [RFC] drm/i915/dp: move link rate arrays where they're used
2018-02-27 10:59 [RFC] drm/i915/dp: move link rate arrays where they're used Jani Nikula
2018-02-27 13:27 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2018-02-27 18:05 ` Pandiyan, Dhinakaran
2018-02-27 18:52 ` Jani Nikula
2018-02-27 18:22 ` Manasi Navare
` (5 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Pandiyan, Dhinakaran @ 2018-02-27 18:05 UTC (permalink / raw)
To: Nikula, Jani; +Cc: intel-gfx@lists.freedesktop.org
On Tue, 2018-02-27 at 12:59 +0200, Jani Nikula wrote:
> Localize link rate arrays by moving them to the functions where they're
> used.
I feel this array expresses platform capability concisely and it's easy
to quickly check what rates a platform supports when the array is at the
top. But,that's probably just me.
-DK
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [RFC] drm/i915/dp: move link rate arrays where they're used
2018-02-27 18:05 ` [RFC] " Pandiyan, Dhinakaran
@ 2018-02-27 18:52 ` Jani Nikula
2018-02-27 21:10 ` Manasi Navare
0 siblings, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2018-02-27 18:52 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx@lists.freedesktop.org
On Tue, 27 Feb 2018, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:
> On Tue, 2018-02-27 at 12:59 +0200, Jani Nikula wrote:
>> Localize link rate arrays by moving them to the functions where they're
>> used.
>
> I feel this array expresses platform capability concisely and it's easy
> to quickly check what rates a platform supports when the array is at the
> top. But,that's probably just me.
I could argue both ways myself, hence RFC. :)
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [RFC] drm/i915/dp: move link rate arrays where they're used
2018-02-27 18:52 ` Jani Nikula
@ 2018-02-27 21:10 ` Manasi Navare
0 siblings, 0 replies; 13+ messages in thread
From: Manasi Navare @ 2018-02-27 21:10 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx@lists.freedesktop.org, Pandiyan, Dhinakaran
On Tue, Feb 27, 2018 at 08:52:49PM +0200, Jani Nikula wrote:
> On Tue, 27 Feb 2018, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:
> > On Tue, 2018-02-27 at 12:59 +0200, Jani Nikula wrote:
> >> Localize link rate arrays by moving them to the functions where they're
> >> used.
> >
> > I feel this array expresses platform capability concisely and it's easy
> > to quickly check what rates a platform supports when the array is at the
> > top. But,that's probably just me.
>
> I could argue both ways myself, hence RFC. :)
>
> BR,
> Jani.
>
I prefer the localized array of these per platform rates since its better if
this information is abstracted from the user and user only sees an array source_rates[].
Per platform rates will still be part of separate arrays for debug purposes and to check
them within code, but since the rest of the driver only uses source_rates, sink_rates,
common_rates arrays, having these per platform arrays local to the function make more sense.
Regards
Manasi
>
> --
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [RFC] drm/i915/dp: move link rate arrays where they're used
2018-02-27 10:59 [RFC] drm/i915/dp: move link rate arrays where they're used Jani Nikula
2018-02-27 13:27 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-02-27 18:05 ` [RFC] " Pandiyan, Dhinakaran
@ 2018-02-27 18:22 ` Manasi Navare
2018-02-27 18:51 ` Jani Nikula
2018-02-27 20:05 ` ✗ Fi.CI.IGT: failure for " Patchwork
` (4 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Manasi Navare @ 2018-02-27 18:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Feb 27, 2018 at 12:59:11PM +0200, Jani Nikula wrote:
> Localize link rate arrays by moving them to the functions where they're
> used. Further clarify the distinction between source and sink
> capabilities. Split pre and post Haswell arrays, and get rid of the
> array size arithmetics. Use a direct rate value in the paranoia case of
> no common rates find.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 44 +++++++++++++++++++++++++----------------
> 1 file changed, 27 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 801a21b16004..6fa6583b16bd 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -96,15 +96,6 @@ static const struct dp_link_dpll chv_dpll[] = {
> { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
> };
>
> -static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
> - 324000, 432000, 540000 };
> -static const int skl_rates[] = { 162000, 216000, 270000,
> - 324000, 432000, 540000 };
> -static const int cnl_rates[] = { 162000, 216000, 270000,
> - 324000, 432000, 540000,
> - 648000, 810000 };
> -static const int default_rates[] = { 162000, 270000, 540000 };
> -
> /**
> * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
> * @intel_dp: DP struct
> @@ -144,14 +135,17 @@ static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> /* update sink rates from dpcd */
> static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
> {
> + static const int dp_rates[] = {
> + 162000, 270000, 540000
> + };
Now that the sink rates can be as high as 810000, shouldnt dp_rates[] include that rate?
Since we use this to populate sink_rates, if the max rate from dpcd is 810000, currently
the sink rates will not get populated with that.
Manasi
> int i, max_rate;
>
> max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
>
> - for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
> - if (default_rates[i] > max_rate)
> + for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
> + if (dp_rates[i] > max_rate)
> break;
> - intel_dp->sink_rates[i] = default_rates[i];
> + intel_dp->sink_rates[i] = dp_rates[i];
> }
>
> intel_dp->num_sink_rates = i;
> @@ -268,6 +262,22 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
> static void
> intel_dp_set_source_rates(struct intel_dp *intel_dp)
> {
> + /* The values must be in increasing order */
> + static const int cnl_rates[] = {
> + 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
> + };
> + static const int bxt_rates[] = {
> + 162000, 216000, 243000, 270000, 324000, 432000, 540000
> + };
> + static const int skl_rates[] = {
> + 162000, 216000, 270000, 324000, 432000, 540000
> + };
> + static const int hsw_rates[] = {
> + 162000, 270000, 540000
> + };
> + static const int g4x_rates[] = {
> + 162000, 270000
> + };
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> const struct ddi_vbt_port_info *info =
> @@ -290,11 +300,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> size = ARRAY_SIZE(skl_rates);
> } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
> IS_BROADWELL(dev_priv)) {
> - source_rates = default_rates;
> - size = ARRAY_SIZE(default_rates);
> + source_rates = hsw_rates;
> + size = ARRAY_SIZE(hsw_rates);
> } else {
> - source_rates = default_rates;
> - size = ARRAY_SIZE(default_rates) - 1;
> + source_rates = g4x_rates;
> + size = ARRAY_SIZE(g4x_rates);
> }
>
> if (max_rate && vbt_max_rate)
> @@ -356,7 +366,7 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
>
> /* Paranoia, there should always be something in common. */
> if (WARN_ON(intel_dp->num_common_rates == 0)) {
> - intel_dp->common_rates[0] = default_rates[0];
> + intel_dp->common_rates[0] = 162000;
> intel_dp->num_common_rates = 1;
> }
> }
> --
> 2.11.0
>
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [RFC] drm/i915/dp: move link rate arrays where they're used
2018-02-27 18:22 ` Manasi Navare
@ 2018-02-27 18:51 ` Jani Nikula
0 siblings, 0 replies; 13+ messages in thread
From: Jani Nikula @ 2018-02-27 18:51 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Tue, 27 Feb 2018, Manasi Navare <manasi.d.navare@intel.com> wrote:
> On Tue, Feb 27, 2018 at 12:59:11PM +0200, Jani Nikula wrote:
>> Localize link rate arrays by moving them to the functions where they're
>> used. Further clarify the distinction between source and sink
>> capabilities. Split pre and post Haswell arrays, and get rid of the
>> array size arithmetics. Use a direct rate value in the paranoia case of
>> no common rates find.
>>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 44 +++++++++++++++++++++++++----------------
>> 1 file changed, 27 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 801a21b16004..6fa6583b16bd 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -96,15 +96,6 @@ static const struct dp_link_dpll chv_dpll[] = {
>> { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>> };
>>
>> -static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
>> - 324000, 432000, 540000 };
>> -static const int skl_rates[] = { 162000, 216000, 270000,
>> - 324000, 432000, 540000 };
>> -static const int cnl_rates[] = { 162000, 216000, 270000,
>> - 324000, 432000, 540000,
>> - 648000, 810000 };
>> -static const int default_rates[] = { 162000, 270000, 540000 };
>> -
>> /**
>> * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
>> * @intel_dp: DP struct
>> @@ -144,14 +135,17 @@ static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>> /* update sink rates from dpcd */
>> static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
>> {
>> + static const int dp_rates[] = {
>> + 162000, 270000, 540000
>> + };
>
> Now that the sink rates can be as high as 810000, shouldnt dp_rates[] include that rate?
> Since we use this to populate sink_rates, if the max rate from dpcd is 810000, currently
> the sink rates will not get populated with that.
This patch is non-functional. Any other changes should be on top.
BR,
Jani.
>
> Manasi
>
>> int i, max_rate;
>>
>> max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
>>
>> - for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
>> - if (default_rates[i] > max_rate)
>> + for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
>> + if (dp_rates[i] > max_rate)
>> break;
>> - intel_dp->sink_rates[i] = default_rates[i];
>> + intel_dp->sink_rates[i] = dp_rates[i];
>> }
>>
>> intel_dp->num_sink_rates = i;
>> @@ -268,6 +262,22 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
>> static void
>> intel_dp_set_source_rates(struct intel_dp *intel_dp)
>> {
>> + /* The values must be in increasing order */
>> + static const int cnl_rates[] = {
>> + 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
>> + };
>> + static const int bxt_rates[] = {
>> + 162000, 216000, 243000, 270000, 324000, 432000, 540000
>> + };
>> + static const int skl_rates[] = {
>> + 162000, 216000, 270000, 324000, 432000, 540000
>> + };
>> + static const int hsw_rates[] = {
>> + 162000, 270000, 540000
>> + };
>> + static const int g4x_rates[] = {
>> + 162000, 270000
>> + };
>> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>> const struct ddi_vbt_port_info *info =
>> @@ -290,11 +300,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>> size = ARRAY_SIZE(skl_rates);
>> } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
>> IS_BROADWELL(dev_priv)) {
>> - source_rates = default_rates;
>> - size = ARRAY_SIZE(default_rates);
>> + source_rates = hsw_rates;
>> + size = ARRAY_SIZE(hsw_rates);
>> } else {
>> - source_rates = default_rates;
>> - size = ARRAY_SIZE(default_rates) - 1;
>> + source_rates = g4x_rates;
>> + size = ARRAY_SIZE(g4x_rates);
>> }
>>
>> if (max_rate && vbt_max_rate)
>> @@ -356,7 +366,7 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
>>
>> /* Paranoia, there should always be something in common. */
>> if (WARN_ON(intel_dp->num_common_rates == 0)) {
>> - intel_dp->common_rates[0] = default_rates[0];
>> + intel_dp->common_rates[0] = 162000;
>> intel_dp->num_common_rates = 1;
>> }
>> }
>> --
>> 2.11.0
>>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915/dp: move link rate arrays where they're used
2018-02-27 10:59 [RFC] drm/i915/dp: move link rate arrays where they're used Jani Nikula
` (2 preceding siblings ...)
2018-02-27 18:22 ` Manasi Navare
@ 2018-02-27 20:05 ` Patchwork
2018-02-28 9:51 ` ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-02-27 20:05 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dp: move link rate arrays where they're used
URL : https://patchwork.freedesktop.org/series/39032/
State : failure
== Summary ==
---- Possible new issues:
Test kms_draw_crc:
Subgroup draw-method-rgb565-blt-untiled:
pass -> SKIP (shard-snb)
Test kms_vblank:
Subgroup pipe-b-ts-continuation-suspend:
skip -> PASS (shard-snb)
Test pm_rpm:
Subgroup cursor-dpms:
pass -> FAIL (shard-hsw)
---- Known issues:
Test gem_eio:
Subgroup in-flight:
incomplete -> PASS (shard-apl) fdo#104945
Test kms_flip:
Subgroup flip-vs-expired-vblank:
fail -> PASS (shard-hsw) fdo#102887
Test kms_sysfs_edid_timing:
pass -> WARN (shard-apl) fdo#100047
Test perf:
Subgroup enable-disable:
fail -> PASS (shard-apl) fdo#103715
Subgroup polling:
pass -> FAIL (shard-hsw) fdo#102252
fdo#104945 https://bugs.freedesktop.org/show_bug.cgi?id=104945
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
shard-apl total:3460 pass:1819 dwarn:1 dfail:0 fail:7 skip:1632 time:12342s
shard-hsw total:3460 pass:1725 dwarn:1 dfail:0 fail:45 skip:1688 time:11991s
shard-snb total:3460 pass:1357 dwarn:1 dfail:0 fail:2 skip:2100 time:6656s
Blacklisted hosts:
shard-kbl total:3460 pass:1943 dwarn:1 dfail:0 fail:7 skip:1509 time:9620s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8171/shards.html
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^ permalink raw reply [flat|nested] 13+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915/dp: move link rate arrays where they're used
2018-02-27 10:59 [RFC] drm/i915/dp: move link rate arrays where they're used Jani Nikula
` (3 preceding siblings ...)
2018-02-27 20:05 ` ✗ Fi.CI.IGT: failure for " Patchwork
@ 2018-02-28 9:51 ` Patchwork
2018-02-28 10:53 ` ✗ Fi.CI.IGT: warning " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-02-28 9:51 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dp: move link rate arrays where they're used
URL : https://patchwork.freedesktop.org/series/39032/
State : success
== Summary ==
Series 39032v1 drm/i915/dp: move link rate arrays where they're used
https://patchwork.freedesktop.org/api/1.0/series/39032/revisions/1/mbox/
---- Known issues:
Test gem_exec_suspend:
Subgroup basic-s3:
dmesg-warn -> PASS (fi-skl-6700k2) fdo#104108
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-WARN (fi-cnl-y3) fdo#103191
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:418s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:426s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:375s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:488s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:285s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:485s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:468s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:459s
fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:394s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:559s
fi-cnl-y3 total:288 pass:261 dwarn:1 dfail:0 fail:0 skip:26 time:577s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:414s
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:293s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:508s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:392s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:411s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:441s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:410s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:455s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:494s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:452s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:494s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:583s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:428s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:503s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:526s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:491s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:471s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:407s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:436s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:523s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:398s
5d22ee63b365bf7e08e0c06d4c7ff62501f27477 drm-tip: 2018y-02m-28d-00h-25m-02s UTC integration manifest
ef9d2c75d087 drm/i915/dp: move link rate arrays where they're used
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8183/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* ✗ Fi.CI.IGT: warning for drm/i915/dp: move link rate arrays where they're used
2018-02-27 10:59 [RFC] drm/i915/dp: move link rate arrays where they're used Jani Nikula
` (4 preceding siblings ...)
2018-02-28 9:51 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-02-28 10:53 ` Patchwork
2018-02-28 21:02 ` [RFC] " Ville Syrjälä
2018-02-28 21:17 ` Manasi Navare
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-02-28 10:53 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dp: move link rate arrays where they're used
URL : https://patchwork.freedesktop.org/series/39032/
State : warning
== Summary ==
---- Possible new issues:
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-scndscrn-indfb-msflip-blt:
pass -> SKIP (shard-hsw)
---- Known issues:
Test gem_eio:
Subgroup in-flight-external:
incomplete -> PASS (shard-apl) fdo#104945
Test kms_chv_cursor_fail:
Subgroup pipe-b-128x128-top-edge:
dmesg-warn -> PASS (shard-snb) fdo#105185
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
pass -> FAIL (shard-hsw) fdo#102887 +1
Test kms_mmap_write_crc:
fail -> PASS (shard-apl) fdo#103286
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
Test kms_sysfs_edid_timing:
pass -> WARN (shard-apl) fdo#100047
Test kms_vblank:
Subgroup pipe-b-ts-continuation-dpms-suspend:
incomplete -> PASS (shard-hsw) fdo#105054
Test pm_rpm:
Subgroup system-suspend:
incomplete -> PASS (shard-hsw) fdo#103375
fdo#104945 https://bugs.freedesktop.org/show_bug.cgi?id=104945
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103286 https://bugs.freedesktop.org/show_bug.cgi?id=103286
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#105054 https://bugs.freedesktop.org/show_bug.cgi?id=105054
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
shard-apl total:3460 pass:1819 dwarn:1 dfail:0 fail:7 skip:1632 time:12192s
shard-hsw total:3460 pass:1764 dwarn:1 dfail:0 fail:3 skip:1691 time:11751s
shard-snb total:3460 pass:1359 dwarn:1 dfail:0 fail:1 skip:2099 time:6589s
Blacklisted hosts:
shard-kbl total:3460 pass:1942 dwarn:1 dfail:0 fail:8 skip:1509 time:9581s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8183/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [RFC] drm/i915/dp: move link rate arrays where they're used
2018-02-27 10:59 [RFC] drm/i915/dp: move link rate arrays where they're used Jani Nikula
` (5 preceding siblings ...)
2018-02-28 10:53 ` ✗ Fi.CI.IGT: warning " Patchwork
@ 2018-02-28 21:02 ` Ville Syrjälä
2018-02-28 21:17 ` Manasi Navare
7 siblings, 0 replies; 13+ messages in thread
From: Ville Syrjälä @ 2018-02-28 21:02 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Feb 27, 2018 at 12:59:11PM +0200, Jani Nikula wrote:
> Localize link rate arrays by moving them to the functions where they're
> used. Further clarify the distinction between source and sink
> capabilities. Split pre and post Haswell arrays, and get rid of the
> array size arithmetics. Use a direct rate value in the paranoia case of
> no common rates find.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 44 +++++++++++++++++++++++++----------------
> 1 file changed, 27 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 801a21b16004..6fa6583b16bd 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -96,15 +96,6 @@ static const struct dp_link_dpll chv_dpll[] = {
> { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
> };
>
> -static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
> - 324000, 432000, 540000 };
> -static const int skl_rates[] = { 162000, 216000, 270000,
> - 324000, 432000, 540000 };
> -static const int cnl_rates[] = { 162000, 216000, 270000,
> - 324000, 432000, 540000,
> - 648000, 810000 };
> -static const int default_rates[] = { 162000, 270000, 540000 };
> -
> /**
> * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
> * @intel_dp: DP struct
> @@ -144,14 +135,17 @@ static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> /* update sink rates from dpcd */
> static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
> {
> + static const int dp_rates[] = {
> + 162000, 270000, 540000
> + };
> int i, max_rate;
>
> max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
>
> - for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
> - if (default_rates[i] > max_rate)
> + for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
> + if (dp_rates[i] > max_rate)
> break;
> - intel_dp->sink_rates[i] = default_rates[i];
> + intel_dp->sink_rates[i] = dp_rates[i];
> }
>
> intel_dp->num_sink_rates = i;
> @@ -268,6 +262,22 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
> static void
> intel_dp_set_source_rates(struct intel_dp *intel_dp)
> {
> + /* The values must be in increasing order */
> + static const int cnl_rates[] = {
> + 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
> + };
> + static const int bxt_rates[] = {
> + 162000, 216000, 243000, 270000, 324000, 432000, 540000
> + };
> + static const int skl_rates[] = {
> + 162000, 216000, 270000, 324000, 432000, 540000
> + };
> + static const int hsw_rates[] = {
> + 162000, 270000, 540000
> + };
> + static const int g4x_rates[] = {
> + 162000, 270000
> + };
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> const struct ddi_vbt_port_info *info =
> @@ -290,11 +300,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> size = ARRAY_SIZE(skl_rates);
> } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
> IS_BROADWELL(dev_priv)) {
> - source_rates = default_rates;
> - size = ARRAY_SIZE(default_rates);
> + source_rates = hsw_rates;
> + size = ARRAY_SIZE(hsw_rates);
> } else {
> - source_rates = default_rates;
> - size = ARRAY_SIZE(default_rates) - 1;
> + source_rates = g4x_rates;
> + size = ARRAY_SIZE(g4x_rates);
> }
>
> if (max_rate && vbt_max_rate)
> @@ -356,7 +366,7 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
>
> /* Paranoia, there should always be something in common. */
> if (WARN_ON(intel_dp->num_common_rates == 0)) {
> - intel_dp->common_rates[0] = default_rates[0];
> + intel_dp->common_rates[0] = 162000;
> intel_dp->num_common_rates = 1;
> }
> }
> --
> 2.11.0
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [RFC] drm/i915/dp: move link rate arrays where they're used
2018-02-27 10:59 [RFC] drm/i915/dp: move link rate arrays where they're used Jani Nikula
` (6 preceding siblings ...)
2018-02-28 21:02 ` [RFC] " Ville Syrjälä
@ 2018-02-28 21:17 ` Manasi Navare
2018-02-28 21:23 ` Jani Nikula
7 siblings, 1 reply; 13+ messages in thread
From: Manasi Navare @ 2018-02-28 21:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Feb 27, 2018 at 12:59:11PM +0200, Jani Nikula wrote:
> Localize link rate arrays by moving them to the functions where they're
> used. Further clarify the distinction between source and sink
> capabilities. Split pre and post Haswell arrays, and get rid of the
> array size arithmetics. Use a direct rate value in the paranoia case of
> no common rates find.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
manasi
> ---
> drivers/gpu/drm/i915/intel_dp.c | 44 +++++++++++++++++++++++++----------------
> 1 file changed, 27 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 801a21b16004..6fa6583b16bd 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -96,15 +96,6 @@ static const struct dp_link_dpll chv_dpll[] = {
> { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
> };
>
> -static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
> - 324000, 432000, 540000 };
> -static const int skl_rates[] = { 162000, 216000, 270000,
> - 324000, 432000, 540000 };
> -static const int cnl_rates[] = { 162000, 216000, 270000,
> - 324000, 432000, 540000,
> - 648000, 810000 };
> -static const int default_rates[] = { 162000, 270000, 540000 };
> -
> /**
> * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
> * @intel_dp: DP struct
> @@ -144,14 +135,17 @@ static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> /* update sink rates from dpcd */
> static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
> {
> + static const int dp_rates[] = {
> + 162000, 270000, 540000
> + };
> int i, max_rate;
>
> max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
>
> - for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
> - if (default_rates[i] > max_rate)
> + for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
> + if (dp_rates[i] > max_rate)
> break;
> - intel_dp->sink_rates[i] = default_rates[i];
> + intel_dp->sink_rates[i] = dp_rates[i];
> }
>
> intel_dp->num_sink_rates = i;
> @@ -268,6 +262,22 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
> static void
> intel_dp_set_source_rates(struct intel_dp *intel_dp)
> {
> + /* The values must be in increasing order */
> + static const int cnl_rates[] = {
> + 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
> + };
> + static const int bxt_rates[] = {
> + 162000, 216000, 243000, 270000, 324000, 432000, 540000
> + };
> + static const int skl_rates[] = {
> + 162000, 216000, 270000, 324000, 432000, 540000
> + };
> + static const int hsw_rates[] = {
> + 162000, 270000, 540000
> + };
> + static const int g4x_rates[] = {
> + 162000, 270000
> + };
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> const struct ddi_vbt_port_info *info =
> @@ -290,11 +300,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> size = ARRAY_SIZE(skl_rates);
> } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
> IS_BROADWELL(dev_priv)) {
> - source_rates = default_rates;
> - size = ARRAY_SIZE(default_rates);
> + source_rates = hsw_rates;
> + size = ARRAY_SIZE(hsw_rates);
> } else {
> - source_rates = default_rates;
> - size = ARRAY_SIZE(default_rates) - 1;
> + source_rates = g4x_rates;
> + size = ARRAY_SIZE(g4x_rates);
> }
>
> if (max_rate && vbt_max_rate)
> @@ -356,7 +366,7 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
>
> /* Paranoia, there should always be something in common. */
> if (WARN_ON(intel_dp->num_common_rates == 0)) {
> - intel_dp->common_rates[0] = default_rates[0];
> + intel_dp->common_rates[0] = 162000;
> intel_dp->num_common_rates = 1;
> }
> }
> --
> 2.11.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [RFC] drm/i915/dp: move link rate arrays where they're used
2018-02-28 21:17 ` Manasi Navare
@ 2018-02-28 21:23 ` Jani Nikula
0 siblings, 0 replies; 13+ messages in thread
From: Jani Nikula @ 2018-02-28 21:23 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Wed, 28 Feb 2018, Manasi Navare <manasi.d.navare@intel.com> wrote:
> On Tue, Feb 27, 2018 at 12:59:11PM +0200, Jani Nikula wrote:
>> Localize link rate arrays by moving them to the functions where they're
>> used. Further clarify the distinction between source and sink
>> capabilities. Split pre and post Haswell arrays, and get rid of the
>> array size arithmetics. Use a direct rate value in the paranoia case of
>> no common rates find.
>>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Auch, I hit enter before I saw this. Pushed to dinq, thanks for the
reviews, and apologies for failing to record yours in the commit.
BR,
Jani.
>
> manasi
>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 44 +++++++++++++++++++++++++----------------
>> 1 file changed, 27 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 801a21b16004..6fa6583b16bd 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -96,15 +96,6 @@ static const struct dp_link_dpll chv_dpll[] = {
>> { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>> };
>>
>> -static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
>> - 324000, 432000, 540000 };
>> -static const int skl_rates[] = { 162000, 216000, 270000,
>> - 324000, 432000, 540000 };
>> -static const int cnl_rates[] = { 162000, 216000, 270000,
>> - 324000, 432000, 540000,
>> - 648000, 810000 };
>> -static const int default_rates[] = { 162000, 270000, 540000 };
>> -
>> /**
>> * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
>> * @intel_dp: DP struct
>> @@ -144,14 +135,17 @@ static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>> /* update sink rates from dpcd */
>> static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
>> {
>> + static const int dp_rates[] = {
>> + 162000, 270000, 540000
>> + };
>> int i, max_rate;
>>
>> max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
>>
>> - for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
>> - if (default_rates[i] > max_rate)
>> + for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
>> + if (dp_rates[i] > max_rate)
>> break;
>> - intel_dp->sink_rates[i] = default_rates[i];
>> + intel_dp->sink_rates[i] = dp_rates[i];
>> }
>>
>> intel_dp->num_sink_rates = i;
>> @@ -268,6 +262,22 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
>> static void
>> intel_dp_set_source_rates(struct intel_dp *intel_dp)
>> {
>> + /* The values must be in increasing order */
>> + static const int cnl_rates[] = {
>> + 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
>> + };
>> + static const int bxt_rates[] = {
>> + 162000, 216000, 243000, 270000, 324000, 432000, 540000
>> + };
>> + static const int skl_rates[] = {
>> + 162000, 216000, 270000, 324000, 432000, 540000
>> + };
>> + static const int hsw_rates[] = {
>> + 162000, 270000, 540000
>> + };
>> + static const int g4x_rates[] = {
>> + 162000, 270000
>> + };
>> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>> const struct ddi_vbt_port_info *info =
>> @@ -290,11 +300,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>> size = ARRAY_SIZE(skl_rates);
>> } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
>> IS_BROADWELL(dev_priv)) {
>> - source_rates = default_rates;
>> - size = ARRAY_SIZE(default_rates);
>> + source_rates = hsw_rates;
>> + size = ARRAY_SIZE(hsw_rates);
>> } else {
>> - source_rates = default_rates;
>> - size = ARRAY_SIZE(default_rates) - 1;
>> + source_rates = g4x_rates;
>> + size = ARRAY_SIZE(g4x_rates);
>> }
>>
>> if (max_rate && vbt_max_rate)
>> @@ -356,7 +366,7 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
>>
>> /* Paranoia, there should always be something in common. */
>> if (WARN_ON(intel_dp->num_common_rates == 0)) {
>> - intel_dp->common_rates[0] = default_rates[0];
>> + intel_dp->common_rates[0] = 162000;
>> intel_dp->num_common_rates = 1;
>> }
>> }
>> --
>> 2.11.0
>>
--
Jani Nikula, Intel Open Source Technology Center
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