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From: Manasi Navare <manasi.d.navare@intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/dp: Add HBR3 rate (8.1 Gbps) to default rates array
Date: Wed, 28 Feb 2018 09:16:17 -0800	[thread overview]
Message-ID: <20180228171617.GC2386@intel.com> (raw)
In-Reply-To: <87muztv60b.fsf@intel.com>

On Wed, Feb 28, 2018 at 11:05:24AM +0200, Jani Nikula wrote:
> On Tue, 27 Feb 2018, Manasi Navare <manasi.d.navare@intel.com> wrote:
> > default_rates[] array is a superset of all the link rates supported
> > by sink devices. DP 1.3 specification adds HBR3 (8.1Gbps) link rate
> > to the set of link rates supported by sink. This patch adds this rate
> > to default_rates[] array that gets used to populate the sink_rates[]
> > array limited by max rate obtained from DP_MAX_LINK_RATE DPCD register.
> >
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 2a3b3ae..f0766fb 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -103,7 +103,7 @@ static const int skl_rates[] = { 162000, 216000, 270000,
> >  static const int cnl_rates[] = { 162000, 216000, 270000,
> >  				 324000, 432000, 540000,
> >  				 648000, 810000 };
> > -static const int default_rates[] = { 162000, 270000, 540000 };
> > +static const int default_rates[] = { 162000, 270000, 540000, 810000 };
> 
> Now this is part of the reason I wanted to do [1], especially the part
> that switches to using hsw_rates and g4x_rates, instead of doing
> ARRAY_SIZE(default_rates) - 1. This innocent looking patch now "enables"
> HBR2 on g4x and HBR3 on hsw and bdw.
> 
> BR,
> Jani.
>

Oh yes I didnt realize that default rates are also getting used to populate
the source rates for HSW and g4x. Yes so localized or not, we definetly need to separate
out the hsw and g4x rates. and then we can add 810000 in the array and call it dp_rates
like your patch does.

I will try to combine your patch with this and resubmit.

Manasi
 
> 
> [1] http://patchwork.freedesktop.org/patch/msgid/20180227105911.4485-1-jani.nikula@intel.com
> 
> 
> >  
> >  /**
> >   * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
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  reply	other threads:[~2018-02-28 17:19 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-27 22:24 [PATCH] drm/i915/dp: Add HBR3 rate (8.1 Gbps) to default rates array Manasi Navare
2018-02-27 23:11 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-02-28  0:27 ` ✓ Fi.CI.IGT: " Patchwork
2018-02-28  9:05 ` [PATCH] " Jani Nikula
2018-02-28 17:16   ` Manasi Navare [this message]
2018-02-28 18:29     ` Jani Nikula

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