From mboxrd@z Thu Jan 1 00:00:00 1970 From: Benson Leung Subject: Re: [PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4 Date: Tue, 6 Mar 2018 11:21:47 -0800 Message-ID: <20180306192147.GB60955@decatoncale.mtv.corp.google.com> References: <1520029558-12219-1-git-send-email-matthew.s.atwood@intel.com> <1520361468-32087-1-git-send-email-matthew.s.atwood@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1627739332==" Return-path: In-Reply-To: <1520361468-32087-1-git-send-email-matthew.s.atwood@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: matthew.s.atwood@intel.com Cc: intel-gfx@lists.freedesktop.org, bleung@google.com, dri-devel@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1627739332== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="wq9mPyueHGvFACwf" Content-Disposition: inline --wq9mPyueHGvFACwf Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Matt, On Tue, Mar 06, 2018 at 10:37:48AM -0800, matthew.s.atwood@intel.com wrote: > From: Matt Atwood >=20 > DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheme from 8 > bits to 7 bits in DPCD 0x000e. The 8th bit describes a new feature, for > panels that use this new feature, this would cause a wait interval for > clock recovery of at least 512 ms, much higher then spec maximum of 16 ms. > This behavior is described in table 2-158 of DP 1.4 spec address 0000Eh. > To avoid breaking panels that are not spec compliant we now warn on > invalid values. >=20 > V2: commit title/message, masking all 7 bits, warn on out of spec values. >=20 > Signed-off-by: Matt Atwood Tested-by: Benson Leung Tested this patch on a DP 1.3 panel which sets the EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT bit in DPCD 0000Eh. It has a value of 0x80 in that field, indicating the extended caps, and 400us for the Main-Link Channel Equalization phase. Confirmed that link training passes normally where prior to this it would f= ail after the driver waits too long. Thanks for the fix! --=20 Benson Leung Staff Software Engineer Chrome OS Kernel Google Inc. bleung@google.com Chromium OS Project bleung@chromium.org --wq9mPyueHGvFACwf Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE6gYDF28Li+nEiKLaHwn1ewov5lgFAlqe6kgACgkQHwn1ewov 5liCdA/+MdNL1ercjwXbVcoH7uh9ya3hwBvyjv6cITlkDXWUlqgaJl+FVBChhv53 ZJ0djx9xF2P22KpbCRa4bocykaW48kVXNwgKytNXbm/7n027utdcLHqxqpM9+q8i 3URbfO2yq6g6B7EkfrOus5TIENXstrBL+OdiPTzXUoZNKuM4wa5NZMGNQY38Ag+7 ZvNkKetqj4lYXiG+tnhGKa+Wsvm45IJ9cfGgfDb2HhCb8kestSr3NCXK7VFAp7CA apt39yIE8QJLVUrz4MpZCfCmHzIB920ZhcfOOCLqqEsuK3UXYMuhzrD0ahuGgPdT uPJ/JhCgahDLb8bQkTGUI1mBIqb2CNYMoGdiRJAgVTX4Wk9Rgbfkh8KlG1OFh3LC iks7qbVU6LdfU7p7QG1H/T5XF/PfNg14CU7+jtZofQ47CkR0u9XtTOYv4E2ddJq0 JPf/y6qpSf/sPfXBEinG346+tL4QTVdDlGb/n0q0tbbkQXSfn5cHY2ChsoEJgyih h+sxAbGlv166ipM26t0FD3r/SyAyxdXuysRqQp1ar3qpFDJRwqQ3G62JeD4d8JTS 3uy6zOSfpVpf2tU8PYGbeDods7reznOinxWh+FcoKnkjG+QBP8Pyyrgap8rkPvVd 7Ym8ISwv1nqt3rFhJJx3cefkDGtcWIRyfYnw7bUWczbBtgq5vsc= =xkd3 -----END PGP SIGNATURE----- --wq9mPyueHGvFACwf-- --===============1627739332== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== --===============1627739332==--