From mboxrd@z Thu Jan 1 00:00:00 1970 From: Benson Leung Subject: Re: [PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4 Date: Wed, 7 Mar 2018 16:49:23 -0800 Message-ID: <20180308004923.GA154843@decatoncale.mtv.corp.google.com> References: <1520029558-12219-1-git-send-email-matthew.s.atwood@intel.com> <1520468931-11695-1-git-send-email-matthew.s.atwood@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2103575398==" Return-path: Received: from mail-io0-x235.google.com (mail-io0-x235.google.com [IPv6:2607:f8b0:4001:c06::235]) by gabe.freedesktop.org (Postfix) with ESMTPS id B26B26E760 for ; Thu, 8 Mar 2018 00:49:27 +0000 (UTC) Received: by mail-io0-x235.google.com with SMTP id b34so5161014ioj.6 for ; Wed, 07 Mar 2018 16:49:27 -0800 (PST) In-Reply-To: <1520468931-11695-1-git-send-email-matthew.s.atwood@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: matthew.s.atwood@intel.com Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============2103575398== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="u3/rZRmxL6MmkK24" Content-Disposition: inline --u3/rZRmxL6MmkK24 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Matt, On Wed, Mar 07, 2018 at 04:28:51PM -0800, matthew.s.atwood@intel.com wrote: > From: Matt Atwood >=20 > DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 > bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended > receiver capabilities. For panels that use this new feature wait interval > would be increased by 512 ms, when spec is max 16 ms. This behavior is > described in table 2-158 of DP 1.4 spec address 0000eh. >=20 > With the introduction of DP 1.4 spec main link clock recovery was > standardized to 100 us regardless of TRAINING_AUX_RD_INTERVAL value. >=20 > To avoid breaking panels that are not spec compiant we now warn on > invalid values. >=20 > V2: commit title/message, masking all 7 bits, warn on out of spec values. > V3: commit message, make link train clock recovery follow DP 1.4 spec. > V4: style changes > V5: typo >=20 > Signed-off-by: Matt Atwood Tested-by: Benson Leung V5 passes link training on that same panel from before with 8th bit set in DPCD 0x000e. =20 Thanks, Benson --=20 Benson Leung Staff Software Engineer Chrome OS Kernel Google Inc. bleung@google.com Chromium OS Project bleung@chromium.org --u3/rZRmxL6MmkK24 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE6gYDF28Li+nEiKLaHwn1ewov5lgFAlqgiJMACgkQHwn1ewov 5lhphQ//RqVrwZGzYPDOwi9E22d2cZySn4QniCooXLXBxpuAHdGI+l5KZUN5S0vd YoPILuiU9sCvvfTSMpz3SvEiYmjUAp7/95B2wZVeERq9jQ9MhIMZUMbcNbbcxH/B 2i4HHHa/P9T7UXvS9vBV7xYoTFm6DPQhCTykm961VH4gQcEyhzY7izeb5646ucbG 9yyeFLxAdW5WMokoOCOlqkQNbCydmNdhwwDhS2rIl8VBsPjFLN7q5lF83wyq1eN/ 8ccqjKjaVxESK6wsviY1baNoJodKZ1tV8UV9b3HGsJkjW4J4QVfbmsAzNw7u7FIW lz6/70piMq4Stz/KKGM/qWxCnUFyH0afQfWj6k54M3rPAzmL89ravZXM2FkHNi2T cQCkSQ8q2HffKzUrHMhU29DDms5Ee6xm1OIqywGnVsXC8jqJiYJUPUflxTJN8PN9 wdt/2xEkGzVIc4jtBw3EYD/ktdGHjsLnwyMQF4Ks3xgDhvpFnIEzwW+6hWvOB0dU VYlJE/rZnuiPkAkVu6GYCHr8NmLjwkOt2d7PDksbCxZWety3P1iblurhkHZ4gNt5 GOCWdZah9H4XhO8HJyJifaKFqyqNoEi3ZfVeU0vIlEgo6KTKnxPN4a6DtCv/BWO9 f0WULqiM0N6ZasNa4fHEILM+lzMpFTE0RfCGDS7etfrkMJZ2c6Y= =tAQ1 -----END PGP SIGNATURE----- --u3/rZRmxL6MmkK24-- --===============2103575398== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============2103575398==--