From mboxrd@z Thu Jan 1 00:00:00 1970 From: Benson Leung Subject: Re: [PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4 Date: Fri, 16 Mar 2018 20:34:56 -0700 Message-ID: <20180317033456.GA194067@decatoncale.mtv.corp.google.com> References: <1520029558-12219-1-git-send-email-matthew.s.atwood@intel.com> <1521148131-18560-1-git-send-email-matthew.s.atwood@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2139795946==" Return-path: Received: from mail-pg0-x229.google.com (mail-pg0-x229.google.com [IPv6:2607:f8b0:400e:c05::229]) by gabe.freedesktop.org (Postfix) with ESMTPS id AE2BC6E0BB for ; Sat, 17 Mar 2018 03:35:00 +0000 (UTC) Received: by mail-pg0-x229.google.com with SMTP id e9so4829159pgs.10 for ; Fri, 16 Mar 2018 20:35:00 -0700 (PDT) In-Reply-To: <1521148131-18560-1-git-send-email-matthew.s.atwood@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: matthew.s.atwood@intel.com Cc: intel-gfx@lists.freedesktop.org, bleung@google.com, dri-devel@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============2139795946== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="G4iJoqBmSsgzjUCe" Content-Disposition: inline --G4iJoqBmSsgzjUCe Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Mar 15, 2018 at 02:08:51PM -0700, matthew.s.atwood@intel.com wrote: > From: Matt Atwood >=20 > DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 > bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended > receiver capabilities. For panels that use this new feature wait interval > would be increased by 512 ms, when spec is max 16 ms. This behavior is > described in table 2-158 of DP 1.4 spec address 0000eh. >=20 > With the introduction of DP 1.4 spec main link clock recovery was > standardized to 100 us regardless of TRAINING_AUX_RD_INTERVAL value. >=20 > To avoid breaking panels that are not spec compiant we now warn on > invalid values. >=20 > V2: commit title/message, masking all 7 bits, warn on out of spec values. > V3: commit message, make link train clock recovery follow DP 1.4 spec. > V4: style changes > V5: typo > V6: print statement revisions, DP_REV to DPCD_REV, comment correction > V7: typo > V8: Style >=20 > Signed-off-by: Matt Atwood Tested-by: Benson Leung This version still passes link training on the panel with 8th bit set in DPCD 0x000e. Thanks, Benson --=20 Benson Leung Staff Software Engineer Chrome OS Kernel Google Inc. bleung@google.com Chromium OS Project bleung@chromium.org --G4iJoqBmSsgzjUCe Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE6gYDF28Li+nEiKLaHwn1ewov5lgFAlqsjOAACgkQHwn1ewov 5lgKQw//W2qNSI75hZjNeYoN4MUL4frEQN3lRqGwoF1zg/E6TM4ZHRrs0c3p9Fz8 EqYy/NwJ1wZodz8PtA/R1dcT99juIMbwlXfDkXSGw5YC/fkhDFmuKb/btVSCqZ8i qDFq1A6fpxgBZhFIghITUMxvNbjgsf3abn7ZpOx7CgAmUJrux+CNRDwlslr+Gq/d UL6c0GDY1sH6TlZWLySr2JnJCB64Mei8vdPSoyJcWn07ZxQGZZHnW6FCGW407kYQ zlAyiJUSPTIQFWTMd4CpVeZxb4j42tiIM6ag7hK4DV0UvncqSc7v8fmO5eto3RtC L2YxENj/Vw3AC5AvGzoIef7P90BPB/hCCqwdMpT5osKEUMdg8KqvvIBWWQPTPK03 1BeGsygjU/NzY9VfDQKrCvGbWTQ5DYmMcIsPktne+CGmXcWNaYkkLzrW16MjNdix AfDZa9PkBWWhlM4hH6e6la8OPswvkMbGEEoysOEWYFgDH/wyD92Yp1us1LNIk6Pp MzBbm70sq5/yQ+zStYLtOb574Sz/CMMWVkcOIR6/U5r3EjgVlqKR3SAiMRlPpBRf MaG8mZYQ4L5WXz/uyQbrQYAvqtZUDExwPIMD1UF91h9Dcd04AFiF74Zh0VCi8btx GOg+CFKi5TNu4md/dItiIRZwlX+5sqfNFfXzQJ31iCik6F9StPs= =cW2t -----END PGP SIGNATURE----- --G4iJoqBmSsgzjUCe-- --===============2139795946== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============2139795946==--