Re: [PATCH v2] drm/i915: set minimum CD clock to twice the BCLK.

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Fri, Apr 06, 2018 at 04:47:08PM +0300, Jani Nikula wrote:
> On Thu, 05 Apr 2018, Abhay Kumar <abhay.kumar@intel.com> wrote:
> > In glk when device boots with 1366x768 panel, HDA codec doesn't comeup.
> > This result in no audio forever as cdclk is < 96Mhz.
> > This chagne will ensure CD clock to be twice of  BCLK.
> 
> In short, we can't poke around CDCLK like this. It needs a full modeset,
> and it's non-trivial from the path you're calling this from.

I tried to cobble something together quickly:
git://github.com/vsyrjala/linux.git glk_cnl_cdclk_audio

Not tested at all, and I have no idea if my assumptions about
snd_hda_intel actually hold.

> 
> I'm considering pushing the original patch [1], because we haven't come
> up with working alternatives. Please confirm that the patch reliably
> fixes the issue.
> 
> (Though I think if you boot with *all* outputs disabled, we'll choose
> the lowest CDCLK possible regardless of the patch, reproducing the same
> issue.)
> 
> What's the CDCLK frequency set by the BIOS/GOP at boot? There are no
> logs with drm.debug=14 attached to the referenced bug.
> 
> I see that bspec says, "158.4 MHz CD (Display Audio enumeration and
> playback OK)" but that's *not* twice the BCLK. I'm inclined to lean
> towards 192 MHz min leading to max CDCLK on GLK.
> 
> BR,
> Jani.
> 
> 
> [1] https://patchwork.freedesktop.org/patch/184778/
> 
> 
> 
> >
> > v2:
> >     - Address comment (Jani)
> >     - New design approach
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102937
> > Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_audio.c | 33 ++++++++++++++++++++++-----------
> >  drivers/gpu/drm/i915/intel_cdclk.c | 21 +++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_drv.h   |  1 +
> >  3 files changed, 44 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> > index 709d6ca68074..f7dd3d532e93 100644
> > --- a/drivers/gpu/drm/i915/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > @@ -723,15 +723,37 @@ static void i915_audio_component_put_power(struct device *kdev)
> >  	intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
> >  }
> >  
> > +/* Get CDCLK in kHz  */
> > +static int i915_audio_component_get_cdclk_freq(struct device *kdev)
> > +{
> > +	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> > +
> > +	if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
> > +		return -ENODEV;
> > +
> > +	return dev_priv->cdclk.hw.cdclk;
> > +}
> > +
> >  static void i915_audio_component_codec_wake_override(struct device *kdev,
> >  						     bool enable)
> >  {
> >  	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> >  	u32 tmp;
> > +	int current_cdclk;
> >  
> >  	if (!IS_GEN9_BC(dev_priv))
> >  		return;
> >  
> > +	current_cdclk = i915_audio_component_get_cdclk_freq(kdev);
> > +
> > +	/*
> > +	 * Before probing for HDA Codec we need to make sure
> > +	 * "The CD clock frequency must be at least twice
> > +	 * the frequency of the Azalia BCLK."
> > +	 */
> > +	if (INTEL_GEN(dev_priv) >= 9 && current_cdclk <= 192000)
> > +		intel_cdclk_bump(dev_priv);
> > +
> >  	i915_audio_component_get_power(kdev);
> >  
> >  	/*
> > @@ -753,17 +775,6 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
> >  	i915_audio_component_put_power(kdev);
> >  }
> >  
> > -/* Get CDCLK in kHz  */
> > -static int i915_audio_component_get_cdclk_freq(struct device *kdev)
> > -{
> > -	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> > -
> > -	if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
> > -		return -ENODEV;
> > -
> > -	return dev_priv->cdclk.hw.cdclk;
> > -}
> > -
> >  /*
> >   * get the intel_encoder according to the parameter port and pipe
> >   * intel_encoder is saved by the index of pipe
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > index dc7db8a2caf8..9426e1b7badc 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1516,6 +1516,27 @@ void bxt_init_cdclk(struct drm_i915_private *dev_priv)
> >  }
> >  
> >  /**
> > + * intel_cdclk_bump - Increase cdclk to 2* BCLK
> > + * @dev_priv: i915 device
> > + *
> > + * Increase CDCLK for GKL and CNL. This is done only
> > + * during HDA codec probe.
> > + */
> > +void intel_cdclk_bump(struct drm_i915_private *dev_priv)
> > +{
> > +	struct intel_cdclk_state cdclk_state;
> > +
> > +	cdclk_state = dev_priv->cdclk.hw;
> > +
> > +	if (IS_GEMINILAKE(dev_priv)) {
> > +		cdclk_state.cdclk = glk_calc_cdclk((2*96000));
> > +		cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
> > +		cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
> > +		bxt_set_cdclk(dev_priv, &cdclk_state);
> > +	}
> > +}
> > +
> > +/**
> >   * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
> >   * @dev_priv: i915 device
> >   *
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index d1452fd2a58d..5192753df3dc 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1417,6 +1417,7 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> >  void cnl_init_cdclk(struct drm_i915_private *dev_priv);
> >  void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
> >  void bxt_init_cdclk(struct drm_i915_private *dev_priv);
> > +void intel_cdclk_bump(struct drm_i915_private *dev_priv);
> >  void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
> >  void icl_init_cdclk(struct drm_i915_private *dev_priv);
> >  void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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