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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH v2 3/9] drm/i915/psr: Remove intel_crtc_state parameter from disable()
Date: Thu, 19 Apr 2018 14:18:26 +0300	[thread overview]
Message-ID: <20180419111826.GB17795@intel.com> (raw)
In-Reply-To: <20180418224311.16577-3-jose.souza@intel.com>

On Wed, Apr 18, 2018 at 03:43:05PM -0700, José Roberto de Souza wrote:
> It is only used by VLV/CHV and we can get this information from
> intel_dp for those platforms.

But why? Abusing active_pipe (which is there just for the pps
tracking) is not a good idea IMO.

> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> 
> Changes from v1:
> - not using legacy drm_crtc pointer(struct drm_crtc *crtc = intel_dig_port->base.base.crtc)
> 
>  drivers/gpu/drm/i915/i915_drv.h  |  3 +--
>  drivers/gpu/drm/i915/intel_psr.c | 17 +++++++----------
>  2 files changed, 8 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 476bca872d48..f5ffb3d72cef 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -612,8 +612,7 @@ struct i915_psr {
>  
>  	void (*enable_source)(struct intel_dp *,
>  			      const struct intel_crtc_state *);
> -	void (*disable_source)(struct intel_dp *,
> -			       const struct intel_crtc_state *);
> +	void (*disable_source)(struct intel_dp *intel_dp);
>  	void (*enable_sink)(struct intel_dp *);
>  	void (*activate)(struct intel_dp *);
>  	void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index ebc47e2b08ca..934498505356 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -665,38 +665,35 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>  	mutex_unlock(&dev_priv->psr.lock);
>  }
>  
> -static void vlv_psr_disable(struct intel_dp *intel_dp,
> -			    const struct intel_crtc_state *old_crtc_state)
> +static void vlv_psr_disable(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
>  	uint32_t val;
>  
>  	if (dev_priv->psr.active) {
>  		/* Put VLV PSR back to PSR_state 0 (disabled). */
>  		if (intel_wait_for_register(dev_priv,
> -					    VLV_PSRSTAT(crtc->pipe),
> +					    VLV_PSRSTAT(intel_dp->active_pipe),
>  					    VLV_EDP_PSR_IN_TRANS,
>  					    0,
>  					    1))
>  			WARN(1, "PSR transition took longer than expected\n");
>  
> -		val = I915_READ(VLV_PSRCTL(crtc->pipe));
> +		val = I915_READ(VLV_PSRCTL(intel_dp->active_pipe));
>  		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
>  		val &= ~VLV_EDP_PSR_ENABLE;
>  		val &= ~VLV_EDP_PSR_MODE_MASK;
> -		I915_WRITE(VLV_PSRCTL(crtc->pipe), val);
> +		I915_WRITE(VLV_PSRCTL(intel_dp->active_pipe), val);
>  
>  		dev_priv->psr.active = false;
>  	} else {
> -		WARN_ON(vlv_is_psr_active_on_pipe(dev, crtc->pipe));
> +		WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_dp->active_pipe));
>  	}
>  }
>  
> -static void hsw_psr_disable(struct intel_dp *intel_dp,
> -			    const struct intel_crtc_state *old_crtc_state)
> +static void hsw_psr_disable(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
> @@ -765,7 +762,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
>  		return;
>  	}
>  
> -	dev_priv->psr.disable_source(intel_dp, old_crtc_state);
> +	dev_priv->psr.disable_source(intel_dp);
>  
>  	/* Disable PSR on Sink */
>  	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
> -- 
> 2.17.0

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2018-04-19 11:18 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-18 22:43 [PATCH v2 1/9] drm/i915/psr: Move specific HSW+ WARN_ON to HSW+ function José Roberto de Souza
2018-04-18 22:43 ` [PATCH v2 2/9] drm/i915/psr: Move PSR exit specific code to hardware specific function José Roberto de Souza
2018-05-16  0:42   ` Dhinakaran Pandiyan
2018-04-18 22:43 ` [PATCH v2 3/9] drm/i915/psr: Remove intel_crtc_state parameter from disable() José Roberto de Souza
2018-04-19 11:18   ` Ville Syrjälä [this message]
2018-04-18 22:43 ` [PATCH v2 4/9] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink José Roberto de Souza
2018-04-26 22:29   ` Dhinakaran Pandiyan
2018-04-30 23:02     ` Souza, Jose
2018-04-18 22:43 ` [PATCH v2 5/9] drm/i915/psr: Handle PSR RFB storage error José Roberto de Souza
2018-04-26 22:37   ` Dhinakaran Pandiyan
2018-04-30 23:28     ` Souza, Jose
2018-05-08 22:16       ` Dhinakaran Pandiyan
2018-04-18 22:43 ` [PATCH v2 6/9] drm/i915/psr/bdw+: Enable CRC check in the static frame on the sink side José Roberto de Souza
2018-04-20 21:16   ` Rodrigo Vivi
2018-04-25 21:02     ` Souza, Jose
2018-05-16  0:38   ` Dhinakaran Pandiyan
2018-04-18 22:43 ` [PATCH v2 7/9] drm/i915/dp: Move code to check if aux ch is busy to a function José Roberto de Souza
2018-04-26 22:51   ` Dhinakaran Pandiyan
2018-04-30 23:39     ` Souza, Jose
2018-05-08 21:29       ` Pandiyan, Dhinakaran
2018-04-18 22:43 ` [PATCH v2 8/9] drm/i915/dp: Improve intel_dp_aux_is_busy() José Roberto de Souza
2018-05-08 22:10   ` Dhinakaran Pandiyan
2018-04-18 22:43 ` [PATCH v2 9/9] drm/i915/dp: Avoid concurrent access when HW is using aux ch José Roberto de Souza
2018-04-18 22:48 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/9] drm/i915/psr: Move specific HSW+ WARN_ON to HSW+ function Patchwork
2018-04-18 22:51 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-04-18 23:09 ` ✓ Fi.CI.BAT: success " Patchwork
2018-04-19  0:53 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-04-26  0:41 ` [PATCH v2 1/9] " Dhinakaran Pandiyan
2018-04-30 22:54   ` Souza, Jose

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