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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Abhay Kumar <abhay.kumar@intel.com>
Cc: jani.nikula@intel.com, intel-gfx@lists.freedesktop.org,
	ville.syrjala@intel.com
Subject: Re: [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK
Date: Wed, 13 Jun 2018 15:27:52 +0300	[thread overview]
Message-ID: <20180613122752.GK23723@intel.com> (raw)
In-Reply-To: <1528840727-22160-1-git-send-email-abhay.kumar@intel.com>

On Tue, Jun 12, 2018 at 02:58:45PM -0700, Abhay Kumar wrote:
> Patches needed to change cdclk to 2*BCLK before accessing HDA Codec.
> 
> Ville Syrjälä (2):
>   drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
>   drm/i915: Shut off PW2 when changing cdclk on glk

Patchwork is probably totally confused by the threading here, so I
doubt you will get any testing report for this.

Also these two alone aren't sufficient. You'll need at least the
other two patches from the pw2 toggle branch.

> 
>  drivers/gpu/drm/i915/i915_drv.h         |  3 ++
>  drivers/gpu/drm/i915/i915_reg.h         |  4 ++
>  drivers/gpu/drm/i915/intel_audio.c      | 67 +++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_cdclk.c      | 43 +++++++++++----------
>  drivers/gpu/drm/i915/intel_display.c    |  7 +++-
>  drivers/gpu/drm/i915/intel_drv.h        |  7 ++++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 34 +++++++++++++++++
>  7 files changed, 140 insertions(+), 25 deletions(-)
> 
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2018-06-13 12:27 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
2018-04-30 10:27 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-04-30 10:28 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-04-30 10:43 ` ✓ Fi.CI.BAT: success " Patchwork
2018-04-30 13:01 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-04-30 18:22 ` [PATCH] " Du,Wenkai
2018-05-01  9:15   ` Saarinen, Jani
2018-05-01 23:42     ` Kumar, Abhay
2018-05-01 23:47       ` Kumar, Abhay
2018-05-02 15:12 ` Ville Syrjälä
2018-05-02 16:57   ` Kumar, Abhay
2018-05-02 17:14     ` Ville Syrjälä
2018-05-02 18:47       ` Kumar, Abhay
2018-05-10  1:25 ` [PATCH v2] " Abhay Kumar
2018-05-11 12:33   ` Ville Syrjälä
2018-05-11 22:04     ` Kumar, Abhay
2018-05-14  9:24       ` Jani Nikula
2018-06-12  7:17   ` [PATCH v3] " Abhay Kumar
2018-06-12 12:13     ` Ville Syrjälä
2018-06-12 16:27       ` Kumar, Abhay
2018-06-12 21:58     ` [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK Abhay Kumar
2018-06-12 21:58       ` [PATCH v4 1/2] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
2018-06-12 21:58       ` [PATCH v4 2/2] drm/i915: Shut off PW2 when changing cdclk on glk Abhay Kumar
2018-06-13 12:27       ` Ville Syrjälä [this message]
2018-05-10  1:54 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2) Patchwork
2018-05-10  1:55 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-10  2:14 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-10  4:35 ` ✓ Fi.CI.IGT: " Patchwork
2018-06-12  7:28 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3) Patchwork
2018-06-12  7:29 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-06-12  7:48 ` ✓ Fi.CI.BAT: success " Patchwork
2018-06-12  8:37 ` ✓ Fi.CI.IGT: " Patchwork
2018-06-12 18:09   ` Saarinen, Jani
2018-06-12 23:51     ` Kumar, Abhay

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