* [PATCH 01/24] drm/i915/icl: Extend AUX F interrupts to ICL
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-05-23 19:02 ` Srivatsa, Anusha
2018-05-22 0:25 ` [PATCH 02/24] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC Paulo Zanoni
` (39 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Paulo Zanoni
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
ICL has AUX F.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f9bc3aaa90d0..2fd92a886789 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2640,7 +2640,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
- if (IS_CNL_WITH_PORT_F(dev_priv))
+ if (IS_CNL_WITH_PORT_F(dev_priv) ||
+ INTEL_GEN(dev_priv) >= 11)
tmp_mask |= CNL_AUX_CHANNEL_F;
if (iir & tmp_mask) {
@@ -3920,7 +3921,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
}
- if (IS_CNL_WITH_PORT_F(dev_priv))
+ if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11)
de_port_masked |= CNL_AUX_CHANNEL_F;
de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 01/24] drm/i915/icl: Extend AUX F interrupts to ICL
2018-05-22 0:25 ` [PATCH 01/24] drm/i915/icl: Extend AUX F interrupts to ICL Paulo Zanoni
@ 2018-05-23 19:02 ` Srivatsa, Anusha
0 siblings, 0 replies; 127+ messages in thread
From: Srivatsa, Anusha @ 2018-05-23 19:02 UTC (permalink / raw)
To: Zanoni, Paulo R, intel-gfx@lists.freedesktop.org; +Cc: Pandiyan, Dhinakaran
>-----Original Message-----
>From: Zanoni, Paulo R
>Sent: Monday, May 21, 2018 5:26 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>; Zanoni, Paulo R
><paulo.r.zanoni@intel.com>; Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Subject: [PATCH 01/24] drm/i915/icl: Extend AUX F interrupts to ICL
>
>From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>
>ICL has AUX F.
>
>Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Looks good.
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/i915_irq.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index f9bc3aaa90d0..2fd92a886789 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -2640,7 +2640,8 @@ gen8_de_irq_handler(struct drm_i915_private
>*dev_priv, u32 master_ctl)
> GEN9_AUX_CHANNEL_C |
> GEN9_AUX_CHANNEL_D;
>
>- if (IS_CNL_WITH_PORT_F(dev_priv))
>+ if (IS_CNL_WITH_PORT_F(dev_priv) ||
>+ INTEL_GEN(dev_priv) >= 11)
> tmp_mask |= CNL_AUX_CHANNEL_F;
>
> if (iir & tmp_mask) {
>@@ -3920,7 +3921,7 @@ static void gen8_de_irq_postinstall(struct
>drm_i915_private *dev_priv)
> de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> }
>
>- if (IS_CNL_WITH_PORT_F(dev_priv))
>+ if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11)
> de_port_masked |= CNL_AUX_CHANNEL_F;
>
> de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>--
>2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 02/24] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
2018-05-22 0:25 ` [PATCH 01/24] drm/i915/icl: Extend AUX F interrupts to ICL Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-05-24 9:22 ` Mika Kuoppala
2018-05-22 0:25 ` [PATCH 03/24] drm/i915/icl: introduce tc_port Paulo Zanoni
` (38 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Paulo Zanoni
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
The Graphics System Event(GSE) interrupt bit has a new location in the
GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the only
DE_MISC interrupt that was enabled, with this change we don't enable/handle
any of DE_MISC interrupts for gen11. Credits to Paulo for pointing out
the register change.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
[Paulo: bikesheds and rebases]
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 38 ++++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
2 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2fd92a886789..dde938bbfb0a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2605,7 +2605,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
I915_WRITE(GEN8_DE_MISC_IIR, iir);
ret = IRQ_HANDLED;
- if (iir & GEN8_DE_MISC_GSE) {
+ if (INTEL_GEN(dev_priv) <= 10 &&
+ (iir & GEN8_DE_MISC_GSE)) {
intel_opregion_asle_intr(dev_priv);
found = true;
}
@@ -2943,6 +2944,30 @@ gen11_gt_irq_handler(struct drm_i915_private * const i915,
spin_unlock(&i915->irq_lock);
}
+static irqreturn_t
+gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
+{
+ irqreturn_t ret = IRQ_NONE;
+ u32 iir;
+
+ if (!(master_ctl & GEN11_GU_MISC_IRQ))
+ return ret;
+
+ iir = I915_READ(GEN11_GU_MISC_IIR);
+ if (iir) {
+ I915_WRITE(GEN11_GU_MISC_IIR, iir);
+ ret = IRQ_HANDLED;
+ if (iir & GEN11_GU_MISC_GSE)
+ intel_opregion_asle_intr(dev_priv);
+ else
+ DRM_ERROR("Unexpected GU Misc interrupt 0x%08x\n", iir);
+ } else {
+ DRM_ERROR("The master control interrupt lied (GU MISC)!\n");
+ }
+
+ return ret;
+}
+
static irqreturn_t gen11_irq_handler(int irq, void *arg)
{
struct drm_i915_private * const i915 = to_i915(arg);
@@ -2976,6 +3001,8 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
enable_rpm_wakeref_asserts(i915);
}
+ gen11_gu_misc_irq_handler(i915, master_ctl);
+
/* Acknowledge and enable interrupts. */
raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
@@ -3465,6 +3492,7 @@ static void gen11_irq_reset(struct drm_device *dev)
GEN3_IRQ_RESET(GEN8_DE_PORT_);
GEN3_IRQ_RESET(GEN8_DE_MISC_);
+ GEN3_IRQ_RESET(GEN11_GU_MISC_);
GEN3_IRQ_RESET(GEN8_PCU_);
}
@@ -3908,9 +3936,12 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
uint32_t de_pipe_enables;
u32 de_port_masked = GEN8_AUX_CHANNEL_A;
u32 de_port_enables;
- u32 de_misc_masked = GEN8_DE_MISC_GSE | GEN8_DE_EDP_PSR;
+ u32 de_misc_masked = GEN8_DE_EDP_PSR;
enum pipe pipe;
+ if (INTEL_GEN(dev_priv) <= 10)
+ de_misc_masked |= GEN8_DE_MISC_GSE;
+
if (INTEL_GEN(dev_priv) >= 9) {
de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
@@ -4004,10 +4035,13 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
static int gen11_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 gu_misc_masked = GEN11_GU_MISC_GSE;
gen11_gt_irq_postinstall(dev_priv);
gen8_de_irq_postinstall(dev_priv);
+ GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+
I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 196a0eb79272..ca474f6f523c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7016,9 +7016,16 @@ enum {
#define GEN8_PCU_IIR _MMIO(0x444e8)
#define GEN8_PCU_IER _MMIO(0x444ec)
+#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
+#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
+#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
+#define GEN11_GU_MISC_IER _MMIO(0x444fc)
+#define GEN11_GU_MISC_GSE (1 << 27)
+
#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
#define GEN11_MASTER_IRQ (1 << 31)
#define GEN11_PCU_IRQ (1 << 30)
+#define GEN11_GU_MISC_IRQ (1 << 29)
#define GEN11_DISPLAY_IRQ (1 << 16)
#define GEN11_GT_DW_IRQ(x) (1 << (x))
#define GEN11_GT_DW1_IRQ (1 << 1)
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 02/24] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
2018-05-22 0:25 ` [PATCH 02/24] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC Paulo Zanoni
@ 2018-05-24 9:22 ` Mika Kuoppala
2018-05-24 22:51 ` Dhinakaran Pandiyan
0 siblings, 1 reply; 127+ messages in thread
From: Mika Kuoppala @ 2018-05-24 9:22 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Paulo Zanoni
Paulo Zanoni <paulo.r.zanoni@intel.com> writes:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>
> The Graphics System Event(GSE) interrupt bit has a new location in the
> GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the only
> DE_MISC interrupt that was enabled, with this change we don't enable/handle
> any of DE_MISC interrupts for gen11. Credits to Paulo for pointing out
> the register change.
>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> [Paulo: bikesheds and rebases]
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 38 ++++++++++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> 2 files changed, 43 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2fd92a886789..dde938bbfb0a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2605,7 +2605,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> I915_WRITE(GEN8_DE_MISC_IIR, iir);
> ret = IRQ_HANDLED;
>
> - if (iir & GEN8_DE_MISC_GSE) {
> + if (INTEL_GEN(dev_priv) <= 10 &&
> + (iir & GEN8_DE_MISC_GSE)) {
This bit should not be ever set with gen11 so no need to
add extra guards?
> intel_opregion_asle_intr(dev_priv);
> found = true;
> }
> @@ -2943,6 +2944,30 @@ gen11_gt_irq_handler(struct drm_i915_private * const i915,
> spin_unlock(&i915->irq_lock);
> }
>
> +static irqreturn_t
Return is never used for anything, just use void.
> +gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> +{
> + irqreturn_t ret = IRQ_NONE;
> + u32 iir;
> +
> + if (!(master_ctl & GEN11_GU_MISC_IRQ))
> + return ret;
> +
> + iir = I915_READ(GEN11_GU_MISC_IIR);
This reg seems to out of forcewake domain so
just use raw_reg_read() in here.
> + if (iir) {
just a note that likely(iir) if you want to add emphasis.
> + I915_WRITE(GEN11_GU_MISC_IIR, iir);
raw_reg_write()
-Mika
> + ret = IRQ_HANDLED;
> + if (iir & GEN11_GU_MISC_GSE)
> + intel_opregion_asle_intr(dev_priv);
> + else
> + DRM_ERROR("Unexpected GU Misc interrupt 0x%08x\n", iir);
> + } else {
> + DRM_ERROR("The master control interrupt lied (GU MISC)!\n");
> + }
> +
> + return ret;
> +}
> +
> static irqreturn_t gen11_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private * const i915 = to_i915(arg);
> @@ -2976,6 +3001,8 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
> enable_rpm_wakeref_asserts(i915);
> }
>
> + gen11_gu_misc_irq_handler(i915, master_ctl);
> +
> /* Acknowledge and enable interrupts. */
> raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
>
> @@ -3465,6 +3492,7 @@ static void gen11_irq_reset(struct drm_device *dev)
>
> GEN3_IRQ_RESET(GEN8_DE_PORT_);
> GEN3_IRQ_RESET(GEN8_DE_MISC_);
> + GEN3_IRQ_RESET(GEN11_GU_MISC_);
> GEN3_IRQ_RESET(GEN8_PCU_);
> }
>
> @@ -3908,9 +3936,12 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> uint32_t de_pipe_enables;
> u32 de_port_masked = GEN8_AUX_CHANNEL_A;
> u32 de_port_enables;
> - u32 de_misc_masked = GEN8_DE_MISC_GSE | GEN8_DE_EDP_PSR;
> + u32 de_misc_masked = GEN8_DE_EDP_PSR;
> enum pipe pipe;
>
> + if (INTEL_GEN(dev_priv) <= 10)
> + de_misc_masked |= GEN8_DE_MISC_GSE;
> +
> if (INTEL_GEN(dev_priv) >= 9) {
> de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
> @@ -4004,10 +4035,13 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
> static int gen11_irq_postinstall(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 gu_misc_masked = GEN11_GU_MISC_GSE;
>
> gen11_gt_irq_postinstall(dev_priv);
> gen8_de_irq_postinstall(dev_priv);
>
> + GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
> +
> I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
>
> I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 196a0eb79272..ca474f6f523c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7016,9 +7016,16 @@ enum {
> #define GEN8_PCU_IIR _MMIO(0x444e8)
> #define GEN8_PCU_IER _MMIO(0x444ec)
>
> +#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
> +#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
> +#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
> +#define GEN11_GU_MISC_IER _MMIO(0x444fc)
> +#define GEN11_GU_MISC_GSE (1 << 27)
> +
> #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
> #define GEN11_MASTER_IRQ (1 << 31)
> #define GEN11_PCU_IRQ (1 << 30)
> +#define GEN11_GU_MISC_IRQ (1 << 29)
> #define GEN11_DISPLAY_IRQ (1 << 16)
> #define GEN11_GT_DW_IRQ(x) (1 << (x))
> #define GEN11_GT_DW1_IRQ (1 << 1)
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 02/24] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
2018-05-24 9:22 ` Mika Kuoppala
@ 2018-05-24 22:51 ` Dhinakaran Pandiyan
2018-05-25 12:00 ` Mika Kuoppala
0 siblings, 1 reply; 127+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-24 22:51 UTC (permalink / raw)
To: Mika Kuoppala, Paulo Zanoni, intel-gfx
On Thu, 2018-05-24 at 12:22 +0300, Mika Kuoppala wrote:
> Paulo Zanoni <paulo.r.zanoni@intel.com> writes:
>
> >
> > From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> >
> > The Graphics System Event(GSE) interrupt bit has a new location in
> > the
> > GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the
> > only
> > DE_MISC interrupt that was enabled, with this change we don't
> > enable/handle
> > any of DE_MISC interrupts for gen11. Credits to Paulo for pointing
> > out
> > the register change.
> >
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > [Paulo: bikesheds and rebases]
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 38
> > ++++++++++++++++++++++++++++++++++++--
> > drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> > 2 files changed, 43 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 2fd92a886789..dde938bbfb0a 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2605,7 +2605,8 @@ gen8_de_irq_handler(struct drm_i915_private
> > *dev_priv, u32 master_ctl)
> > I915_WRITE(GEN8_DE_MISC_IIR, iir);
> > ret = IRQ_HANDLED;
> >
> > - if (iir & GEN8_DE_MISC_GSE) {
> > + if (INTEL_GEN(dev_priv) <= 10 &&
> > + (iir & GEN8_DE_MISC_GSE)) {
> This bit should not be ever set with gen11 so no need to
> add extra guards?
The bit is reserved on gen-11, we can't be sure if some future platform
is not going to reuse it for something else.The guard also adds clarity
that the gen-11 handler is elsewhere.
>
> >
> > intel_opregion_asle_intr(dev_priv)
> > ;
> > found = true;
> > }
> > @@ -2943,6 +2944,30 @@ gen11_gt_irq_handler(struct drm_i915_private
> > * const i915,
> > spin_unlock(&i915->irq_lock);
> > }
> >
> > +static irqreturn_t
> Return is never used for anything, just use void.
Looks like the caller was reworked upstream, I'll change this.
>
> >
> > +gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, u32
> > master_ctl)
> > +{
> > + irqreturn_t ret = IRQ_NONE;
> > + u32 iir;
> > +
> > + if (!(master_ctl & GEN11_GU_MISC_IRQ))
> > + return ret;
> > +
> > + iir = I915_READ(GEN11_GU_MISC_IIR);
> This reg seems to out of forcewake domain so
> just use raw_reg_read() in here.
How do you check that? And what exactly is the forcewake domain? Is it
similar to a power domain?
>
> >
> > + if (iir) {
> just a note that likely(iir) if you want to add emphasis.
>
> >
> > + I915_WRITE(GEN11_GU_MISC_IIR, iir);
> raw_reg_write()
> -Mika
>
> >
> > + ret = IRQ_HANDLED;
> > + if (iir & GEN11_GU_MISC_GSE)
> > + intel_opregion_asle_intr(dev_priv);
> > + else
> > + DRM_ERROR("Unexpected GU Misc interrupt
> > 0x%08x\n", iir);
> > + } else {
> > + DRM_ERROR("The master control interrupt lied (GU
> > MISC)!\n");
> > + }
> > +
> > + return ret;
> > +}
> > +
> > static irqreturn_t gen11_irq_handler(int irq, void *arg)
> > {
> > struct drm_i915_private * const i915 = to_i915(arg);
> > @@ -2976,6 +3001,8 @@ static irqreturn_t gen11_irq_handler(int irq,
> > void *arg)
> > enable_rpm_wakeref_asserts(i915);
> > }
> >
> > + gen11_gu_misc_irq_handler(i915, master_ctl);
> > +
> > /* Acknowledge and enable interrupts. */
> > raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ |
> > master_ctl);
> >
> > @@ -3465,6 +3492,7 @@ static void gen11_irq_reset(struct drm_device
> > *dev)
> >
> > GEN3_IRQ_RESET(GEN8_DE_PORT_);
> > GEN3_IRQ_RESET(GEN8_DE_MISC_);
> > + GEN3_IRQ_RESET(GEN11_GU_MISC_);
> > GEN3_IRQ_RESET(GEN8_PCU_);
> > }
> >
> > @@ -3908,9 +3936,12 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > uint32_t de_pipe_enables;
> > u32 de_port_masked = GEN8_AUX_CHANNEL_A;
> > u32 de_port_enables;
> > - u32 de_misc_masked = GEN8_DE_MISC_GSE | GEN8_DE_EDP_PSR;
> > + u32 de_misc_masked = GEN8_DE_EDP_PSR;
> > enum pipe pipe;
> >
> > + if (INTEL_GEN(dev_priv) <= 10)
> > + de_misc_masked |= GEN8_DE_MISC_GSE;
> > +
> > if (INTEL_GEN(dev_priv) >= 9) {
> > de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> > de_port_masked |= GEN9_AUX_CHANNEL_B |
> > GEN9_AUX_CHANNEL_C |
> > @@ -4004,10 +4035,13 @@ static void gen11_gt_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > static int gen11_irq_postinstall(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > + u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> >
> > gen11_gt_irq_postinstall(dev_priv);
> > gen8_de_irq_postinstall(dev_priv);
> >
> > + GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked,
> > gu_misc_masked);
> > +
> > I915_WRITE(GEN11_DISPLAY_INT_CTL,
> > GEN11_DISPLAY_IRQ_ENABLE);
> >
> > I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 196a0eb79272..ca474f6f523c 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7016,9 +7016,16 @@ enum {
> > #define GEN8_PCU_IIR _MMIO(0x444e8)
> > #define GEN8_PCU_IER _MMIO(0x444ec)
> >
> > +#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
> > +#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
> > +#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
> > +#define GEN11_GU_MISC_IER _MMIO(0x444fc)
> > +#define GEN11_GU_MISC_GSE (1 << 27)
> > +
> > #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
> > #define GEN11_MASTER_IRQ (1 << 31)
> > #define GEN11_PCU_IRQ (1 << 30)
> > +#define GEN11_GU_MISC_IRQ (1 << 29)
> > #define GEN11_DISPLAY_IRQ (1 << 16)
> > #define GEN11_GT_DW_IRQ(x) (1 << (x))
> > #define GEN11_GT_DW1_IRQ (1 << 1)
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^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 02/24] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
2018-05-24 22:51 ` Dhinakaran Pandiyan
@ 2018-05-25 12:00 ` Mika Kuoppala
2018-05-25 19:43 ` [PATCH v2] " Dhinakaran Pandiyan
0 siblings, 1 reply; 127+ messages in thread
From: Mika Kuoppala @ 2018-05-25 12:00 UTC (permalink / raw)
To: dhinakaran.pandiyan, Paulo Zanoni, intel-gfx
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> writes:
> On Thu, 2018-05-24 at 12:22 +0300, Mika Kuoppala wrote:
>> Paulo Zanoni <paulo.r.zanoni@intel.com> writes:
>>
>> >
>> > From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> >
>> > The Graphics System Event(GSE) interrupt bit has a new location in
>> > the
>> > GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the
>> > only
>> > DE_MISC interrupt that was enabled, with this change we don't
>> > enable/handle
>> > any of DE_MISC interrupts for gen11. Credits to Paulo for pointing
>> > out
>> > the register change.
>> >
>> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> > [Paulo: bikesheds and rebases]
>> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/i915_irq.c | 38
>> > ++++++++++++++++++++++++++++++++++++--
>> > drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
>> > 2 files changed, 43 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
>> > b/drivers/gpu/drm/i915/i915_irq.c
>> > index 2fd92a886789..dde938bbfb0a 100644
>> > --- a/drivers/gpu/drm/i915/i915_irq.c
>> > +++ b/drivers/gpu/drm/i915/i915_irq.c
>> > @@ -2605,7 +2605,8 @@ gen8_de_irq_handler(struct drm_i915_private
>> > *dev_priv, u32 master_ctl)
>> > I915_WRITE(GEN8_DE_MISC_IIR, iir);
>> > ret = IRQ_HANDLED;
>> >
>> > - if (iir & GEN8_DE_MISC_GSE) {
>> > + if (INTEL_GEN(dev_priv) <= 10 &&
>> > + (iir & GEN8_DE_MISC_GSE)) {
>> This bit should not be ever set with gen11 so no need to
>> add extra guards?
> The bit is reserved on gen-11, we can't be sure if some future platform
> is not going to reuse it for something else.The guard also adds clarity
> that the gen-11 handler is elsewhere.
It adds latency to interrupt handler too. We already mask that specific
interrupt so guarding against collision would be the responsibility
of that future platform enabling patchset.
>
>>
>> >
>> > intel_opregion_asle_intr(dev_priv)
>> > ;
>> > found = true;
>> > }
>> > @@ -2943,6 +2944,30 @@ gen11_gt_irq_handler(struct drm_i915_private
>> > * const i915,
>> > spin_unlock(&i915->irq_lock);
>> > }
>> >
>> > +static irqreturn_t
>> Return is never used for anything, just use void.
> Looks like the caller was reworked upstream, I'll change this.
>
>>
>> >
>> > +gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, u32
>> > master_ctl)
>> > +{
>> > + irqreturn_t ret = IRQ_NONE;
>> > + u32 iir;
>> > +
>> > + if (!(master_ctl & GEN11_GU_MISC_IRQ))
>> > + return ret;
>> > +
>> > + iir = I915_READ(GEN11_GU_MISC_IIR);
>> This reg seems to out of forcewake domain so
>> just use raw_reg_read() in here.
> How do you check that? And what exactly is the forcewake domain? Is it
> similar to a power domain?
>
from intel_uncore.c:
static const struct intel_forcewake_range __gen11_fw_ranges[] = {
..
GEN_FW_RANGE(0x40000, 0x1bffff, 0),
...
So using I915_READ will work as it will that it doesn't need
forcewake dance. But the checks add latency, not much, but this
is interrupt handler after all so we do care.
forcewake domains are per engine power saving feature where you need
to do certain dance to wake the domain up and also to let it sleep.
For more details skim through intel_uncore.[hc].
-Mika
>>
>> >
>> > + if (iir) {
>> just a note that likely(iir) if you want to add emphasis.
>>
>> >
>> > + I915_WRITE(GEN11_GU_MISC_IIR, iir);
>> raw_reg_write()
>> -Mika
>>
>> >
>> > + ret = IRQ_HANDLED;
>> > + if (iir & GEN11_GU_MISC_GSE)
>> > + intel_opregion_asle_intr(dev_priv);
>> > + else
>> > + DRM_ERROR("Unexpected GU Misc interrupt
>> > 0x%08x\n", iir);
>> > + } else {
>> > + DRM_ERROR("The master control interrupt lied (GU
>> > MISC)!\n");
>> > + }
>> > +
>> > + return ret;
>> > +}
>> > +
>> > static irqreturn_t gen11_irq_handler(int irq, void *arg)
>> > {
>> > struct drm_i915_private * const i915 = to_i915(arg);
>> > @@ -2976,6 +3001,8 @@ static irqreturn_t gen11_irq_handler(int irq,
>> > void *arg)
>> > enable_rpm_wakeref_asserts(i915);
>> > }
>> >
>> > + gen11_gu_misc_irq_handler(i915, master_ctl);
>> > +
>> > /* Acknowledge and enable interrupts. */
>> > raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ |
>> > master_ctl);
>> >
>> > @@ -3465,6 +3492,7 @@ static void gen11_irq_reset(struct drm_device
>> > *dev)
>> >
>> > GEN3_IRQ_RESET(GEN8_DE_PORT_);
>> > GEN3_IRQ_RESET(GEN8_DE_MISC_);
>> > + GEN3_IRQ_RESET(GEN11_GU_MISC_);
>> > GEN3_IRQ_RESET(GEN8_PCU_);
>> > }
>> >
>> > @@ -3908,9 +3936,12 @@ static void gen8_de_irq_postinstall(struct
>> > drm_i915_private *dev_priv)
>> > uint32_t de_pipe_enables;
>> > u32 de_port_masked = GEN8_AUX_CHANNEL_A;
>> > u32 de_port_enables;
>> > - u32 de_misc_masked = GEN8_DE_MISC_GSE | GEN8_DE_EDP_PSR;
>> > + u32 de_misc_masked = GEN8_DE_EDP_PSR;
>> > enum pipe pipe;
>> >
>> > + if (INTEL_GEN(dev_priv) <= 10)
>> > + de_misc_masked |= GEN8_DE_MISC_GSE;
>> > +
>> > if (INTEL_GEN(dev_priv) >= 9) {
>> > de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
>> > de_port_masked |= GEN9_AUX_CHANNEL_B |
>> > GEN9_AUX_CHANNEL_C |
>> > @@ -4004,10 +4035,13 @@ static void gen11_gt_irq_postinstall(struct
>> > drm_i915_private *dev_priv)
>> > static int gen11_irq_postinstall(struct drm_device *dev)
>> > {
>> > struct drm_i915_private *dev_priv = dev->dev_private;
>> > + u32 gu_misc_masked = GEN11_GU_MISC_GSE;
>> >
>> > gen11_gt_irq_postinstall(dev_priv);
>> > gen8_de_irq_postinstall(dev_priv);
>> >
>> > + GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked,
>> > gu_misc_masked);
>> > +
>> > I915_WRITE(GEN11_DISPLAY_INT_CTL,
>> > GEN11_DISPLAY_IRQ_ENABLE);
>> >
>> > I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > b/drivers/gpu/drm/i915/i915_reg.h
>> > index 196a0eb79272..ca474f6f523c 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -7016,9 +7016,16 @@ enum {
>> > #define GEN8_PCU_IIR _MMIO(0x444e8)
>> > #define GEN8_PCU_IER _MMIO(0x444ec)
>> >
>> > +#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
>> > +#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
>> > +#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
>> > +#define GEN11_GU_MISC_IER _MMIO(0x444fc)
>> > +#define GEN11_GU_MISC_GSE (1 << 27)
>> > +
>> > #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
>> > #define GEN11_MASTER_IRQ (1 << 31)
>> > #define GEN11_PCU_IRQ (1 << 30)
>> > +#define GEN11_GU_MISC_IRQ (1 << 29)
>> > #define GEN11_DISPLAY_IRQ (1 << 16)
>> > #define GEN11_GT_DW_IRQ(x) (1 << (x))
>> > #define GEN11_GT_DW1_IRQ (1 << 1)
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^ permalink raw reply [flat|nested] 127+ messages in thread* [PATCH v2] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
2018-05-25 12:00 ` Mika Kuoppala
@ 2018-05-25 19:43 ` Dhinakaran Pandiyan
2018-05-25 19:56 ` Chris Wilson
0 siblings, 1 reply; 127+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-25 19:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Paulo Zanoni
The Graphics System Event(GSE) interrupt bit has a new location in the
GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the only
DE_MISC interrupt that was enabled, with this change we don't enable/handle
any of DE_MISC interrupts for gen11. Credits to Paulo for pointing out
the register change.
v2: from DK
raw_reg_[read/write], branch prediction hint and drop platform check (Mika)
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
[Paulo: bikesheds and rebases]
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 31 ++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2fd92a886789..cdbc23b21df6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2943,6 +2943,26 @@ gen11_gt_irq_handler(struct drm_i915_private * const i915,
spin_unlock(&i915->irq_lock);
}
+static void
+gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv,
+ const u32 master_ctl)
+{
+ void __iomem * const regs = dev_priv->regs;
+ u32 iir;
+
+ if (!(master_ctl & GEN11_GU_MISC_IRQ))
+ return;
+
+ iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
+ if (likely(iir)) {
+ raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
+ if (iir & GEN11_GU_MISC_GSE)
+ intel_opregion_asle_intr(dev_priv);
+ else
+ DRM_ERROR("Unexpected GU Misc interrupt 0x%08x\n", iir);
+ }
+}
+
static irqreturn_t gen11_irq_handler(int irq, void *arg)
{
struct drm_i915_private * const i915 = to_i915(arg);
@@ -2976,6 +2996,8 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
enable_rpm_wakeref_asserts(i915);
}
+ gen11_gu_misc_irq_handler(i915, master_ctl);
+
/* Acknowledge and enable interrupts. */
raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
@@ -3465,6 +3487,7 @@ static void gen11_irq_reset(struct drm_device *dev)
GEN3_IRQ_RESET(GEN8_DE_PORT_);
GEN3_IRQ_RESET(GEN8_DE_MISC_);
+ GEN3_IRQ_RESET(GEN11_GU_MISC_);
GEN3_IRQ_RESET(GEN8_PCU_);
}
@@ -3908,9 +3931,12 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
uint32_t de_pipe_enables;
u32 de_port_masked = GEN8_AUX_CHANNEL_A;
u32 de_port_enables;
- u32 de_misc_masked = GEN8_DE_MISC_GSE | GEN8_DE_EDP_PSR;
+ u32 de_misc_masked = GEN8_DE_EDP_PSR;
enum pipe pipe;
+ if (INTEL_GEN(dev_priv) <= 10)
+ de_misc_masked |= GEN8_DE_MISC_GSE;
+
if (INTEL_GEN(dev_priv) >= 9) {
de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
@@ -4004,10 +4030,13 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
static int gen11_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 gu_misc_masked = GEN11_GU_MISC_GSE;
gen11_gt_irq_postinstall(dev_priv);
gen8_de_irq_postinstall(dev_priv);
+ GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+
I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6953419881c4..67d392c3ca2c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7025,9 +7025,16 @@ enum {
#define GEN8_PCU_IIR _MMIO(0x444e8)
#define GEN8_PCU_IER _MMIO(0x444ec)
+#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
+#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
+#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
+#define GEN11_GU_MISC_IER _MMIO(0x444fc)
+#define GEN11_GU_MISC_GSE (1 << 27)
+
#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
#define GEN11_MASTER_IRQ (1 << 31)
#define GEN11_PCU_IRQ (1 << 30)
+#define GEN11_GU_MISC_IRQ (1 << 29)
#define GEN11_DISPLAY_IRQ (1 << 16)
#define GEN11_GT_DW_IRQ(x) (1 << (x))
#define GEN11_GT_DW1_IRQ (1 << 1)
--
2.14.1
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^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH v2] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
2018-05-25 19:43 ` [PATCH v2] " Dhinakaran Pandiyan
@ 2018-05-25 19:56 ` Chris Wilson
2018-06-14 1:51 ` Dhinakaran Pandiyan
2018-06-14 19:54 ` [PATCH v3] " Dhinakaran Pandiyan
0 siblings, 2 replies; 127+ messages in thread
From: Chris Wilson @ 2018-05-25 19:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Paulo Zanoni
Quoting Dhinakaran Pandiyan (2018-05-25 20:43:13)
> The Graphics System Event(GSE) interrupt bit has a new location in the
> GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the only
> DE_MISC interrupt that was enabled, with this change we don't enable/handle
> any of DE_MISC interrupts for gen11. Credits to Paulo for pointing out
> the register change.
>
> v2: from DK
> raw_reg_[read/write], branch prediction hint and drop platform check (Mika)
>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> [Paulo: bikesheds and rebases]
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 31 ++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> 2 files changed, 37 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2fd92a886789..cdbc23b21df6 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2943,6 +2943,26 @@ gen11_gt_irq_handler(struct drm_i915_private * const i915,
> spin_unlock(&i915->irq_lock);
> }
>
> +static void
> +gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv,
> + const u32 master_ctl)
> +{
> + void __iomem * const regs = dev_priv->regs;
> + u32 iir;
> +
> + if (!(master_ctl & GEN11_GU_MISC_IRQ))
> + return;
> +
> + iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
> + if (likely(iir)) {
> + raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
> + if (iir & GEN11_GU_MISC_GSE)
> + intel_opregion_asle_intr(dev_priv);
> + else
> + DRM_ERROR("Unexpected GU Misc interrupt 0x%08x\n", iir);
You should be re-enabling the master interrupt *before* doing any work.
No?
Keeping the master interrupt disabled stops all other CPUs from
processing our interrupts; e.g. basically stopping us feeding the GPU
with work while we wait for you.
-Chris
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^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH v2] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
2018-05-25 19:56 ` Chris Wilson
@ 2018-06-14 1:51 ` Dhinakaran Pandiyan
2018-06-14 10:32 ` Ville Syrjälä
2018-06-14 19:54 ` [PATCH v3] " Dhinakaran Pandiyan
1 sibling, 1 reply; 127+ messages in thread
From: Dhinakaran Pandiyan @ 2018-06-14 1:51 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Paulo Zanoni
On Fri, 2018-05-25 at 20:56 +0100, Chris Wilson wrote:
> Quoting Dhinakaran Pandiyan (2018-05-25 20:43:13)
> >
> > The Graphics System Event(GSE) interrupt bit has a new location in
> > the
> > GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the
> > only
> > DE_MISC interrupt that was enabled, with this change we don't
> > enable/handle
> > any of DE_MISC interrupts for gen11. Credits to Paulo for pointing
> > out
> > the register change.
> >
> > v2: from DK
> > raw_reg_[read/write], branch prediction hint and drop platform
> > check (Mika)
> >
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > [Paulo: bikesheds and rebases]
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 31
> > ++++++++++++++++++++++++++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> > 2 files changed, 37 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 2fd92a886789..cdbc23b21df6 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2943,6 +2943,26 @@ gen11_gt_irq_handler(struct drm_i915_private
> > * const i915,
> > spin_unlock(&i915->irq_lock);
> > }
> >
> > +static void
> > +gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv,
> > + const u32 master_ctl)
> > +{
> > + void __iomem * const regs = dev_priv->regs;
> > + u32 iir;
> > +
> > + if (!(master_ctl & GEN11_GU_MISC_IRQ))
> > + return;
> > +
> > + iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
> > + if (likely(iir)) {
> > + raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
> > + if (iir & GEN11_GU_MISC_GSE)
> > + intel_opregion_asle_intr(dev_priv);
> > + else
> > + DRM_ERROR("Unexpected GU Misc interrupt
> > 0x%08x\n", iir);
> You should be re-enabling the master interrupt *before* doing any
> work.
> No?
intel_opregion_asle_intr() doesn't do much other than scheduling work
and this is similar to how interrupts are handled for other platforms.
Are you suggesting we optimize our interrupt handling logic to read all
the required IIR's first, re-enable the master interrupt and then call
the specific handlers based on the set IIR's? This would be a
widespread change.
>
> Keeping the master interrupt disabled stops all other CPUs from
> processing our interrupts; e.g. basically stopping us feeding the GPU
> with work while we wait for you.
> -Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH v2] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
2018-06-14 1:51 ` Dhinakaran Pandiyan
@ 2018-06-14 10:32 ` Ville Syrjälä
2018-06-14 20:21 ` Dhinakaran Pandiyan
0 siblings, 1 reply; 127+ messages in thread
From: Ville Syrjälä @ 2018-06-14 10:32 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx, Paulo Zanoni
On Wed, Jun 13, 2018 at 06:51:37PM -0700, Dhinakaran Pandiyan wrote:
> On Fri, 2018-05-25 at 20:56 +0100, Chris Wilson wrote:
> > Quoting Dhinakaran Pandiyan (2018-05-25 20:43:13)
> > >
> > > The Graphics System Event(GSE) interrupt bit has a new location in
> > > the
> > > GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the
> > > only
> > > DE_MISC interrupt that was enabled, with this change we don't
> > > enable/handle
> > > any of DE_MISC interrupts for gen11. Credits to Paulo for pointing
> > > out
> > > the register change.
> > >
> > > v2: from DK
> > > raw_reg_[read/write], branch prediction hint and drop platform
> > > check (Mika)
> > >
> > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > [Paulo: bikesheds and rebases]
> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 31
> > > ++++++++++++++++++++++++++++++-
> > > drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> > > 2 files changed, 37 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 2fd92a886789..cdbc23b21df6 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -2943,6 +2943,26 @@ gen11_gt_irq_handler(struct drm_i915_private
> > > * const i915,
> > > spin_unlock(&i915->irq_lock);
> > > }
> > >
> > > +static void
> > > +gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv,
> > > + const u32 master_ctl)
> > > +{
> > > + void __iomem * const regs = dev_priv->regs;
> > > + u32 iir;
> > > +
> > > + if (!(master_ctl & GEN11_GU_MISC_IRQ))
> > > + return;
> > > +
> > > + iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
> > > + if (likely(iir)) {
> > > + raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
> > > + if (iir & GEN11_GU_MISC_GSE)
> > > + intel_opregion_asle_intr(dev_priv);
> > > + else
> > > + DRM_ERROR("Unexpected GU Misc interrupt
> > > 0x%08x\n", iir);
> > You should be re-enabling the master interrupt *before* doing any
> > work.
> > No?
> intel_opregion_asle_intr() doesn't do much other than scheduling work
> and this is similar to how interrupts are handled for other platforms.
>
> Are you suggesting we optimize our interrupt handling logic to read all
> the required IIR's first, re-enable the master interrupt and then call
> the specific handlers based on the set IIR's? This would be a
> widespread change.
That is what I have done for all the gmch platforms. The gen8+ gt
irq handler is already split up as well because chv needed it.
I think it's the right way to do things. I just didn't have the
energy at the time to convert all the more moden platforms as well.
It would also open up the possibility of using threaded irqs and
keeping some of the super latency sensitive stuff in the hard irq
handler while moving everthing else into the thread.
>
> >
> > Keeping the master interrupt disabled stops all other CPUs from
> > processing our interrupts; e.g. basically stopping us feeding the GPU
> > with work while we wait for you.
> > -Chris
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH v2] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
2018-06-14 10:32 ` Ville Syrjälä
@ 2018-06-14 20:21 ` Dhinakaran Pandiyan
0 siblings, 0 replies; 127+ messages in thread
From: Dhinakaran Pandiyan @ 2018-06-14 20:21 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Paulo Zanoni
On Thu, 2018-06-14 at 13:32 +0300, Ville Syrjälä wrote:
> On Wed, Jun 13, 2018 at 06:51:37PM -0700, Dhinakaran Pandiyan wrote:
> >
> > On Fri, 2018-05-25 at 20:56 +0100, Chris Wilson wrote:
> > >
> > > Quoting Dhinakaran Pandiyan (2018-05-25 20:43:13)
> > > >
> > > >
> > > > The Graphics System Event(GSE) interrupt bit has a new location
> > > > in
> > > > the
> > > > GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was
> > > > the
> > > > only
> > > > DE_MISC interrupt that was enabled, with this change we don't
> > > > enable/handle
> > > > any of DE_MISC interrupts for gen11. Credits to Paulo for
> > > > pointing
> > > > out
> > > > the register change.
> > > >
> > > > v2: from DK
> > > > raw_reg_[read/write], branch prediction hint and drop platform
> > > > check (Mika)
> > > >
> > > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.c
> > > > om>
> > > > [Paulo: bikesheds and rebases]
> > > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/i915_irq.c | 31
> > > > ++++++++++++++++++++++++++++++-
> > > > drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> > > > 2 files changed, 37 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > index 2fd92a886789..cdbc23b21df6 100644
> > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > @@ -2943,6 +2943,26 @@ gen11_gt_irq_handler(struct
> > > > drm_i915_private
> > > > * const i915,
> > > > spin_unlock(&i915->irq_lock);
> > > > }
> > > >
> > > > +static void
> > > > +gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv,
> > > > + const u32 master_ctl)
> > > > +{
> > > > + void __iomem * const regs = dev_priv->regs;
> > > > + u32 iir;
> > > > +
> > > > + if (!(master_ctl & GEN11_GU_MISC_IRQ))
> > > > + return;
> > > > +
> > > > + iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
> > > > + if (likely(iir)) {
> > > > + raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
> > > > + if (iir & GEN11_GU_MISC_GSE)
> > > > + intel_opregion_asle_intr(dev_priv);
> > > > + else
> > > > + DRM_ERROR("Unexpected GU Misc interrupt
> > > > 0x%08x\n", iir);
> > > You should be re-enabling the master interrupt *before* doing any
> > > work.
> > > No?
> > intel_opregion_asle_intr() doesn't do much other than scheduling
> > work
> > and this is similar to how interrupts are handled for other
> > platforms.
> >
> > Are you suggesting we optimize our interrupt handling logic to read
> > all
> > the required IIR's first, re-enable the master interrupt and then
> > call
> > the specific handlers based on the set IIR's? This would be a
> > widespread change.
> That is what I have done for all the gmch platforms. The gen8+ gt
> irq handler is already split up as well because chv needed it.
> I think it's the right way to do things. I just didn't have the
> energy at the time to convert all the more moden platforms as well.
Makes a lot of sense.I have converted this particular patch for now.
-DK
>
> It would also open up the possibility of using threaded irqs and
> keeping some of the super latency sensitive stuff in the hard irq
> handler while moving everthing else into the thread.
>
> >
> >
> > >
> > >
> > > Keeping the master interrupt disabled stops all other CPUs from
> > > processing our interrupts; e.g. basically stopping us feeding the
> > > GPU
> > > with work while we wait for you.
> > > -Chris
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH v3] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
2018-05-25 19:56 ` Chris Wilson
2018-06-14 1:51 ` Dhinakaran Pandiyan
@ 2018-06-14 19:54 ` Dhinakaran Pandiyan
2018-06-15 23:18 ` Paulo Zanoni
1 sibling, 1 reply; 127+ messages in thread
From: Dhinakaran Pandiyan @ 2018-06-14 19:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Dhinakaran Pandiyan
The Graphics System Event(GSE) interrupt bit has a new location in the
GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the only
DE_MISC interrupt that was enabled, with this change we don't enable/handle
any of DE_MISC interrupts for gen11. Credits to Paulo for pointing out
the register change.
v2: from DK
raw_reg_[read/write], branch prediction hint and drop platform check (Mika)
v3: From DK
Early re-enable of master interrupt (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
[Paulo: bikesheds and rebases]
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 46 ++++++++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
2 files changed, 52 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c52060a35317..c7bd6caa98ea 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2946,11 +2946,44 @@ gen11_gt_irq_handler(struct drm_i915_private * const i915,
spin_unlock(&i915->irq_lock);
}
+static void
+gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32 master_ctl,
+ u32 *iir)
+{
+ void __iomem * const regs = dev_priv->regs;
+
+ if (!(master_ctl & GEN11_GU_MISC_IRQ))
+ return;
+
+ *iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
+ if (likely(*iir))
+ raw_reg_write(regs, GEN11_GU_MISC_IIR, *iir);
+}
+
+static void
+gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv,
+ const u32 master_ctl, const u32 iir)
+{
+ if (!(master_ctl & GEN11_GU_MISC_IRQ))
+ return;
+
+ if (unlikely(!iir)) {
+ DRM_ERROR("GU_MISC iir blank!\n");
+ return;
+ }
+
+ if (iir & GEN11_GU_MISC_GSE)
+ intel_opregion_asle_intr(dev_priv);
+ else
+ DRM_ERROR("Unexpected GU_MISC interrupt 0x%x\n", iir);
+}
+
static irqreturn_t gen11_irq_handler(int irq, void *arg)
{
struct drm_i915_private * const i915 = to_i915(arg);
void __iomem * const regs = i915->regs;
u32 master_ctl;
+ u32 gu_misc_iir;
if (!intel_irqs_enabled(i915))
return IRQ_NONE;
@@ -2979,9 +3012,13 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
enable_rpm_wakeref_asserts(i915);
}
+ gen11_gu_misc_irq_ack(i915, master_ctl, &gu_misc_iir);
+
/* Acknowledge and enable interrupts. */
raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
+ gen11_gu_misc_irq_handler(i915, master_ctl, gu_misc_iir);
+
return IRQ_HANDLED;
}
@@ -3468,6 +3505,7 @@ static void gen11_irq_reset(struct drm_device *dev)
GEN3_IRQ_RESET(GEN8_DE_PORT_);
GEN3_IRQ_RESET(GEN8_DE_MISC_);
+ GEN3_IRQ_RESET(GEN11_GU_MISC_);
GEN3_IRQ_RESET(GEN8_PCU_);
}
@@ -3911,9 +3949,12 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
uint32_t de_pipe_enables;
u32 de_port_masked = GEN8_AUX_CHANNEL_A;
u32 de_port_enables;
- u32 de_misc_masked = GEN8_DE_MISC_GSE | GEN8_DE_EDP_PSR;
+ u32 de_misc_masked = GEN8_DE_EDP_PSR;
enum pipe pipe;
+ if (INTEL_GEN(dev_priv) <= 10)
+ de_misc_masked |= GEN8_DE_MISC_GSE;
+
if (INTEL_GEN(dev_priv) >= 9) {
de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
@@ -4010,10 +4051,13 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
static int gen11_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 gu_misc_masked = GEN11_GU_MISC_GSE;
gen11_gt_irq_postinstall(dev_priv);
gen8_de_irq_postinstall(dev_priv);
+ GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+
I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 140f6a27d696..e4aebccf4461 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7053,9 +7053,16 @@ enum {
#define GEN8_PCU_IIR _MMIO(0x444e8)
#define GEN8_PCU_IER _MMIO(0x444ec)
+#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
+#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
+#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
+#define GEN11_GU_MISC_IER _MMIO(0x444fc)
+#define GEN11_GU_MISC_GSE (1 << 27)
+
#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
#define GEN11_MASTER_IRQ (1 << 31)
#define GEN11_PCU_IRQ (1 << 30)
+#define GEN11_GU_MISC_IRQ (1 << 29)
#define GEN11_DISPLAY_IRQ (1 << 16)
#define GEN11_GT_DW_IRQ(x) (1 << (x))
#define GEN11_GT_DW1_IRQ (1 << 1)
--
2.14.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH v3] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
2018-06-14 19:54 ` [PATCH v3] " Dhinakaran Pandiyan
@ 2018-06-15 23:18 ` Paulo Zanoni
0 siblings, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-06-15 23:18 UTC (permalink / raw)
To: Dhinakaran Pandiyan, intel-gfx
Em Qui, 2018-06-14 às 12:54 -0700, Dhinakaran Pandiyan escreveu:
> The Graphics System Event(GSE) interrupt bit has a new location in
> the
> GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the
> only
> DE_MISC interrupt that was enabled, with this change we don't
> enable/handle
> any of DE_MISC interrupts for gen11. Credits to Paulo for pointing
> out
> the register change.
>
> v2: from DK
> raw_reg_[read/write], branch prediction hint and drop platform check
> (Mika)
>
> v3: From DK
> Early re-enable of master interrupt (Chris)
Looks like all the requests have been implemented:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> [Paulo: bikesheds and rebases]
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 46
> ++++++++++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> 2 files changed, 52 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index c52060a35317..c7bd6caa98ea 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2946,11 +2946,44 @@ gen11_gt_irq_handler(struct drm_i915_private
> * const i915,
> spin_unlock(&i915->irq_lock);
> }
>
> +static void
> +gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32
> master_ctl,
> + u32 *iir)
> +{
> + void __iomem * const regs = dev_priv->regs;
> +
> + if (!(master_ctl & GEN11_GU_MISC_IRQ))
> + return;
> +
> + *iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
> + if (likely(*iir))
> + raw_reg_write(regs, GEN11_GU_MISC_IIR, *iir);
> +}
> +
> +static void
> +gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv,
> + const u32 master_ctl, const u32 iir)
> +{
> + if (!(master_ctl & GEN11_GU_MISC_IRQ))
> + return;
> +
> + if (unlikely(!iir)) {
> + DRM_ERROR("GU_MISC iir blank!\n");
> + return;
> + }
> +
> + if (iir & GEN11_GU_MISC_GSE)
> + intel_opregion_asle_intr(dev_priv);
> + else
> + DRM_ERROR("Unexpected GU_MISC interrupt 0x%x\n",
> iir);
> +}
> +
> static irqreturn_t gen11_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private * const i915 = to_i915(arg);
> void __iomem * const regs = i915->regs;
> u32 master_ctl;
> + u32 gu_misc_iir;
>
> if (!intel_irqs_enabled(i915))
> return IRQ_NONE;
> @@ -2979,9 +3012,13 @@ static irqreturn_t gen11_irq_handler(int irq,
> void *arg)
> enable_rpm_wakeref_asserts(i915);
> }
>
> + gen11_gu_misc_irq_ack(i915, master_ctl, &gu_misc_iir);
> +
> /* Acknowledge and enable interrupts. */
> raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ |
> master_ctl);
>
> + gen11_gu_misc_irq_handler(i915, master_ctl, gu_misc_iir);
> +
> return IRQ_HANDLED;
> }
>
> @@ -3468,6 +3505,7 @@ static void gen11_irq_reset(struct drm_device
> *dev)
>
> GEN3_IRQ_RESET(GEN8_DE_PORT_);
> GEN3_IRQ_RESET(GEN8_DE_MISC_);
> + GEN3_IRQ_RESET(GEN11_GU_MISC_);
> GEN3_IRQ_RESET(GEN8_PCU_);
> }
>
> @@ -3911,9 +3949,12 @@ static void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
> uint32_t de_pipe_enables;
> u32 de_port_masked = GEN8_AUX_CHANNEL_A;
> u32 de_port_enables;
> - u32 de_misc_masked = GEN8_DE_MISC_GSE | GEN8_DE_EDP_PSR;
> + u32 de_misc_masked = GEN8_DE_EDP_PSR;
> enum pipe pipe;
>
> + if (INTEL_GEN(dev_priv) <= 10)
> + de_misc_masked |= GEN8_DE_MISC_GSE;
> +
> if (INTEL_GEN(dev_priv) >= 9) {
> de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> de_port_masked |= GEN9_AUX_CHANNEL_B |
> GEN9_AUX_CHANNEL_C |
> @@ -4010,10 +4051,13 @@ static void gen11_gt_irq_postinstall(struct
> drm_i915_private *dev_priv)
> static int gen11_irq_postinstall(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 gu_misc_masked = GEN11_GU_MISC_GSE;
>
> gen11_gt_irq_postinstall(dev_priv);
> gen8_de_irq_postinstall(dev_priv);
>
> + GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked,
> gu_misc_masked);
> +
> I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
>
> I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 140f6a27d696..e4aebccf4461 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7053,9 +7053,16 @@ enum {
> #define GEN8_PCU_IIR _MMIO(0x444e8)
> #define GEN8_PCU_IER _MMIO(0x444ec)
>
> +#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
> +#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
> +#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
> +#define GEN11_GU_MISC_IER _MMIO(0x444fc)
> +#define GEN11_GU_MISC_GSE (1 << 27)
> +
> #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
> #define GEN11_MASTER_IRQ (1 << 31)
> #define GEN11_PCU_IRQ (1 << 30)
> +#define GEN11_GU_MISC_IRQ (1 << 29)
> #define GEN11_DISPLAY_IRQ (1 << 16)
> #define GEN11_GT_DW_IRQ(x) (1 << (x))
> #define GEN11_GT_DW1_IRQ (1 << 1)
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 03/24] drm/i915/icl: introduce tc_port
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
2018-05-22 0:25 ` [PATCH 01/24] drm/i915/icl: Extend AUX F interrupts to ICL Paulo Zanoni
2018-05-22 0:25 ` [PATCH 02/24] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-05-22 6:13 ` Kumar, Mahesh
2018-05-22 0:25 ` [PATCH 04/24] drm/i915/icl: Support for TC North Display interrupts Paulo Zanoni
` (37 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Dhinakaran Pandiyan
Add and enum for TC ports and auxiliary functions to handle them.
Icelake brings a lot of registers and other things that only apply to
the TC ports and are indexed starting from 0, so having an enum for
tc_ports that starts at 0 really helps the indexing.
This patch is based on previous patches written by Dhinakaran Pandiyan
and Mahesh Kumar.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/intel_display.h | 11 +++++++++++
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c9ec88acad9c..64593b0fbebd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5807,6 +5807,22 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
I915_WRITE(BCLRPAT(crtc->pipe), 0);
}
+bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
+{
+ if (IS_ICELAKE(dev_priv))
+ return port >= PORT_C && port <= PORT_F;
+
+ return false;
+}
+
+enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
+{
+ if (!intel_port_is_tc(dev_priv, port))
+ return PORT_TC_NONE;
+
+ return port - PORT_C;
+}
+
enum intel_display_power_domain intel_port_to_power_domain(enum port port)
{
switch (port) {
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 2ef31617614a..c88185ed7594 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -126,6 +126,17 @@ enum port {
#define port_name(p) ((p) + 'A')
+enum tc_port {
+ PORT_TC_NONE = -1,
+
+ PORT_TC1 = 0,
+ PORT_TC2,
+ PORT_TC3,
+ PORT_TC4,
+
+ I915_MAX_TC_PORTS
+};
+
enum dpio_channel {
DPIO_CH0,
DPIO_CH1
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 22af249393a4..a54232c270e1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1493,6 +1493,9 @@ void intel_connector_attach_encoder(struct intel_connector *connector,
struct intel_encoder *encoder);
struct drm_display_mode *
intel_encoder_current_mode(struct intel_encoder *encoder);
+bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
+enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
+ enum port port);
enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
--
2.14.3
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^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 03/24] drm/i915/icl: introduce tc_port
2018-05-22 0:25 ` [PATCH 03/24] drm/i915/icl: introduce tc_port Paulo Zanoni
@ 2018-05-22 6:13 ` Kumar, Mahesh
0 siblings, 0 replies; 127+ messages in thread
From: Kumar, Mahesh @ 2018-05-22 6:13 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: Dhinakaran Pandiyan
Reviewed-by: Mahesh Kumar <mahesh1.kumar@intel.com>
On 5/22/2018 5:55 AM, Paulo Zanoni wrote:
> Add and enum for TC ports and auxiliary functions to handle them.
> Icelake brings a lot of registers and other things that only apply to
> the TC ports and are indexed starting from 0, so having an enum for
> tc_ports that starts at 0 really helps the indexing.
>
> This patch is based on previous patches written by Dhinakaran Pandiyan
> and Mahesh Kumar.
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 16 ++++++++++++++++
> drivers/gpu/drm/i915/intel_display.h | 11 +++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 3 +++
> 3 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c9ec88acad9c..64593b0fbebd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5807,6 +5807,22 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
> I915_WRITE(BCLRPAT(crtc->pipe), 0);
> }
>
> +bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
> +{
> + if (IS_ICELAKE(dev_priv))
> + return port >= PORT_C && port <= PORT_F;
> +
> + return false;
> +}
> +
> +enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
> +{
> + if (!intel_port_is_tc(dev_priv, port))
> + return PORT_TC_NONE;
> +
> + return port - PORT_C;
> +}
> +
> enum intel_display_power_domain intel_port_to_power_domain(enum port port)
> {
> switch (port) {
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index 2ef31617614a..c88185ed7594 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -126,6 +126,17 @@ enum port {
>
> #define port_name(p) ((p) + 'A')
>
> +enum tc_port {
> + PORT_TC_NONE = -1,
> +
> + PORT_TC1 = 0,
> + PORT_TC2,
> + PORT_TC3,
> + PORT_TC4,
> +
> + I915_MAX_TC_PORTS
> +};
> +
> enum dpio_channel {
> DPIO_CH0,
> DPIO_CH1
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 22af249393a4..a54232c270e1 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1493,6 +1493,9 @@ void intel_connector_attach_encoder(struct intel_connector *connector,
> struct intel_encoder *encoder);
> struct drm_display_mode *
> intel_encoder_current_mode(struct intel_encoder *encoder);
> +bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
> +enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> + enum port port);
>
> enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 04/24] drm/i915/icl: Support for TC North Display interrupts
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (2 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 03/24] drm/i915/icl: introduce tc_port Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-06-13 22:20 ` Lucas De Marchi
2018-05-22 0:25 ` [PATCH 05/24] drm/i915/icp: Add Interrupt Support Paulo Zanoni
` (36 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Dhinakaran Pandiyan, Paulo Zanoni
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
The hotplug interrupts for the ports can be routed to either North
Display or South Display depending on the output mode. DP Alternate or
DP over TBT outputs will have hotplug interrupts routed to the North
Display while interrupts for legacy modes will be routed to the South
Display in PCH. This patch adds hotplug interrupt handling support for
DP Alternate mode.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
[Paulo: coding style changes]
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 95 +++++++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++
2 files changed, 112 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dde938bbfb0a..9bcec5fdb9d0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -115,6 +115,13 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
};
+static const u32 hpd_tc_gen11[HPD_NUM_PINS] = {
+ [HPD_PORT_C] = GEN11_TC1_HOTPLUG,
+ [HPD_PORT_D] = GEN11_TC2_HOTPLUG,
+ [HPD_PORT_E] = GEN11_TC3_HOTPLUG,
+ [HPD_PORT_F] = GEN11_TC4_HOTPLUG
+};
+
/* IIR can theoretically queue up two events. Be paranoid. */
#define GEN8_IRQ_RESET_NDX(type, which) do { \
I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
@@ -1549,6 +1556,22 @@ static void gen8_gt_irq_handler(struct drm_i915_private *i915,
}
}
+static bool gen11_port_hotplug_long_detect(enum port port, u32 val)
+{
+ switch (port) {
+ case PORT_C:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
+ case PORT_D:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
+ case PORT_E:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
+ case PORT_F:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
+ default:
+ return false;
+ }
+}
+
static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
{
switch (port) {
@@ -2590,6 +2613,25 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
}
+static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
+{
+ u32 pin_mask = 0, long_mask = 0;
+ u32 trigger_tc, dig_hotplug_reg;
+
+ trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
+ if (trigger_tc) {
+ dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
+ I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
+
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
+ dig_hotplug_reg, hpd_tc_gen11,
+ gen11_port_hotplug_long_detect);
+ intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
+ } else {
+ DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir);
+ }
+}
+
static irqreturn_t
gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
{
@@ -2626,6 +2668,17 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
}
+ if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
+ iir = I915_READ(GEN11_DE_HPD_IIR);
+ if (iir) {
+ I915_WRITE(GEN11_DE_HPD_IIR, iir);
+ ret = IRQ_HANDLED;
+ gen11_hpd_irq_handler(dev_priv, iir);
+ } else {
+ DRM_ERROR("The master control interrupt lied, (DE HPD)!\n");
+ }
+ }
+
if (master_ctl & GEN8_DE_PORT_IRQ) {
iir = I915_READ(GEN8_DE_PORT_IIR);
if (iir) {
@@ -3492,6 +3545,7 @@ static void gen11_irq_reset(struct drm_device *dev)
GEN3_IRQ_RESET(GEN8_DE_PORT_);
GEN3_IRQ_RESET(GEN8_DE_MISC_);
+ GEN3_IRQ_RESET(GEN11_DE_HPD_);
GEN3_IRQ_RESET(GEN11_GU_MISC_);
GEN3_IRQ_RESET(GEN8_PCU_);
}
@@ -3610,6 +3664,34 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
ibx_hpd_detection_setup(dev_priv);
}
+static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
+{
+ u32 hotplug;
+
+ hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
+ hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
+ I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
+}
+
+static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+ u32 hotplug_irqs, enabled_irqs;
+ u32 val;
+
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_tc_gen11);
+ hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK;
+
+ val = I915_READ(GEN11_DE_HPD_IMR);
+ val &= ~hotplug_irqs;
+ I915_WRITE(GEN11_DE_HPD_IMR, val);
+ POSTING_READ(GEN11_DE_HPD_IMR);
+
+ gen11_hpd_detection_setup(dev_priv);
+}
+
static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 val, hotplug;
@@ -3980,10 +4062,17 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
- if (IS_GEN9_LP(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11) {
+ u32 de_hpd_masked = 0;
+ u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK;
+
+ GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables);
+ gen11_hpd_detection_setup(dev_priv);
+ } else if (IS_GEN9_LP(dev_priv)) {
bxt_hpd_detection_setup(dev_priv);
- else if (IS_BROADWELL(dev_priv))
+ } else if (IS_BROADWELL(dev_priv)) {
ilk_hpd_detection_setup(dev_priv);
+ }
}
static int gen8_irq_postinstall(struct drm_device *dev)
@@ -4505,7 +4594,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->irq_uninstall = gen11_irq_reset;
dev->driver->enable_vblank = gen8_enable_vblank;
dev->driver->disable_vblank = gen8_disable_vblank;
- dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
+ dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
} else if (INTEL_GEN(dev_priv) >= 8) {
dev->driver->irq_handler = gen8_irq_handler;
dev->driver->irq_preinstall = gen8_irq_reset;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ca474f6f523c..19600097581f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7036,11 +7036,31 @@ enum {
#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
#define GEN11_DE_PCH_IRQ (1 << 23)
#define GEN11_DE_MISC_IRQ (1 << 22)
+#define GEN11_DE_HPD_IRQ (1 << 21)
#define GEN11_DE_PORT_IRQ (1 << 20)
#define GEN11_DE_PIPE_C (1 << 18)
#define GEN11_DE_PIPE_B (1 << 17)
#define GEN11_DE_PIPE_A (1 << 16)
+#define GEN11_DE_HPD_ISR _MMIO(0x44470)
+#define GEN11_DE_HPD_IMR _MMIO(0x44474)
+#define GEN11_DE_HPD_IIR _MMIO(0x44478)
+#define GEN11_DE_HPD_IER _MMIO(0x4447c)
+#define GEN11_TC4_HOTPLUG (1 << 19)
+#define GEN11_TC3_HOTPLUG (1 << 18)
+#define GEN11_TC2_HOTPLUG (1 << 17)
+#define GEN11_TC1_HOTPLUG (1 << 16)
+#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG | \
+ GEN11_TC3_HOTPLUG | \
+ GEN11_TC2_HOTPLUG | \
+ GEN11_TC1_HOTPLUG)
+
+#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
+#define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4)
+#define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
+#define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
+#define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4)
+
#define GEN11_GT_INTR_DW0 _MMIO(0x190018)
#define GEN11_CSME (31)
#define GEN11_GUNIT (28)
--
2.14.3
_______________________________________________
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^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 04/24] drm/i915/icl: Support for TC North Display interrupts
2018-05-22 0:25 ` [PATCH 04/24] drm/i915/icl: Support for TC North Display interrupts Paulo Zanoni
@ 2018-06-13 22:20 ` Lucas De Marchi
2018-06-15 23:47 ` Paulo Zanoni
0 siblings, 1 reply; 127+ messages in thread
From: Lucas De Marchi @ 2018-06-13 22:20 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: Jani Nikula, intel-gfx, Dhinakaran Pandiyan
+Chris
On Mon, May 21, 2018 at 05:25:38PM -0700, Paulo Zanoni wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>
> The hotplug interrupts for the ports can be routed to either North
> Display or South Display depending on the output mode. DP Alternate or
> DP over TBT outputs will have hotplug interrupts routed to the North
> Display while interrupts for legacy modes will be routed to the South
> Display in PCH. This patch adds hotplug interrupt handling support for
> DP Alternate mode.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> [Paulo: coding style changes]
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 95 +++++++++++++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++
> 2 files changed, 112 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index dde938bbfb0a..9bcec5fdb9d0 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -115,6 +115,13 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
> [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
> };
>
> +static const u32 hpd_tc_gen11[HPD_NUM_PINS] = {
> + [HPD_PORT_C] = GEN11_TC1_HOTPLUG,
> + [HPD_PORT_D] = GEN11_TC2_HOTPLUG,
> + [HPD_PORT_E] = GEN11_TC3_HOTPLUG,
> + [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> +};
> +
> /* IIR can theoretically queue up two events. Be paranoid. */
> #define GEN8_IRQ_RESET_NDX(type, which) do { \
> I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
> @@ -1549,6 +1556,22 @@ static void gen8_gt_irq_handler(struct drm_i915_private *i915,
> }
> }
>
> +static bool gen11_port_hotplug_long_detect(enum port port, u32 val)
> +{
> + switch (port) {
> + case PORT_C:
> + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
> + case PORT_D:
> + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
> + case PORT_E:
> + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
> + case PORT_F:
> + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
> + default:
> + return false;
> + }
> +}
> +
> static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
> {
> switch (port) {
> @@ -2590,6 +2613,25 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
> intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> }
>
> +static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> +{
> + u32 pin_mask = 0, long_mask = 0;
> + u32 trigger_tc, dig_hotplug_reg;
> +
> + trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
> + if (trigger_tc) {
> + dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
> + I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
> +
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
> + dig_hotplug_reg, hpd_tc_gen11,
> + gen11_port_hotplug_long_detect);
> + intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> + } else {
> + DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir);
> + }
> +}
> +
> static irqreturn_t
> gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> {
> @@ -2626,6 +2668,17 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
> }
>
> + if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
> + iir = I915_READ(GEN11_DE_HPD_IIR);
> + if (iir) {
> + I915_WRITE(GEN11_DE_HPD_IIR, iir);
> + ret = IRQ_HANDLED;
> + gen11_hpd_irq_handler(dev_priv, iir);
I think the same question as for the 2nd patch remains here. Shouldn't
we being re-enabling the master interrupt before doing any further
processing?
However all gens are like that. A change here seems to belong on a
different patch... it's also the case for previous gens. Chris, is there
anything different you are seeing on gen11?
Lucas De Marchi
> + } else {
> + DRM_ERROR("The master control interrupt lied, (DE HPD)!\n");
> + }
> + }
> +
> if (master_ctl & GEN8_DE_PORT_IRQ) {
> iir = I915_READ(GEN8_DE_PORT_IIR);
> if (iir) {
> @@ -3492,6 +3545,7 @@ static void gen11_irq_reset(struct drm_device *dev)
>
> GEN3_IRQ_RESET(GEN8_DE_PORT_);
> GEN3_IRQ_RESET(GEN8_DE_MISC_);
> + GEN3_IRQ_RESET(GEN11_DE_HPD_);
> GEN3_IRQ_RESET(GEN11_GU_MISC_);
> GEN3_IRQ_RESET(GEN8_PCU_);
> }
> @@ -3610,6 +3664,34 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
> ibx_hpd_detection_setup(dev_priv);
> }
>
> +static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
> +{
> + u32 hotplug;
> +
> + hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
> + hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
> + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
> + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
> + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
> + I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
> +}
> +
> +static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +{
> + u32 hotplug_irqs, enabled_irqs;
> + u32 val;
> +
> + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_tc_gen11);
> + hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK;
> +
> + val = I915_READ(GEN11_DE_HPD_IMR);
> + val &= ~hotplug_irqs;
> + I915_WRITE(GEN11_DE_HPD_IMR, val);
> + POSTING_READ(GEN11_DE_HPD_IMR);
> +
> + gen11_hpd_detection_setup(dev_priv);
> +}
> +
> static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> u32 val, hotplug;
> @@ -3980,10 +4062,17 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
> GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
>
> - if (IS_GEN9_LP(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 11) {
> + u32 de_hpd_masked = 0;
> + u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK;
> +
> + GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables);
> + gen11_hpd_detection_setup(dev_priv);
> + } else if (IS_GEN9_LP(dev_priv)) {
> bxt_hpd_detection_setup(dev_priv);
> - else if (IS_BROADWELL(dev_priv))
> + } else if (IS_BROADWELL(dev_priv)) {
> ilk_hpd_detection_setup(dev_priv);
> + }
> }
>
> static int gen8_irq_postinstall(struct drm_device *dev)
> @@ -4505,7 +4594,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev->driver->irq_uninstall = gen11_irq_reset;
> dev->driver->enable_vblank = gen8_enable_vblank;
> dev->driver->disable_vblank = gen8_disable_vblank;
> - dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> + dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
> } else if (INTEL_GEN(dev_priv) >= 8) {
> dev->driver->irq_handler = gen8_irq_handler;
> dev->driver->irq_preinstall = gen8_irq_reset;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ca474f6f523c..19600097581f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7036,11 +7036,31 @@ enum {
> #define GEN11_AUDIO_CODEC_IRQ (1 << 24)
> #define GEN11_DE_PCH_IRQ (1 << 23)
> #define GEN11_DE_MISC_IRQ (1 << 22)
> +#define GEN11_DE_HPD_IRQ (1 << 21)
> #define GEN11_DE_PORT_IRQ (1 << 20)
> #define GEN11_DE_PIPE_C (1 << 18)
> #define GEN11_DE_PIPE_B (1 << 17)
> #define GEN11_DE_PIPE_A (1 << 16)
>
> +#define GEN11_DE_HPD_ISR _MMIO(0x44470)
> +#define GEN11_DE_HPD_IMR _MMIO(0x44474)
> +#define GEN11_DE_HPD_IIR _MMIO(0x44478)
> +#define GEN11_DE_HPD_IER _MMIO(0x4447c)
> +#define GEN11_TC4_HOTPLUG (1 << 19)
> +#define GEN11_TC3_HOTPLUG (1 << 18)
> +#define GEN11_TC2_HOTPLUG (1 << 17)
> +#define GEN11_TC1_HOTPLUG (1 << 16)
> +#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG | \
> + GEN11_TC3_HOTPLUG | \
> + GEN11_TC2_HOTPLUG | \
> + GEN11_TC1_HOTPLUG)
> +
> +#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
> +#define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4)
> +#define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> +#define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
> +#define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4)
> +
> #define GEN11_GT_INTR_DW0 _MMIO(0x190018)
> #define GEN11_CSME (31)
> #define GEN11_GUNIT (28)
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 04/24] drm/i915/icl: Support for TC North Display interrupts
2018-06-13 22:20 ` Lucas De Marchi
@ 2018-06-15 23:47 ` Paulo Zanoni
0 siblings, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-06-15 23:47 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Jani Nikula, intel-gfx, Dhinakaran Pandiyan
Em Qua, 2018-06-13 às 15:20 -0700, Lucas De Marchi escreveu:
> +Chris
>
> On Mon, May 21, 2018 at 05:25:38PM -0700, Paulo Zanoni wrote:
> > From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> >
> > The hotplug interrupts for the ports can be routed to either North
> > Display or South Display depending on the output mode. DP Alternate
> > or
> > DP over TBT outputs will have hotplug interrupts routed to the
> > North
> > Display while interrupts for legacy modes will be routed to the
> > South
> > Display in PCH. This patch adds hotplug interrupt handling support
> > for
> > DP Alternate mode.
> >
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > [Paulo: coding style changes]
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 95
> > +++++++++++++++++++++++++++++++++++++++--
> > drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++
> > 2 files changed, 112 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index dde938bbfb0a..9bcec5fdb9d0 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -115,6 +115,13 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
> > [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
> > };
> >
> > +static const u32 hpd_tc_gen11[HPD_NUM_PINS] = {
> > + [HPD_PORT_C] = GEN11_TC1_HOTPLUG,
> > + [HPD_PORT_D] = GEN11_TC2_HOTPLUG,
> > + [HPD_PORT_E] = GEN11_TC3_HOTPLUG,
> > + [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > +};
> > +
> > /* IIR can theoretically queue up two events. Be paranoid. */
> > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
> > @@ -1549,6 +1556,22 @@ static void gen8_gt_irq_handler(struct
> > drm_i915_private *i915,
> > }
> > }
> >
> > +static bool gen11_port_hotplug_long_detect(enum port port, u32
> > val)
> > +{
> > + switch (port) {
> > + case PORT_C:
> > + return val &
> > GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
> > + case PORT_D:
> > + return val &
> > GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
> > + case PORT_E:
> > + return val &
> > GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
> > + case PORT_F:
> > + return val &
> > GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
> > + default:
> > + return false;
> > + }
> > +}
> > +
> > static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
> > {
> > switch (port) {
> > @@ -2590,6 +2613,25 @@ static void bxt_hpd_irq_handler(struct
> > drm_i915_private *dev_priv,
> > intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> > }
> >
> > +static void gen11_hpd_irq_handler(struct drm_i915_private
> > *dev_priv, u32 iir)
> > +{
> > + u32 pin_mask = 0, long_mask = 0;
> > + u32 trigger_tc, dig_hotplug_reg;
> > +
> > + trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
> > + if (trigger_tc) {
> > + dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
> > + I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
> > +
> > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > &long_mask, trigger_tc,
> > + dig_hotplug_reg, hpd_tc_gen11,
> > + gen11_port_hotplug_long_detect)
> > ;
> > + intel_hpd_irq_handler(dev_priv, pin_mask,
> > long_mask);
> > + } else {
> > + DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n",
> > iir);
> > + }
> > +}
> > +
> > static irqreturn_t
> > gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32
> > master_ctl)
> > {
> > @@ -2626,6 +2668,17 @@ gen8_de_irq_handler(struct drm_i915_private
> > *dev_priv, u32 master_ctl)
> > DRM_ERROR("The master control interrupt
> > lied (DE MISC)!\n");
> > }
> >
> > + if (INTEL_GEN(dev_priv) >= 11 && (master_ctl &
> > GEN11_DE_HPD_IRQ)) {
> > + iir = I915_READ(GEN11_DE_HPD_IIR);
> > + if (iir) {
> > + I915_WRITE(GEN11_DE_HPD_IIR, iir);
> > + ret = IRQ_HANDLED;
> > + gen11_hpd_irq_handler(dev_priv, iir);
>
> I think the same question as for the 2nd patch remains here.
> Shouldn't
> we being re-enabling the master interrupt before doing any further
> processing?
>
> However all gens are like that. A change here seems to belong on a
> different patch... it's also the case for previous gens. Chris, is
> there
> anything different you are seeing on gen11?
I'd say this type of request should definitely be on a separate patch.
We have some major inconsistencies in the way we handle interrupts:
some places use raw write/read, some places don't, some places do use
the likely/unlikely helpers, some places don't, some places do the post
processing, some places don't. If we want people to use a specific
style we should probably convert the current code to use it first.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Lucas De Marchi
>
>
> > + } else {
> > + DRM_ERROR("The master control interrupt
> > lied, (DE HPD)!\n");
> > + }
> > + }
> > +
> > if (master_ctl & GEN8_DE_PORT_IRQ) {
> > iir = I915_READ(GEN8_DE_PORT_IIR);
> > if (iir) {
> > @@ -3492,6 +3545,7 @@ static void gen11_irq_reset(struct drm_device
> > *dev)
> >
> > GEN3_IRQ_RESET(GEN8_DE_PORT_);
> > GEN3_IRQ_RESET(GEN8_DE_MISC_);
> > + GEN3_IRQ_RESET(GEN11_DE_HPD_);
> > GEN3_IRQ_RESET(GEN11_GU_MISC_);
> > GEN3_IRQ_RESET(GEN8_PCU_);
> > }
> > @@ -3610,6 +3664,34 @@ static void ibx_hpd_irq_setup(struct
> > drm_i915_private *dev_priv)
> > ibx_hpd_detection_setup(dev_priv);
> > }
> >
> > +static void gen11_hpd_detection_setup(struct drm_i915_private
> > *dev_priv)
> > +{
> > + u32 hotplug;
> > +
> > + hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
> > + hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
> > + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
> > + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
> > + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
> > + I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
> > +}
> > +
> > +static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
> > +{
> > + u32 hotplug_irqs, enabled_irqs;
> > + u32 val;
> > +
> > + enabled_irqs = intel_hpd_enabled_irqs(dev_priv,
> > hpd_tc_gen11);
> > + hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK;
> > +
> > + val = I915_READ(GEN11_DE_HPD_IMR);
> > + val &= ~hotplug_irqs;
> > + I915_WRITE(GEN11_DE_HPD_IMR, val);
> > + POSTING_READ(GEN11_DE_HPD_IMR);
> > +
> > + gen11_hpd_detection_setup(dev_priv);
> > +}
> > +
> > static void spt_hpd_detection_setup(struct drm_i915_private
> > *dev_priv)
> > {
> > u32 val, hotplug;
> > @@ -3980,10 +4062,17 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked,
> > de_port_enables);
> > GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked,
> > de_misc_masked);
> >
> > - if (IS_GEN9_LP(dev_priv))
> > + if (INTEL_GEN(dev_priv) >= 11) {
> > + u32 de_hpd_masked = 0;
> > + u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK;
> > +
> > + GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked,
> > de_hpd_enables);
> > + gen11_hpd_detection_setup(dev_priv);
> > + } else if (IS_GEN9_LP(dev_priv)) {
> > bxt_hpd_detection_setup(dev_priv);
> > - else if (IS_BROADWELL(dev_priv))
> > + } else if (IS_BROADWELL(dev_priv)) {
> > ilk_hpd_detection_setup(dev_priv);
> > + }
> > }
> >
> > static int gen8_irq_postinstall(struct drm_device *dev)
> > @@ -4505,7 +4594,7 @@ void intel_irq_init(struct drm_i915_private
> > *dev_priv)
> > dev->driver->irq_uninstall = gen11_irq_reset;
> > dev->driver->enable_vblank = gen8_enable_vblank;
> > dev->driver->disable_vblank = gen8_disable_vblank;
> > - dev_priv->display.hpd_irq_setup =
> > spt_hpd_irq_setup;
> > + dev_priv->display.hpd_irq_setup =
> > gen11_hpd_irq_setup;
> > } else if (INTEL_GEN(dev_priv) >= 8) {
> > dev->driver->irq_handler = gen8_irq_handler;
> > dev->driver->irq_preinstall = gen8_irq_reset;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index ca474f6f523c..19600097581f 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7036,11 +7036,31 @@ enum {
> > #define GEN11_AUDIO_CODEC_IRQ (1 << 24)
> > #define GEN11_DE_PCH_IRQ (1 << 23)
> > #define GEN11_DE_MISC_IRQ (1 << 22)
> > +#define GEN11_DE_HPD_IRQ (1 << 21)
> > #define GEN11_DE_PORT_IRQ (1 << 20)
> > #define GEN11_DE_PIPE_C (1 << 18)
> > #define GEN11_DE_PIPE_B (1 << 17)
> > #define GEN11_DE_PIPE_A (1 << 16)
> >
> > +#define GEN11_DE_HPD_ISR _MMIO(0x44470)
> > +#define GEN11_DE_HPD_IMR _MMIO(0x44474)
> > +#define GEN11_DE_HPD_IIR _MMIO(0x44478)
> > +#define GEN11_DE_HPD_IER _MMIO(0x4447c)
> > +#define GEN11_TC4_HOTPLUG (1 << 19)
> > +#define GEN11_TC3_HOTPLUG (1 << 18)
> > +#define GEN11_TC2_HOTPLUG (1 << 17)
> > +#define GEN11_TC1_HOTPLUG (1 << 16)
> > +#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLU
> > G | \
> > + GEN11_TC3_HOTPLUG
> > | \
> > + GEN11_TC2_HOTPLUG
> > | \
> > + GEN11_TC1_HOTPLUG
> > )
> > +
> > +#define GEN11_TC_HOTPLUG_CTL _MMIO(
> > 0x44038)
> > +#define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 <<
> > (tc_port) * 4)
> > +#define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2
> > << (tc_port) * 4)
> > +#define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 <<
> > (tc_port) * 4)
> > +#define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 <<
> > (tc_port) * 4)
> > +
> > #define GEN11_GT_INTR_DW0 _MMIO(0x190018)
> > #define GEN11_CSME (31)
> > #define GEN11_GUNIT (28)
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 05/24] drm/i915/icp: Add Interrupt Support
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (3 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 04/24] drm/i915/icl: Support for TC North Display interrupts Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-05-24 23:53 ` Lucas De Marchi
2018-05-22 0:25 ` [PATCH 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE Paulo Zanoni
` (35 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Dhinakaran Pandiyan
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
This patch addresses Interrupts from south display engine (SDE).
ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
Introduce these registers and their intended values.
Introduce icp_irq_handler().
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
[Paulo: coding style bikesheds and rebases].
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 134 +++++++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++
2 files changed, 172 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9bcec5fdb9d0..6b109991786f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -122,6 +122,15 @@ static const u32 hpd_tc_gen11[HPD_NUM_PINS] = {
[HPD_PORT_F] = GEN11_TC4_HOTPLUG
};
+static const u32 hpd_icp[HPD_NUM_PINS] = {
+ [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
+ [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
+ [HPD_PORT_C] = ICP_TC1_HOTPLUG,
+ [HPD_PORT_D] = ICP_TC2_HOTPLUG,
+ [HPD_PORT_E] = ICP_TC3_HOTPLUG,
+ [HPD_PORT_F] = ICP_TC4_HOTPLUG
+};
+
/* IIR can theoretically queue up two events. Be paranoid. */
#define GEN8_IRQ_RESET_NDX(type, which) do { \
I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
@@ -1586,6 +1595,34 @@ static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
}
}
+static bool icp_ddi_port_hotplug_long_detect(enum port port, u32 val)
+{
+ switch (port) {
+ case PORT_A:
+ return val & ICP_DDIA_HPD_LONG_DETECT;
+ case PORT_B:
+ return val & ICP_DDIB_HPD_LONG_DETECT;
+ default:
+ return false;
+ }
+}
+
+static bool icp_tc_port_hotplug_long_detect(enum port port, u32 val)
+{
+ switch (port) {
+ case PORT_C:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
+ case PORT_D:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
+ case PORT_E:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
+ case PORT_F:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
+ default:
+ return false;
+ }
+}
+
static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
{
switch (port) {
@@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
cpt_serr_int_handler(dev_priv);
}
+static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
+{
+ u32 ddi_hotplug_trigger = pch_iir & ICP_SDE_DDI_MASK;
+ u32 tc_hotplug_trigger = pch_iir & ICP_SDE_TC_MASK;
+ u32 pin_mask = 0, long_mask = 0;
+
+ if (ddi_hotplug_trigger) {
+ u32 dig_hotplug_reg;
+
+ dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
+ I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
+
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ ddi_hotplug_trigger,
+ dig_hotplug_reg, hpd_icp,
+ icp_ddi_port_hotplug_long_detect);
+ }
+
+ if (tc_hotplug_trigger) {
+ u32 dig_hotplug_reg;
+
+ dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
+ I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
+
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ tc_hotplug_trigger,
+ dig_hotplug_reg, hpd_icp,
+ icp_tc_port_hotplug_long_detect);
+ }
+
+ if (pin_mask)
+ intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
+
+ if (pch_iir & ICP_GMBUS)
+ gmbus_irq_handler(dev_priv);
+}
+
static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
@@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
I915_WRITE(SDEIIR, iir);
ret = IRQ_HANDLED;
- if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
- HAS_PCH_CNP(dev_priv))
+ if (HAS_PCH_ICP(dev_priv))
+ icp_irq_handler(dev_priv, iir);
+ else if (HAS_PCH_SPT(dev_priv) ||
+ HAS_PCH_KBP(dev_priv) ||
+ HAS_PCH_CNP(dev_priv))
spt_irq_handler(dev_priv, iir);
else
cpt_irq_handler(dev_priv, iir);
@@ -3548,6 +3625,9 @@ static void gen11_irq_reset(struct drm_device *dev)
GEN3_IRQ_RESET(GEN11_DE_HPD_);
GEN3_IRQ_RESET(GEN11_GU_MISC_);
GEN3_IRQ_RESET(GEN8_PCU_);
+
+ if (HAS_PCH_ICP(dev_priv))
+ GEN3_IRQ_RESET(ICP_SDE_);
}
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3664,6 +3744,35 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
ibx_hpd_detection_setup(dev_priv);
}
+static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv)
+{
+ u32 hotplug;
+
+ hotplug = I915_READ(SHOTPLUG_CTL_DDI);
+ hotplug |= ICP_DDIA_HPD_ENABLE |
+ ICP_DDIB_HPD_ENABLE;
+ I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
+
+ hotplug = I915_READ(SHOTPLUG_CTL_TC);
+ hotplug |= ICP_TC_HPD_ENABLE(PORT_TC1) |
+ ICP_TC_HPD_ENABLE(PORT_TC2) |
+ ICP_TC_HPD_ENABLE(PORT_TC3) |
+ ICP_TC_HPD_ENABLE(PORT_TC4);
+ I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
+}
+
+static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+ u32 hotplug_irqs, enabled_irqs;
+
+ hotplug_irqs = ICP_SDE_DDI_MASK | ICP_SDE_TC_MASK;
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp);
+
+ ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
+
+ icp_hpd_detection_setup(dev_priv);
+}
+
static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug;
@@ -3690,6 +3799,9 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
POSTING_READ(GEN11_DE_HPD_IMR);
gen11_hpd_detection_setup(dev_priv);
+
+ if (HAS_PCH_ICP(dev_priv))
+ icp_hpd_irq_setup(dev_priv);
}
static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
@@ -4121,11 +4233,29 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
}
+static void icp_irq_postinstall(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ u32 mask = ICP_GMBUS;
+
+ WARN_ON(I915_READ(ICP_SDE_IER) != 0);
+ I915_WRITE(ICP_SDE_IER, 0xffffffff);
+ POSTING_READ(ICP_SDE_IER);
+
+ gen3_assert_iir_is_zero(dev_priv, ICP_SDE_IIR);
+ I915_WRITE(ICP_SDE_IMR, ~mask);
+
+ icp_hpd_detection_setup(dev_priv);
+}
+
static int gen11_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
+ if (HAS_PCH_ICP(dev_priv))
+ icp_irq_postinstall(dev);
+
gen11_gt_irq_postinstall(dev_priv);
gen8_de_irq_postinstall(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 19600097581f..28ce96ce0484 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7460,6 +7460,46 @@ enum {
#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
+/* ICP */
+#define ICP_SDE_ISR _MMIO(0xc4000)
+#define ICP_SDE_IMR _MMIO(0xc4004)
+#define ICP_SDE_IIR _MMIO(0xc4008)
+#define ICP_SDE_IER _MMIO(0xc400c)
+#define ICP_TC4_HOTPLUG (1 << 27)
+#define ICP_TC3_HOTPLUG (1 << 26)
+#define ICP_TC2_HOTPLUG (1 << 25)
+#define ICP_TC1_HOTPLUG (1 << 24)
+#define ICP_GMBUS (1 << 23)
+#define ICP_DDIB_HOTPLUG (1 << 17)
+#define ICP_DDIA_HOTPLUG (1 << 16)
+
+#define ICP_SDE_DDI_MASK (ICP_DDIB_HOTPLUG | \
+ ICP_DDIA_HOTPLUG)
+
+#define ICP_SDE_TC_MASK (ICP_TC4_HOTPLUG | \
+ ICP_TC3_HOTPLUG | \
+ ICP_TC2_HOTPLUG | \
+ ICP_TC1_HOTPLUG)
+
+#define SHOTPLUG_CTL_DDI _MMIO(0xc4030) /* SHOTPLUG_CTL */
+#define ICP_DDIB_HPD_ENABLE (1 << 7)
+#define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
+#define ICP_DDIB_HPD_NO_DETECT (0 << 4)
+#define ICP_DDIB_HPD_SHORT_DETECT (1 << 4)
+#define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
+#define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
+#define ICP_DDIA_HPD_ENABLE (1 << 3)
+#define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
+#define ICP_DDIA_HPD_NO_DETECT (0 << 0)
+#define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
+#define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
+#define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
+
+#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
+#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
+#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
+#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
+
#define PCH_GPIOA _MMIO(0xc5010)
#define PCH_GPIOB _MMIO(0xc5014)
#define PCH_GPIOC _MMIO(0xc5018)
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 05/24] drm/i915/icp: Add Interrupt Support
2018-05-22 0:25 ` [PATCH 05/24] drm/i915/icp: Add Interrupt Support Paulo Zanoni
@ 2018-05-24 23:53 ` Lucas De Marchi
2018-05-25 0:45 ` Dhinakaran Pandiyan
0 siblings, 1 reply; 127+ messages in thread
From: Lucas De Marchi @ 2018-05-24 23:53 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Dhinakaran Pandiyan
On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> This patch addresses Interrupts from south display engine (SDE).
>
> ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> Introduce these registers and their intended values.
>
> Introduce icp_irq_handler().
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> [Paulo: coding style bikesheds and rebases].
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 134 +++++++++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++
> 2 files changed, 172 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 9bcec5fdb9d0..6b109991786f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -122,6 +122,15 @@ static const u32 hpd_tc_gen11[HPD_NUM_PINS] = {
> [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> };
>
> +static const u32 hpd_icp[HPD_NUM_PINS] = {
> + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> +};
> +
> /* IIR can theoretically queue up two events. Be paranoid. */
> #define GEN8_IRQ_RESET_NDX(type, which) do { \
> I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
> @@ -1586,6 +1595,34 @@ static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
> }
> }
>
> +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32 val)
> +{
> + switch (port) {
> + case PORT_A:
> + return val & ICP_DDIA_HPD_LONG_DETECT;
> + case PORT_B:
> + return val & ICP_DDIB_HPD_LONG_DETECT;
> + default:
> + return false;
> + }
> +}
> +
> +static bool icp_tc_port_hotplug_long_detect(enum port port, u32 val)
> +{
> + switch (port) {
> + case PORT_C:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> + case PORT_D:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> + case PORT_E:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> + case PORT_F:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> + default:
> + return false;
> + }
> +}
> +
> static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
> {
> switch (port) {
> @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> cpt_serr_int_handler(dev_priv);
> }
>
> +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> +{
> + u32 ddi_hotplug_trigger = pch_iir & ICP_SDE_DDI_MASK;
> + u32 tc_hotplug_trigger = pch_iir & ICP_SDE_TC_MASK;
> + u32 pin_mask = 0, long_mask = 0;
> +
> + if (ddi_hotplug_trigger) {
> + u32 dig_hotplug_reg;
> +
> + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> +
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + ddi_hotplug_trigger,
> + dig_hotplug_reg, hpd_icp,
> + icp_ddi_port_hotplug_long_detect);
> + }
> +
> + if (tc_hotplug_trigger) {
> + u32 dig_hotplug_reg;
> +
> + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> +
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + tc_hotplug_trigger,
> + dig_hotplug_reg, hpd_icp,
> + icp_tc_port_hotplug_long_detect);
> + }
> +
> + if (pin_mask)
> + intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> +
> + if (pch_iir & ICP_GMBUS)
> + gmbus_irq_handler(dev_priv);
> +}
> +
> static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> {
> u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
> @@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> I915_WRITE(SDEIIR, iir);
> ret = IRQ_HANDLED;
>
> - if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
> - HAS_PCH_CNP(dev_priv))
> + if (HAS_PCH_ICP(dev_priv))
> + icp_irq_handler(dev_priv, iir);
> + else if (HAS_PCH_SPT(dev_priv) ||
> + HAS_PCH_KBP(dev_priv) ||
> + HAS_PCH_CNP(dev_priv))
> spt_irq_handler(dev_priv, iir);
> else
> cpt_irq_handler(dev_priv, iir);
> @@ -3548,6 +3625,9 @@ static void gen11_irq_reset(struct drm_device *dev)
> GEN3_IRQ_RESET(GEN11_DE_HPD_);
> GEN3_IRQ_RESET(GEN11_GU_MISC_);
> GEN3_IRQ_RESET(GEN8_PCU_);
> +
> + if (HAS_PCH_ICP(dev_priv))
> + GEN3_IRQ_RESET(ICP_SDE_);
> }
>
> void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> @@ -3664,6 +3744,35 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
> ibx_hpd_detection_setup(dev_priv);
> }
>
> +static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv)
> +{
> + u32 hotplug;
> +
> + hotplug = I915_READ(SHOTPLUG_CTL_DDI);
> + hotplug |= ICP_DDIA_HPD_ENABLE |
> + ICP_DDIB_HPD_ENABLE;
> + I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
> +
> + hotplug = I915_READ(SHOTPLUG_CTL_TC);
> + hotplug |= ICP_TC_HPD_ENABLE(PORT_TC1) |
> + ICP_TC_HPD_ENABLE(PORT_TC2) |
> + ICP_TC_HPD_ENABLE(PORT_TC3) |
> + ICP_TC_HPD_ENABLE(PORT_TC4);
> + I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
> +}
> +
> +static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +{
> + u32 hotplug_irqs, enabled_irqs;
> +
> + hotplug_irqs = ICP_SDE_DDI_MASK | ICP_SDE_TC_MASK;
> + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp);
> +
> + ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> +
> + icp_hpd_detection_setup(dev_priv);
> +}
> +
> static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> u32 hotplug;
> @@ -3690,6 +3799,9 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
> POSTING_READ(GEN11_DE_HPD_IMR);
>
> gen11_hpd_detection_setup(dev_priv);
> +
> + if (HAS_PCH_ICP(dev_priv))
> + icp_hpd_irq_setup(dev_priv);
> }
>
> static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
> @@ -4121,11 +4233,29 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> }
>
> +static void icp_irq_postinstall(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + u32 mask = ICP_GMBUS;
> +
> + WARN_ON(I915_READ(ICP_SDE_IER) != 0);
> + I915_WRITE(ICP_SDE_IER, 0xffffffff);
> + POSTING_READ(ICP_SDE_IER);
> +
> + gen3_assert_iir_is_zero(dev_priv, ICP_SDE_IIR);
> + I915_WRITE(ICP_SDE_IMR, ~mask);
> +
> + icp_hpd_detection_setup(dev_priv);
> +}
> +
> static int gen11_irq_postinstall(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 gu_misc_masked = GEN11_GU_MISC_GSE;
>
> + if (HAS_PCH_ICP(dev_priv))
> + icp_irq_postinstall(dev);
> +
> gen11_gt_irq_postinstall(dev_priv);
> gen8_de_irq_postinstall(dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 19600097581f..28ce96ce0484 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7460,6 +7460,46 @@ enum {
> #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
> #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
>
> +/* ICP */
> +#define ICP_SDE_ISR _MMIO(0xc4000)
> +#define ICP_SDE_IMR _MMIO(0xc4004)
> +#define ICP_SDE_IIR _MMIO(0xc4008)
> +#define ICP_SDE_IER _MMIO(0xc400c)
These are exactly the same registers as SDE{ISR,IMR,IIR,IER}. For all
the other platforms what we do is rather postfix the platform name.
I think we should follow what they do here.
> +#define ICP_TC4_HOTPLUG (1 << 27)
> +#define ICP_TC3_HOTPLUG (1 << 26)
> +#define ICP_TC2_HOTPLUG (1 << 25)
> +#define ICP_TC1_HOTPLUG (1 << 24)
> +#define ICP_GMBUS (1 << 23)
> +#define ICP_DDIB_HOTPLUG (1 << 17)
> +#define ICP_DDIA_HOTPLUG (1 << 16)
so these would become SDE_TC4_HOTPLUG_ICP and so on.
> +
> +#define ICP_SDE_DDI_MASK (ICP_DDIB_HOTPLUG | \
> + ICP_DDIA_HOTPLUG)
> +
> +#define ICP_SDE_TC_MASK (ICP_TC4_HOTPLUG | \
> + ICP_TC3_HOTPLUG | \
> + ICP_TC2_HOTPLUG | \
> + ICP_TC1_HOTPLUG)
> +
> +#define SHOTPLUG_CTL_DDI _MMIO(0xc4030) /* SHOTPLUG_CTL */
This also seems to reuse what we have defined as PCH_PORT_HOTPLUG with a
comment to SHOTPLUG_CTL there, although here I tend to be in favor of
using the current real name of the register (SHOTPLUG_CTL).
The rest looks good to me.
Lucas De Marchi
> +#define ICP_DDIB_HPD_ENABLE (1 << 7)
> +#define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
> +#define ICP_DDIB_HPD_NO_DETECT (0 << 4)
> +#define ICP_DDIB_HPD_SHORT_DETECT (1 << 4)
> +#define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
> +#define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
> +#define ICP_DDIA_HPD_ENABLE (1 << 3)
> +#define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
> +#define ICP_DDIA_HPD_NO_DETECT (0 << 0)
> +#define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
> +#define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
> +#define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
> +
> +#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
> +#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
> +#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> +#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
> +
> #define PCH_GPIOA _MMIO(0xc5010)
> #define PCH_GPIOB _MMIO(0xc5014)
> #define PCH_GPIOC _MMIO(0xc5018)
> --
> 2.14.3
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 05/24] drm/i915/icp: Add Interrupt Support
2018-05-24 23:53 ` Lucas De Marchi
@ 2018-05-25 0:45 ` Dhinakaran Pandiyan
2018-05-25 0:43 ` Lucas De Marchi
0 siblings, 1 reply; 127+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-25 0:45 UTC (permalink / raw)
To: Lucas De Marchi, Paulo Zanoni; +Cc: intel-gfx
On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> >
> > From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >
> > This patch addresses Interrupts from south display engine (SDE).
> >
> > ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> > Introduce these registers and their intended values.
> >
> > Introduce icp_irq_handler().
> >
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > [Paulo: coding style bikesheds and rebases].
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 134
> > +++++++++++++++++++++++++++++++++++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++
> > 2 files changed, 172 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 9bcec5fdb9d0..6b109991786f 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -122,6 +122,15 @@ static const u32 hpd_tc_gen11[HPD_NUM_PINS] =
> > {
> > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > };
> >
> > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > +};
> > +
> > /* IIR can theoretically queue up two events. Be paranoid. */
> > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
> > @@ -1586,6 +1595,34 @@ static bool
> > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > }
> > }
> >
> > +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32
> > val)
> > +{
> > + switch (port) {
> > + case PORT_A:
> > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > + case PORT_B:
> > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > + default:
> > + return false;
> > + }
> > +}
> > +
> > +static bool icp_tc_port_hotplug_long_detect(enum port port, u32
> > val)
> > +{
> > + switch (port) {
> > + case PORT_C:
> > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > + case PORT_D:
> > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > + case PORT_E:
> > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > + case PORT_F:
> > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > + default:
> > + return false;
> > + }
> > +}
> > +
> > static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
> > {
> > switch (port) {
> > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > drm_i915_private *dev_priv, u32 pch_iir)
> > cpt_serr_int_handler(dev_priv);
> > }
> >
> > +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32
> > pch_iir)
> > +{
> > + u32 ddi_hotplug_trigger = pch_iir & ICP_SDE_DDI_MASK;
> > + u32 tc_hotplug_trigger = pch_iir & ICP_SDE_TC_MASK;
> > + u32 pin_mask = 0, long_mask = 0;
> > +
> > + if (ddi_hotplug_trigger) {
> > + u32 dig_hotplug_reg;
> > +
> > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> > + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> > +
> > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > &long_mask,
> > + ddi_hotplug_trigger,
> > + dig_hotplug_reg, hpd_icp,
> > + icp_ddi_port_hotplug_long_detec
> > t);
> > + }
> > +
> > + if (tc_hotplug_trigger) {
> > + u32 dig_hotplug_reg;
> > +
> > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> > + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> > +
> > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > &long_mask,
> > + tc_hotplug_trigger,
> > + dig_hotplug_reg, hpd_icp,
> > + icp_tc_port_hotplug_long_detect
> > );
> > + }
> > +
> > + if (pin_mask)
> > + intel_hpd_irq_handler(dev_priv, pin_mask,
> > long_mask);
> > +
> > + if (pch_iir & ICP_GMBUS)
> > + gmbus_irq_handler(dev_priv);
> > +}
> > +
> > static void spt_irq_handler(struct drm_i915_private *dev_priv, u32
> > pch_iir)
> > {
> > u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
> > @@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct drm_i915_private
> > *dev_priv, u32 master_ctl)
> > I915_WRITE(SDEIIR, iir);
> > ret = IRQ_HANDLED;
> >
> > - if (HAS_PCH_SPT(dev_priv) ||
> > HAS_PCH_KBP(dev_priv) ||
> > - HAS_PCH_CNP(dev_priv))
> > + if (HAS_PCH_ICP(dev_priv))
> > + icp_irq_handler(dev_priv, iir);
> > + else if (HAS_PCH_SPT(dev_priv) ||
> > + HAS_PCH_KBP(dev_priv) ||
> > + HAS_PCH_CNP(dev_priv))
> > spt_irq_handler(dev_priv, iir);
> > else
> > cpt_irq_handler(dev_priv, iir);
> > @@ -3548,6 +3625,9 @@ static void gen11_irq_reset(struct drm_device
> > *dev)
> > GEN3_IRQ_RESET(GEN11_DE_HPD_);
> > GEN3_IRQ_RESET(GEN11_GU_MISC_);
> > GEN3_IRQ_RESET(GEN8_PCU_);
> > +
> > + if (HAS_PCH_ICP(dev_priv))
> > + GEN3_IRQ_RESET(ICP_SDE_);
> > }
> >
> > void gen8_irq_power_well_post_enable(struct drm_i915_private
> > *dev_priv,
> > @@ -3664,6 +3744,35 @@ static void ibx_hpd_irq_setup(struct
> > drm_i915_private *dev_priv)
> > ibx_hpd_detection_setup(dev_priv);
> > }
> >
> > +static void icp_hpd_detection_setup(struct drm_i915_private
> > *dev_priv)
> > +{
> > + u32 hotplug;
> > +
> > + hotplug = I915_READ(SHOTPLUG_CTL_DDI);
> > + hotplug |= ICP_DDIA_HPD_ENABLE |
> > + ICP_DDIB_HPD_ENABLE;
> > + I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
> > +
> > + hotplug = I915_READ(SHOTPLUG_CTL_TC);
> > + hotplug |= ICP_TC_HPD_ENABLE(PORT_TC1) |
> > + ICP_TC_HPD_ENABLE(PORT_TC2) |
> > + ICP_TC_HPD_ENABLE(PORT_TC3) |
> > + ICP_TC_HPD_ENABLE(PORT_TC4);
> > + I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
> > +}
> > +
> > +static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> > +{
> > + u32 hotplug_irqs, enabled_irqs;
> > +
> > + hotplug_irqs = ICP_SDE_DDI_MASK | ICP_SDE_TC_MASK;
> > + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp);
> > +
> > + ibx_display_interrupt_update(dev_priv, hotplug_irqs,
> > enabled_irqs);
> > +
> > + icp_hpd_detection_setup(dev_priv);
> > +}
> > +
> > static void gen11_hpd_detection_setup(struct drm_i915_private
> > *dev_priv)
> > {
> > u32 hotplug;
> > @@ -3690,6 +3799,9 @@ static void gen11_hpd_irq_setup(struct
> > drm_i915_private *dev_priv)
> > POSTING_READ(GEN11_DE_HPD_IMR);
> >
> > gen11_hpd_detection_setup(dev_priv);
> > +
> > + if (HAS_PCH_ICP(dev_priv))
> > + icp_hpd_irq_setup(dev_priv);
> > }
> >
> > static void spt_hpd_detection_setup(struct drm_i915_private
> > *dev_priv)
> > @@ -4121,11 +4233,29 @@ static void gen11_gt_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> > }
> >
> > +static void icp_irq_postinstall(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + u32 mask = ICP_GMBUS;
> > +
> > + WARN_ON(I915_READ(ICP_SDE_IER) != 0);
> > + I915_WRITE(ICP_SDE_IER, 0xffffffff);
> > + POSTING_READ(ICP_SDE_IER);
> > +
> > + gen3_assert_iir_is_zero(dev_priv, ICP_SDE_IIR);
> > + I915_WRITE(ICP_SDE_IMR, ~mask);
> > +
> > + icp_hpd_detection_setup(dev_priv);
> > +}
> > +
> > static int gen11_irq_postinstall(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> >
> > + if (HAS_PCH_ICP(dev_priv))
> > + icp_irq_postinstall(dev);
> > +
> > gen11_gt_irq_postinstall(dev_priv);
> > gen8_de_irq_postinstall(dev_priv);
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 19600097581f..28ce96ce0484 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7460,6 +7460,46 @@ enum {
> > #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
> > #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
> >
> > +/* ICP */
> > +#define ICP_SDE_ISR _MMIO(0xc4000)
> > +#define ICP_SDE_IMR _MMIO(0xc4004)
> > +#define ICP_SDE_IIR _MMIO(0xc4008)
> > +#define ICP_SDE_IER _MMIO(0xc400c)
> These are exactly the same registers as SDE{ISR,IMR,IIR,IER}. For all
> the other platforms what we do is rather postfix the platform name.
>
> I think we should follow what they do here.
>
>
> >
> > +#define ICP_TC4_HOTPLUG (1 << 27)
> > +#define ICP_TC3_HOTPLUG (1 << 26)
> > +#define ICP_TC2_HOTPLUG (1 << 25)
> > +#define ICP_TC1_HOTPLUG (1 << 24)
> > +#define ICP_GMBUS (1 << 23)
> > +#define ICP_DDIB_HOTPLUG (1 << 17)
> > +#define ICP_DDIA_HOTPLUG (1 << 16)
> so these would become SDE_TC4_HOTPLUG_ICP and so on.
>
The reason I preferred this naming for gen-11 is it is symmetric to the
corresponding definitions in the north engine.
For example,
+#define GEN11_DE_HPD_ISR _MMIO(0x44470)
+#define GEN11_DE_HPD_IMR _MMIO(0x44474)
+#define GEN11_DE_HPD_IIR _MMIO(0x44478)
+#define GEN11_DE_HPD_IER _MMIO(0x4447c)
+#define GEN11_TC4_HOTPLUG (1 << 19)
+#define GEN11_TC3_HOTPLUG (1 << 18)
+#define GEN11_TC2_HOTPLUG (1 << 17)
+#define GEN11_TC1_HOTPLUG (1 << 16)
With interrupts getting routed to north or south engines for the same
port, this naming scheme makes the duality clearer IMO.
> >
> > +
> > +#define ICP_SDE_DDI_MASK (ICP_DDIB_HOTPLUG |
> > \
> > + ICP_DDIA_HOTPLUG)
> > +
> > +#define ICP_SDE_TC_MASK (ICP_TC4_HOTPLUG |
> > \
> > + ICP_TC3_HOTPLUG |
> > \
> > + ICP_TC2_HOTPLUG |
> > \
> > + ICP_TC1_HOTPLUG)
> > +
> > +#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
> > /* SHOTPLUG_CTL */
> This also seems to reuse what we have defined as PCH_PORT_HOTPLUG
> with a
> comment to SHOTPLUG_CTL there, although here I tend to be in favor of
> using the current real name of the register (SHOTPLUG_CTL).
The real name I see is SHOTPLUG_CTL_DDI for ICP.
I don't believe we should attempt to make these definitions consistent
with previous platforms over making them consistent with each other.
>
> The rest looks good to me.
>
> Lucas De Marchi
>
> >
> > +#define ICP_DDIB_HPD_ENABLE (1 << 7)
> > +#define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
> > +#define ICP_DDIB_HPD_NO_DETECT (0 << 4)
> > +#define ICP_DDIB_HPD_SHORT_DETECT (1 << 4)
> > +#define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
> > +#define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
> > +#define ICP_DDIA_HPD_ENABLE (1 << 3)
> > +#define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
> > +#define ICP_DDIA_HPD_NO_DETECT (0 << 0)
> > +#define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
> > +#define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
> > +#define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
> > +
> > +#define SHOTPLUG_CTL_TC _MMIO(0xc40
> > 34)
> > +#define ICP_TC_HPD_ENABLE(tc_port) (8 <<
> > (tc_port) * 4)
> > +#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) *
> > 4)
> > +#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port)
> > * 4)
> > +
> > #define PCH_GPIOA _MMIO(0xc5010)
> > #define PCH_GPIOB _MMIO(0xc5014)
> > #define PCH_GPIOC _MMIO(0xc5018)
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^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 05/24] drm/i915/icp: Add Interrupt Support
2018-05-25 0:45 ` Dhinakaran Pandiyan
@ 2018-05-25 0:43 ` Lucas De Marchi
2018-05-30 0:04 ` Lucas De Marchi
0 siblings, 1 reply; 127+ messages in thread
From: Lucas De Marchi @ 2018-05-25 0:43 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx, Paulo Zanoni
On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan wrote:
> On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > >
> > > From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > >
> > > This patch addresses Interrupts from south display engine (SDE).
> > >
> > > ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> > > Introduce these registers and their intended values.
> > >
> > > Introduce icp_irq_handler().
> > >
> > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > [Paulo: coding style bikesheds and rebases].
> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 134
> > > +++++++++++++++++++++++++++++++++++++++-
> > > drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++
> > > 2 files changed, 172 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 9bcec5fdb9d0..6b109991786f 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -122,6 +122,15 @@ static const u32 hpd_tc_gen11[HPD_NUM_PINS] =
> > > {
> > > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > > };
> > >
> > > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > > +};
> > > +
> > > /* IIR can theoretically queue up two events. Be paranoid. */
> > > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > > I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
> > > @@ -1586,6 +1595,34 @@ static bool
> > > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > > }
> > > }
> > >
> > > +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32
> > > val)
> > > +{
> > > + switch (port) {
> > > + case PORT_A:
> > > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > > + case PORT_B:
> > > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > > + default:
> > > + return false;
> > > + }
> > > +}
> > > +
> > > +static bool icp_tc_port_hotplug_long_detect(enum port port, u32
> > > val)
> > > +{
> > > + switch (port) {
> > > + case PORT_C:
> > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > > + case PORT_D:
> > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > > + case PORT_E:
> > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > > + case PORT_F:
> > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > > + default:
> > > + return false;
> > > + }
> > > +}
> > > +
> > > static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
> > > {
> > > switch (port) {
> > > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > > drm_i915_private *dev_priv, u32 pch_iir)
> > > cpt_serr_int_handler(dev_priv);
> > > }
> > >
> > > +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32
> > > pch_iir)
> > > +{
> > > + u32 ddi_hotplug_trigger = pch_iir & ICP_SDE_DDI_MASK;
> > > + u32 tc_hotplug_trigger = pch_iir & ICP_SDE_TC_MASK;
> > > + u32 pin_mask = 0, long_mask = 0;
> > > +
> > > + if (ddi_hotplug_trigger) {
> > > + u32 dig_hotplug_reg;
> > > +
> > > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> > > + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> > > +
> > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > &long_mask,
> > > + ddi_hotplug_trigger,
> > > + dig_hotplug_reg, hpd_icp,
> > > + icp_ddi_port_hotplug_long_detec
> > > t);
> > > + }
> > > +
> > > + if (tc_hotplug_trigger) {
> > > + u32 dig_hotplug_reg;
> > > +
> > > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> > > + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> > > +
> > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > &long_mask,
> > > + tc_hotplug_trigger,
> > > + dig_hotplug_reg, hpd_icp,
> > > + icp_tc_port_hotplug_long_detect
> > > );
> > > + }
> > > +
> > > + if (pin_mask)
> > > + intel_hpd_irq_handler(dev_priv, pin_mask,
> > > long_mask);
> > > +
> > > + if (pch_iir & ICP_GMBUS)
> > > + gmbus_irq_handler(dev_priv);
> > > +}
> > > +
> > > static void spt_irq_handler(struct drm_i915_private *dev_priv, u32
> > > pch_iir)
> > > {
> > > u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
> > > @@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct drm_i915_private
> > > *dev_priv, u32 master_ctl)
> > > I915_WRITE(SDEIIR, iir);
> > > ret = IRQ_HANDLED;
> > >
> > > - if (HAS_PCH_SPT(dev_priv) ||
> > > HAS_PCH_KBP(dev_priv) ||
> > > - HAS_PCH_CNP(dev_priv))
> > > + if (HAS_PCH_ICP(dev_priv))
> > > + icp_irq_handler(dev_priv, iir);
> > > + else if (HAS_PCH_SPT(dev_priv) ||
> > > + HAS_PCH_KBP(dev_priv) ||
> > > + HAS_PCH_CNP(dev_priv))
> > > spt_irq_handler(dev_priv, iir);
> > > else
> > > cpt_irq_handler(dev_priv, iir);
> > > @@ -3548,6 +3625,9 @@ static void gen11_irq_reset(struct drm_device
> > > *dev)
> > > GEN3_IRQ_RESET(GEN11_DE_HPD_);
> > > GEN3_IRQ_RESET(GEN11_GU_MISC_);
> > > GEN3_IRQ_RESET(GEN8_PCU_);
> > > +
> > > + if (HAS_PCH_ICP(dev_priv))
> > > + GEN3_IRQ_RESET(ICP_SDE_);
> > > }
> > >
> > > void gen8_irq_power_well_post_enable(struct drm_i915_private
> > > *dev_priv,
> > > @@ -3664,6 +3744,35 @@ static void ibx_hpd_irq_setup(struct
> > > drm_i915_private *dev_priv)
> > > ibx_hpd_detection_setup(dev_priv);
> > > }
> > >
> > > +static void icp_hpd_detection_setup(struct drm_i915_private
> > > *dev_priv)
> > > +{
> > > + u32 hotplug;
> > > +
> > > + hotplug = I915_READ(SHOTPLUG_CTL_DDI);
> > > + hotplug |= ICP_DDIA_HPD_ENABLE |
> > > + ICP_DDIB_HPD_ENABLE;
> > > + I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
> > > +
> > > + hotplug = I915_READ(SHOTPLUG_CTL_TC);
> > > + hotplug |= ICP_TC_HPD_ENABLE(PORT_TC1) |
> > > + ICP_TC_HPD_ENABLE(PORT_TC2) |
> > > + ICP_TC_HPD_ENABLE(PORT_TC3) |
> > > + ICP_TC_HPD_ENABLE(PORT_TC4);
> > > + I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
> > > +}
> > > +
> > > +static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> > > +{
> > > + u32 hotplug_irqs, enabled_irqs;
> > > +
> > > + hotplug_irqs = ICP_SDE_DDI_MASK | ICP_SDE_TC_MASK;
> > > + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp);
> > > +
> > > + ibx_display_interrupt_update(dev_priv, hotplug_irqs,
> > > enabled_irqs);
> > > +
> > > + icp_hpd_detection_setup(dev_priv);
> > > +}
> > > +
> > > static void gen11_hpd_detection_setup(struct drm_i915_private
> > > *dev_priv)
> > > {
> > > u32 hotplug;
> > > @@ -3690,6 +3799,9 @@ static void gen11_hpd_irq_setup(struct
> > > drm_i915_private *dev_priv)
> > > POSTING_READ(GEN11_DE_HPD_IMR);
> > >
> > > gen11_hpd_detection_setup(dev_priv);
> > > +
> > > + if (HAS_PCH_ICP(dev_priv))
> > > + icp_hpd_irq_setup(dev_priv);
> > > }
> > >
> > > static void spt_hpd_detection_setup(struct drm_i915_private
> > > *dev_priv)
> > > @@ -4121,11 +4233,29 @@ static void gen11_gt_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> > > }
> > >
> > > +static void icp_irq_postinstall(struct drm_device *dev)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > + u32 mask = ICP_GMBUS;
> > > +
> > > + WARN_ON(I915_READ(ICP_SDE_IER) != 0);
> > > + I915_WRITE(ICP_SDE_IER, 0xffffffff);
> > > + POSTING_READ(ICP_SDE_IER);
> > > +
> > > + gen3_assert_iir_is_zero(dev_priv, ICP_SDE_IIR);
> > > + I915_WRITE(ICP_SDE_IMR, ~mask);
> > > +
> > > + icp_hpd_detection_setup(dev_priv);
> > > +}
> > > +
> > > static int gen11_irq_postinstall(struct drm_device *dev)
> > > {
> > > struct drm_i915_private *dev_priv = dev->dev_private;
> > > u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> > >
> > > + if (HAS_PCH_ICP(dev_priv))
> > > + icp_irq_postinstall(dev);
> > > +
> > > gen11_gt_irq_postinstall(dev_priv);
> > > gen8_de_irq_postinstall(dev_priv);
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 19600097581f..28ce96ce0484 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7460,6 +7460,46 @@ enum {
> > > #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
> > > #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
> > >
> > > +/* ICP */
> > > +#define ICP_SDE_ISR _MMIO(0xc4000)
> > > +#define ICP_SDE_IMR _MMIO(0xc4004)
> > > +#define ICP_SDE_IIR _MMIO(0xc4008)
> > > +#define ICP_SDE_IER _MMIO(0xc400c)
> > These are exactly the same registers as SDE{ISR,IMR,IIR,IER}. For all
> > the other platforms what we do is rather postfix the platform name.
> >
> > I think we should follow what they do here.
> >
> >
> > >
> > > +#define ICP_TC4_HOTPLUG (1 << 27)
> > > +#define ICP_TC3_HOTPLUG (1 << 26)
> > > +#define ICP_TC2_HOTPLUG (1 << 25)
> > > +#define ICP_TC1_HOTPLUG (1 << 24)
> > > +#define ICP_GMBUS (1 << 23)
> > > +#define ICP_DDIB_HOTPLUG (1 << 17)
> > > +#define ICP_DDIA_HOTPLUG (1 << 16)
> > so these would become SDE_TC4_HOTPLUG_ICP and so on.
> >
>
> The reason I preferred this naming for gen-11 is it is symmetric to the
> corresponding definitions in the north engine.
>
> For example,
> +#define GEN11_DE_HPD_ISR _MMIO(0x44470)
> +#define GEN11_DE_HPD_IMR _MMIO(0x44474)
> +#define GEN11_DE_HPD_IIR _MMIO(0x44478)
> +#define GEN11_DE_HPD_IER _MMIO(0x4447c)
> +#define GEN11_TC4_HOTPLUG (1 << 19)
> +#define GEN11_TC3_HOTPLUG (1 << 18)
> +#define GEN11_TC2_HOTPLUG (1 << 17)
> +#define GEN11_TC1_HOTPLUG (1 << 16)
>
> With interrupts getting routed to north or south engines for the same
> port, this naming scheme makes the duality clearer IMO.
Still the register is the same as SDEISR and there are places in which we
read it expecting to be the same number.
Only the bits are different, so name the bits differently as it is for
other platforms. I think of the symmetry here just and accident of
life expecting to be different if north and south engines don't have the
same ports.
Lucas De Marchi
>
>
> > >
> > > +
> > > +#define ICP_SDE_DDI_MASK (ICP_DDIB_HOTPLUG |
> > > \
> > > + ICP_DDIA_HOTPLUG)
> > > +
> > > +#define ICP_SDE_TC_MASK (ICP_TC4_HOTPLUG |
> > > \
> > > + ICP_TC3_HOTPLUG |
> > > \
> > > + ICP_TC2_HOTPLUG |
> > > \
> > > + ICP_TC1_HOTPLUG)
> > > +
> > > +#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
> > > /* SHOTPLUG_CTL */
> > This also seems to reuse what we have defined as PCH_PORT_HOTPLUG
> > with a
> > comment to SHOTPLUG_CTL there, although here I tend to be in favor of
> > using the current real name of the register (SHOTPLUG_CTL).
>
> The real name I see is SHOTPLUG_CTL_DDI for ICP.
>
> I don't believe we should attempt to make these definitions consistent
> with previous platforms over making them consistent with each other.
>
>
> >
> > The rest looks good to me.
> >
> > Lucas De Marchi
> >
> > >
> > > +#define ICP_DDIB_HPD_ENABLE (1 << 7)
> > > +#define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
> > > +#define ICP_DDIB_HPD_NO_DETECT (0 << 4)
> > > +#define ICP_DDIB_HPD_SHORT_DETECT (1 << 4)
> > > +#define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
> > > +#define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
> > > +#define ICP_DDIA_HPD_ENABLE (1 << 3)
> > > +#define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
> > > +#define ICP_DDIA_HPD_NO_DETECT (0 << 0)
> > > +#define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
> > > +#define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
> > > +#define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
> > > +
> > > +#define SHOTPLUG_CTL_TC _MMIO(0xc40
> > > 34)
> > > +#define ICP_TC_HPD_ENABLE(tc_port) (8 <<
> > > (tc_port) * 4)
> > > +#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) *
> > > 4)
> > > +#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port)
> > > * 4)
> > > +
> > > #define PCH_GPIOA _MMIO(0xc5010)
> > > #define PCH_GPIOB _MMIO(0xc5014)
> > > #define PCH_GPIOC _MMIO(0xc5018)
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^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 05/24] drm/i915/icp: Add Interrupt Support
2018-05-25 0:43 ` Lucas De Marchi
@ 2018-05-30 0:04 ` Lucas De Marchi
2018-06-13 22:23 ` Lucas De Marchi
0 siblings, 1 reply; 127+ messages in thread
From: Lucas De Marchi @ 2018-05-30 0:04 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx, Paulo Zanoni
On Thu, May 24, 2018 at 05:43:24PM -0700, Lucas De Marchi wrote:
> On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan wrote:
> > On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > > >
> > > > From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > >
> > > > This patch addresses Interrupts from south display engine (SDE).
> > > >
> > > > ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> > > > Introduce these registers and their intended values.
> > > >
> > > > Introduce icp_irq_handler().
> > > >
> > > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > > [Paulo: coding style bikesheds and rebases].
> > > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/i915_irq.c | 134
> > > > +++++++++++++++++++++++++++++++++++++++-
> > > > drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++
> > > > 2 files changed, 172 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > index 9bcec5fdb9d0..6b109991786f 100644
> > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > @@ -122,6 +122,15 @@ static const u32 hpd_tc_gen11[HPD_NUM_PINS] =
> > > > {
> > > > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > > > };
> > > >
> > > > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > > > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > > > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > > > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > > > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > > > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > > > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > > > +};
> > > > +
> > > > /* IIR can theoretically queue up two events. Be paranoid. */
> > > > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > > > I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
> > > > @@ -1586,6 +1595,34 @@ static bool
> > > > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > > > }
> > > > }
> > > >
> > > > +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32
> > > > val)
> > > > +{
> > > > + switch (port) {
> > > > + case PORT_A:
> > > > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > > > + case PORT_B:
> > > > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > > > + default:
> > > > + return false;
> > > > + }
> > > > +}
> > > > +
> > > > +static bool icp_tc_port_hotplug_long_detect(enum port port, u32
> > > > val)
> > > > +{
> > > > + switch (port) {
> > > > + case PORT_C:
> > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > > > + case PORT_D:
> > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > > > + case PORT_E:
> > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > > > + case PORT_F:
> > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > > > + default:
> > > > + return false;
> > > > + }
> > > > +}
> > > > +
> > > > static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
> > > > {
> > > > switch (port) {
> > > > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > > > drm_i915_private *dev_priv, u32 pch_iir)
> > > > cpt_serr_int_handler(dev_priv);
> > > > }
> > > >
> > > > +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32
> > > > pch_iir)
> > > > +{
> > > > + u32 ddi_hotplug_trigger = pch_iir & ICP_SDE_DDI_MASK;
> > > > + u32 tc_hotplug_trigger = pch_iir & ICP_SDE_TC_MASK;
> > > > + u32 pin_mask = 0, long_mask = 0;
> > > > +
> > > > + if (ddi_hotplug_trigger) {
> > > > + u32 dig_hotplug_reg;
> > > > +
> > > > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> > > > + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> > > > +
> > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > &long_mask,
> > > > + ddi_hotplug_trigger,
> > > > + dig_hotplug_reg, hpd_icp,
> > > > + icp_ddi_port_hotplug_long_detec
> > > > t);
> > > > + }
> > > > +
> > > > + if (tc_hotplug_trigger) {
> > > > + u32 dig_hotplug_reg;
> > > > +
> > > > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> > > > + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> > > > +
> > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > &long_mask,
> > > > + tc_hotplug_trigger,
> > > > + dig_hotplug_reg, hpd_icp,
> > > > + icp_tc_port_hotplug_long_detect
> > > > );
> > > > + }
> > > > +
> > > > + if (pin_mask)
> > > > + intel_hpd_irq_handler(dev_priv, pin_mask,
> > > > long_mask);
> > > > +
> > > > + if (pch_iir & ICP_GMBUS)
> > > > + gmbus_irq_handler(dev_priv);
> > > > +}
> > > > +
> > > > static void spt_irq_handler(struct drm_i915_private *dev_priv, u32
> > > > pch_iir)
> > > > {
> > > > u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
> > > > @@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct drm_i915_private
> > > > *dev_priv, u32 master_ctl)
> > > > I915_WRITE(SDEIIR, iir);
> > > > ret = IRQ_HANDLED;
> > > >
> > > > - if (HAS_PCH_SPT(dev_priv) ||
> > > > HAS_PCH_KBP(dev_priv) ||
> > > > - HAS_PCH_CNP(dev_priv))
> > > > + if (HAS_PCH_ICP(dev_priv))
> > > > + icp_irq_handler(dev_priv, iir);
to be clear on what I was saying... See the context just above: we read
and write SDEIIR to get/clear the interrupt bits. Yet you are defining a
ICP_SDE_IIR that has to be the same value. To avoid any confusion, I
think it's better to stay with SDEIIR and just change the bit
definition.
> > > > + else if (HAS_PCH_SPT(dev_priv) ||
> > > > + HAS_PCH_KBP(dev_priv) ||
> > > > + HAS_PCH_CNP(dev_priv))
> > > > spt_irq_handler(dev_priv, iir);
> > > > else
> > > > cpt_irq_handler(dev_priv, iir);
> > > > @@ -3548,6 +3625,9 @@ static void gen11_irq_reset(struct drm_device
> > > > *dev)
> > > > GEN3_IRQ_RESET(GEN11_DE_HPD_);
> > > > GEN3_IRQ_RESET(GEN11_GU_MISC_);
> > > > GEN3_IRQ_RESET(GEN8_PCU_);
> > > > +
> > > > + if (HAS_PCH_ICP(dev_priv))
> > > > + GEN3_IRQ_RESET(ICP_SDE_);
> > > > }
> > > >
> > > > void gen8_irq_power_well_post_enable(struct drm_i915_private
> > > > *dev_priv,
> > > > @@ -3664,6 +3744,35 @@ static void ibx_hpd_irq_setup(struct
> > > > drm_i915_private *dev_priv)
> > > > ibx_hpd_detection_setup(dev_priv);
> > > > }
> > > >
> > > > +static void icp_hpd_detection_setup(struct drm_i915_private
> > > > *dev_priv)
> > > > +{
> > > > + u32 hotplug;
> > > > +
> > > > + hotplug = I915_READ(SHOTPLUG_CTL_DDI);
> > > > + hotplug |= ICP_DDIA_HPD_ENABLE |
> > > > + ICP_DDIB_HPD_ENABLE;
> > > > + I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
> > > > +
> > > > + hotplug = I915_READ(SHOTPLUG_CTL_TC);
> > > > + hotplug |= ICP_TC_HPD_ENABLE(PORT_TC1) |
> > > > + ICP_TC_HPD_ENABLE(PORT_TC2) |
> > > > + ICP_TC_HPD_ENABLE(PORT_TC3) |
> > > > + ICP_TC_HPD_ENABLE(PORT_TC4);
> > > > + I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
> > > > +}
> > > > +
> > > > +static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> > > > +{
> > > > + u32 hotplug_irqs, enabled_irqs;
> > > > +
> > > > + hotplug_irqs = ICP_SDE_DDI_MASK | ICP_SDE_TC_MASK;
> > > > + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp);
> > > > +
> > > > + ibx_display_interrupt_update(dev_priv, hotplug_irqs,
> > > > enabled_irqs);
> > > > +
> > > > + icp_hpd_detection_setup(dev_priv);
> > > > +}
> > > > +
> > > > static void gen11_hpd_detection_setup(struct drm_i915_private
> > > > *dev_priv)
> > > > {
> > > > u32 hotplug;
> > > > @@ -3690,6 +3799,9 @@ static void gen11_hpd_irq_setup(struct
> > > > drm_i915_private *dev_priv)
> > > > POSTING_READ(GEN11_DE_HPD_IMR);
> > > >
> > > > gen11_hpd_detection_setup(dev_priv);
> > > > +
> > > > + if (HAS_PCH_ICP(dev_priv))
> > > > + icp_hpd_irq_setup(dev_priv);
> > > > }
> > > >
> > > > static void spt_hpd_detection_setup(struct drm_i915_private
> > > > *dev_priv)
> > > > @@ -4121,11 +4233,29 @@ static void gen11_gt_irq_postinstall(struct
> > > > drm_i915_private *dev_priv)
> > > > I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> > > > }
> > > >
> > > > +static void icp_irq_postinstall(struct drm_device *dev)
> > > > +{
> > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > + u32 mask = ICP_GMBUS;
> > > > +
> > > > + WARN_ON(I915_READ(ICP_SDE_IER) != 0);
> > > > + I915_WRITE(ICP_SDE_IER, 0xffffffff);
> > > > + POSTING_READ(ICP_SDE_IER);
> > > > +
> > > > + gen3_assert_iir_is_zero(dev_priv, ICP_SDE_IIR);
> > > > + I915_WRITE(ICP_SDE_IMR, ~mask);
> > > > +
> > > > + icp_hpd_detection_setup(dev_priv);
> > > > +}
> > > > +
> > > > static int gen11_irq_postinstall(struct drm_device *dev)
> > > > {
> > > > struct drm_i915_private *dev_priv = dev->dev_private;
> > > > u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> > > >
> > > > + if (HAS_PCH_ICP(dev_priv))
> > > > + icp_irq_postinstall(dev);
> > > > +
> > > > gen11_gt_irq_postinstall(dev_priv);
> > > > gen8_de_irq_postinstall(dev_priv);
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 19600097581f..28ce96ce0484 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -7460,6 +7460,46 @@ enum {
> > > > #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
> > > > #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
> > > >
> > > > +/* ICP */
> > > > +#define ICP_SDE_ISR _MMIO(0xc4000)
> > > > +#define ICP_SDE_IMR _MMIO(0xc4004)
> > > > +#define ICP_SDE_IIR _MMIO(0xc4008)
> > > > +#define ICP_SDE_IER _MMIO(0xc400c)
> > > These are exactly the same registers as SDE{ISR,IMR,IIR,IER}. For all
> > > the other platforms what we do is rather postfix the platform name.
> > >
> > > I think we should follow what they do here.
> > >
> > >
> > > >
> > > > +#define ICP_TC4_HOTPLUG (1 << 27)
> > > > +#define ICP_TC3_HOTPLUG (1 << 26)
> > > > +#define ICP_TC2_HOTPLUG (1 << 25)
> > > > +#define ICP_TC1_HOTPLUG (1 << 24)
> > > > +#define ICP_GMBUS (1 << 23)
> > > > +#define ICP_DDIB_HOTPLUG (1 << 17)
> > > > +#define ICP_DDIA_HOTPLUG (1 << 16)
> > > so these would become SDE_TC4_HOTPLUG_ICP and so on.
> > >
> >
> > The reason I preferred this naming for gen-11 is it is symmetric to the
> > corresponding definitions in the north engine.
> >
> > For example,
> > +#define GEN11_DE_HPD_ISR _MMIO(0x44470)
> > +#define GEN11_DE_HPD_IMR _MMIO(0x44474)
> > +#define GEN11_DE_HPD_IIR _MMIO(0x44478)
> > +#define GEN11_DE_HPD_IER _MMIO(0x4447c)
> > +#define GEN11_TC4_HOTPLUG (1 << 19)
> > +#define GEN11_TC3_HOTPLUG (1 << 18)
> > +#define GEN11_TC2_HOTPLUG (1 << 17)
> > +#define GEN11_TC1_HOTPLUG (1 << 16)
> >
> > With interrupts getting routed to north or south engines for the same
> > port, this naming scheme makes the duality clearer IMO.
>
> Still the register is the same as SDEISR and there are places in which we
> read it expecting to be the same number.
>
> Only the bits are different, so name the bits differently as it is for
> other platforms. I think of the symmetry here just and accident of
> life expecting to be different if north and south engines don't have the
> same ports.
This is on gen8_de_irq_handler() which is still used for gen11.
Lucas De Marchi
>
> Lucas De Marchi
>
> >
> >
> > > >
> > > > +
> > > > +#define ICP_SDE_DDI_MASK (ICP_DDIB_HOTPLUG |
> > > > \
> > > > + ICP_DDIA_HOTPLUG)
> > > > +
> > > > +#define ICP_SDE_TC_MASK (ICP_TC4_HOTPLUG |
> > > > \
> > > > + ICP_TC3_HOTPLUG |
> > > > \
> > > > + ICP_TC2_HOTPLUG |
> > > > \
> > > > + ICP_TC1_HOTPLUG)
> > > > +
> > > > +#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
> > > > /* SHOTPLUG_CTL */
> > > This also seems to reuse what we have defined as PCH_PORT_HOTPLUG
> > > with a
> > > comment to SHOTPLUG_CTL there, although here I tend to be in favor of
> > > using the current real name of the register (SHOTPLUG_CTL).
> >
> > The real name I see is SHOTPLUG_CTL_DDI for ICP.
> >
> > I don't believe we should attempt to make these definitions consistent
> > with previous platforms over making them consistent with each other.
> >
> >
> > >
> > > The rest looks good to me.
> > >
> > > Lucas De Marchi
> > >
> > > >
> > > > +#define ICP_DDIB_HPD_ENABLE (1 << 7)
> > > > +#define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
> > > > +#define ICP_DDIB_HPD_NO_DETECT (0 << 4)
> > > > +#define ICP_DDIB_HPD_SHORT_DETECT (1 << 4)
> > > > +#define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
> > > > +#define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
> > > > +#define ICP_DDIA_HPD_ENABLE (1 << 3)
> > > > +#define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
> > > > +#define ICP_DDIA_HPD_NO_DETECT (0 << 0)
> > > > +#define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
> > > > +#define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
> > > > +#define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
> > > > +
> > > > +#define SHOTPLUG_CTL_TC _MMIO(0xc40
> > > > 34)
> > > > +#define ICP_TC_HPD_ENABLE(tc_port) (8 <<
> > > > (tc_port) * 4)
> > > > +#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) *
> > > > 4)
> > > > +#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port)
> > > > * 4)
> > > > +
> > > > #define PCH_GPIOA _MMIO(0xc5010)
> > > > #define PCH_GPIOB _MMIO(0xc5014)
> > > > #define PCH_GPIOC _MMIO(0xc5018)
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^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 05/24] drm/i915/icp: Add Interrupt Support
2018-05-30 0:04 ` Lucas De Marchi
@ 2018-06-13 22:23 ` Lucas De Marchi
2018-06-14 0:04 ` Paulo Zanoni
2018-06-14 2:21 ` Dhinakaran Pandiyan
0 siblings, 2 replies; 127+ messages in thread
From: Lucas De Marchi @ 2018-06-13 22:23 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx, Paulo Zanoni
On Tue, May 29, 2018 at 05:04:58PM -0700, Lucas De Marchi wrote:
> On Thu, May 24, 2018 at 05:43:24PM -0700, Lucas De Marchi wrote:
> > On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan wrote:
> > > On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > > > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > > > >
> > > > > From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > > >
> > > > > This patch addresses Interrupts from south display engine (SDE).
> > > > >
> > > > > ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> > > > > Introduce these registers and their intended values.
> > > > >
> > > > > Introduce icp_irq_handler().
> > > > >
> > > > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > > > [Paulo: coding style bikesheds and rebases].
> > > > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/i915_irq.c | 134
> > > > > +++++++++++++++++++++++++++++++++++++++-
> > > > > drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++
> > > > > 2 files changed, 172 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > > index 9bcec5fdb9d0..6b109991786f 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > @@ -122,6 +122,15 @@ static const u32 hpd_tc_gen11[HPD_NUM_PINS] =
> > > > > {
> > > > > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > > > > };
> > > > >
> > > > > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > > > > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > > > > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > > > > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > > > > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > > > > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > > > > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > > > > +};
> > > > > +
> > > > > /* IIR can theoretically queue up two events. Be paranoid. */
> > > > > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > > > > I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
> > > > > @@ -1586,6 +1595,34 @@ static bool
> > > > > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > > > > }
> > > > > }
> > > > >
> > > > > +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32
> > > > > val)
> > > > > +{
> > > > > + switch (port) {
> > > > > + case PORT_A:
> > > > > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > > > > + case PORT_B:
> > > > > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > > > > + default:
> > > > > + return false;
> > > > > + }
> > > > > +}
> > > > > +
> > > > > +static bool icp_tc_port_hotplug_long_detect(enum port port, u32
> > > > > val)
> > > > > +{
> > > > > + switch (port) {
> > > > > + case PORT_C:
> > > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > > > > + case PORT_D:
> > > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > > > > + case PORT_E:
> > > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > > > > + case PORT_F:
> > > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > > > > + default:
> > > > > + return false;
> > > > > + }
> > > > > +}
> > > > > +
> > > > > static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
> > > > > {
> > > > > switch (port) {
> > > > > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > > > > drm_i915_private *dev_priv, u32 pch_iir)
> > > > > cpt_serr_int_handler(dev_priv);
> > > > > }
> > > > >
> > > > > +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32
> > > > > pch_iir)
> > > > > +{
> > > > > + u32 ddi_hotplug_trigger = pch_iir & ICP_SDE_DDI_MASK;
> > > > > + u32 tc_hotplug_trigger = pch_iir & ICP_SDE_TC_MASK;
> > > > > + u32 pin_mask = 0, long_mask = 0;
> > > > > +
> > > > > + if (ddi_hotplug_trigger) {
> > > > > + u32 dig_hotplug_reg;
> > > > > +
> > > > > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> > > > > + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> > > > > +
> > > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > > &long_mask,
> > > > > + ddi_hotplug_trigger,
> > > > > + dig_hotplug_reg, hpd_icp,
> > > > > + icp_ddi_port_hotplug_long_detec
> > > > > t);
> > > > > + }
> > > > > +
> > > > > + if (tc_hotplug_trigger) {
> > > > > + u32 dig_hotplug_reg;
> > > > > +
> > > > > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> > > > > + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> > > > > +
> > > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > > &long_mask,
> > > > > + tc_hotplug_trigger,
> > > > > + dig_hotplug_reg, hpd_icp,
> > > > > + icp_tc_port_hotplug_long_detect
> > > > > );
> > > > > + }
> > > > > +
> > > > > + if (pin_mask)
> > > > > + intel_hpd_irq_handler(dev_priv, pin_mask,
> > > > > long_mask);
> > > > > +
> > > > > + if (pch_iir & ICP_GMBUS)
> > > > > + gmbus_irq_handler(dev_priv);
> > > > > +}
> > > > > +
> > > > > static void spt_irq_handler(struct drm_i915_private *dev_priv, u32
> > > > > pch_iir)
> > > > > {
> > > > > u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
> > > > > @@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct drm_i915_private
> > > > > *dev_priv, u32 master_ctl)
> > > > > I915_WRITE(SDEIIR, iir);
> > > > > ret = IRQ_HANDLED;
> > > > >
> > > > > - if (HAS_PCH_SPT(dev_priv) ||
> > > > > HAS_PCH_KBP(dev_priv) ||
> > > > > - HAS_PCH_CNP(dev_priv))
> > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > + icp_irq_handler(dev_priv, iir);
>
> to be clear on what I was saying... See the context just above: we read
> and write SDEIIR to get/clear the interrupt bits. Yet you are defining a
> ICP_SDE_IIR that has to be the same value. To avoid any confusion, I
> think it's better to stay with SDEIIR and just change the bit
> definition.
Dk, any news on this?
Lucas De Marchi
>
>
> > > > > + else if (HAS_PCH_SPT(dev_priv) ||
> > > > > + HAS_PCH_KBP(dev_priv) ||
> > > > > + HAS_PCH_CNP(dev_priv))
> > > > > spt_irq_handler(dev_priv, iir);
> > > > > else
> > > > > cpt_irq_handler(dev_priv, iir);
> > > > > @@ -3548,6 +3625,9 @@ static void gen11_irq_reset(struct drm_device
> > > > > *dev)
> > > > > GEN3_IRQ_RESET(GEN11_DE_HPD_);
> > > > > GEN3_IRQ_RESET(GEN11_GU_MISC_);
> > > > > GEN3_IRQ_RESET(GEN8_PCU_);
> > > > > +
> > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > + GEN3_IRQ_RESET(ICP_SDE_);
> > > > > }
> > > > >
> > > > > void gen8_irq_power_well_post_enable(struct drm_i915_private
> > > > > *dev_priv,
> > > > > @@ -3664,6 +3744,35 @@ static void ibx_hpd_irq_setup(struct
> > > > > drm_i915_private *dev_priv)
> > > > > ibx_hpd_detection_setup(dev_priv);
> > > > > }
> > > > >
> > > > > +static void icp_hpd_detection_setup(struct drm_i915_private
> > > > > *dev_priv)
> > > > > +{
> > > > > + u32 hotplug;
> > > > > +
> > > > > + hotplug = I915_READ(SHOTPLUG_CTL_DDI);
> > > > > + hotplug |= ICP_DDIA_HPD_ENABLE |
> > > > > + ICP_DDIB_HPD_ENABLE;
> > > > > + I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
> > > > > +
> > > > > + hotplug = I915_READ(SHOTPLUG_CTL_TC);
> > > > > + hotplug |= ICP_TC_HPD_ENABLE(PORT_TC1) |
> > > > > + ICP_TC_HPD_ENABLE(PORT_TC2) |
> > > > > + ICP_TC_HPD_ENABLE(PORT_TC3) |
> > > > > + ICP_TC_HPD_ENABLE(PORT_TC4);
> > > > > + I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
> > > > > +}
> > > > > +
> > > > > +static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> > > > > +{
> > > > > + u32 hotplug_irqs, enabled_irqs;
> > > > > +
> > > > > + hotplug_irqs = ICP_SDE_DDI_MASK | ICP_SDE_TC_MASK;
> > > > > + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp);
> > > > > +
> > > > > + ibx_display_interrupt_update(dev_priv, hotplug_irqs,
> > > > > enabled_irqs);
> > > > > +
> > > > > + icp_hpd_detection_setup(dev_priv);
> > > > > +}
> > > > > +
> > > > > static void gen11_hpd_detection_setup(struct drm_i915_private
> > > > > *dev_priv)
> > > > > {
> > > > > u32 hotplug;
> > > > > @@ -3690,6 +3799,9 @@ static void gen11_hpd_irq_setup(struct
> > > > > drm_i915_private *dev_priv)
> > > > > POSTING_READ(GEN11_DE_HPD_IMR);
> > > > >
> > > > > gen11_hpd_detection_setup(dev_priv);
> > > > > +
> > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > + icp_hpd_irq_setup(dev_priv);
> > > > > }
> > > > >
> > > > > static void spt_hpd_detection_setup(struct drm_i915_private
> > > > > *dev_priv)
> > > > > @@ -4121,11 +4233,29 @@ static void gen11_gt_irq_postinstall(struct
> > > > > drm_i915_private *dev_priv)
> > > > > I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> > > > > }
> > > > >
> > > > > +static void icp_irq_postinstall(struct drm_device *dev)
> > > > > +{
> > > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > + u32 mask = ICP_GMBUS;
> > > > > +
> > > > > + WARN_ON(I915_READ(ICP_SDE_IER) != 0);
> > > > > + I915_WRITE(ICP_SDE_IER, 0xffffffff);
> > > > > + POSTING_READ(ICP_SDE_IER);
> > > > > +
> > > > > + gen3_assert_iir_is_zero(dev_priv, ICP_SDE_IIR);
> > > > > + I915_WRITE(ICP_SDE_IMR, ~mask);
> > > > > +
> > > > > + icp_hpd_detection_setup(dev_priv);
> > > > > +}
> > > > > +
> > > > > static int gen11_irq_postinstall(struct drm_device *dev)
> > > > > {
> > > > > struct drm_i915_private *dev_priv = dev->dev_private;
> > > > > u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> > > > >
> > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > + icp_irq_postinstall(dev);
> > > > > +
> > > > > gen11_gt_irq_postinstall(dev_priv);
> > > > > gen8_de_irq_postinstall(dev_priv);
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > > index 19600097581f..28ce96ce0484 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > @@ -7460,6 +7460,46 @@ enum {
> > > > > #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
> > > > > #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
> > > > >
> > > > > +/* ICP */
> > > > > +#define ICP_SDE_ISR _MMIO(0xc4000)
> > > > > +#define ICP_SDE_IMR _MMIO(0xc4004)
> > > > > +#define ICP_SDE_IIR _MMIO(0xc4008)
> > > > > +#define ICP_SDE_IER _MMIO(0xc400c)
> > > > These are exactly the same registers as SDE{ISR,IMR,IIR,IER}. For all
> > > > the other platforms what we do is rather postfix the platform name.
> > > >
> > > > I think we should follow what they do here.
> > > >
> > > >
> > > > >
> > > > > +#define ICP_TC4_HOTPLUG (1 << 27)
> > > > > +#define ICP_TC3_HOTPLUG (1 << 26)
> > > > > +#define ICP_TC2_HOTPLUG (1 << 25)
> > > > > +#define ICP_TC1_HOTPLUG (1 << 24)
> > > > > +#define ICP_GMBUS (1 << 23)
> > > > > +#define ICP_DDIB_HOTPLUG (1 << 17)
> > > > > +#define ICP_DDIA_HOTPLUG (1 << 16)
> > > > so these would become SDE_TC4_HOTPLUG_ICP and so on.
> > > >
> > >
> > > The reason I preferred this naming for gen-11 is it is symmetric to the
> > > corresponding definitions in the north engine.
> > >
> > > For example,
> > > +#define GEN11_DE_HPD_ISR _MMIO(0x44470)
> > > +#define GEN11_DE_HPD_IMR _MMIO(0x44474)
> > > +#define GEN11_DE_HPD_IIR _MMIO(0x44478)
> > > +#define GEN11_DE_HPD_IER _MMIO(0x4447c)
> > > +#define GEN11_TC4_HOTPLUG (1 << 19)
> > > +#define GEN11_TC3_HOTPLUG (1 << 18)
> > > +#define GEN11_TC2_HOTPLUG (1 << 17)
> > > +#define GEN11_TC1_HOTPLUG (1 << 16)
> > >
> > > With interrupts getting routed to north or south engines for the same
> > > port, this naming scheme makes the duality clearer IMO.
> >
> > Still the register is the same as SDEISR and there are places in which we
> > read it expecting to be the same number.
> >
> > Only the bits are different, so name the bits differently as it is for
> > other platforms. I think of the symmetry here just and accident of
> > life expecting to be different if north and south engines don't have the
> > same ports.
>
> This is on gen8_de_irq_handler() which is still used for gen11.
>
> Lucas De Marchi
>
> >
> > Lucas De Marchi
> >
> > >
> > >
> > > > >
> > > > > +
> > > > > +#define ICP_SDE_DDI_MASK (ICP_DDIB_HOTPLUG |
> > > > > \
> > > > > + ICP_DDIA_HOTPLUG)
> > > > > +
> > > > > +#define ICP_SDE_TC_MASK (ICP_TC4_HOTPLUG |
> > > > > \
> > > > > + ICP_TC3_HOTPLUG |
> > > > > \
> > > > > + ICP_TC2_HOTPLUG |
> > > > > \
> > > > > + ICP_TC1_HOTPLUG)
> > > > > +
> > > > > +#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
> > > > > /* SHOTPLUG_CTL */
> > > > This also seems to reuse what we have defined as PCH_PORT_HOTPLUG
> > > > with a
> > > > comment to SHOTPLUG_CTL there, although here I tend to be in favor of
> > > > using the current real name of the register (SHOTPLUG_CTL).
> > >
> > > The real name I see is SHOTPLUG_CTL_DDI for ICP.
> > >
> > > I don't believe we should attempt to make these definitions consistent
> > > with previous platforms over making them consistent with each other.
> > >
> > >
> > > >
> > > > The rest looks good to me.
> > > >
> > > > Lucas De Marchi
> > > >
> > > > >
> > > > > +#define ICP_DDIB_HPD_ENABLE (1 << 7)
> > > > > +#define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
> > > > > +#define ICP_DDIB_HPD_NO_DETECT (0 << 4)
> > > > > +#define ICP_DDIB_HPD_SHORT_DETECT (1 << 4)
> > > > > +#define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
> > > > > +#define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
> > > > > +#define ICP_DDIA_HPD_ENABLE (1 << 3)
> > > > > +#define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
> > > > > +#define ICP_DDIA_HPD_NO_DETECT (0 << 0)
> > > > > +#define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
> > > > > +#define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
> > > > > +#define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
> > > > > +
> > > > > +#define SHOTPLUG_CTL_TC _MMIO(0xc40
> > > > > 34)
> > > > > +#define ICP_TC_HPD_ENABLE(tc_port) (8 <<
> > > > > (tc_port) * 4)
> > > > > +#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) *
> > > > > 4)
> > > > > +#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port)
> > > > > * 4)
> > > > > +
> > > > > #define PCH_GPIOA _MMIO(0xc5010)
> > > > > #define PCH_GPIOB _MMIO(0xc5014)
> > > > > #define PCH_GPIOC _MMIO(0xc5018)
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^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 05/24] drm/i915/icp: Add Interrupt Support
2018-06-13 22:23 ` Lucas De Marchi
@ 2018-06-14 0:04 ` Paulo Zanoni
2018-06-14 2:21 ` Dhinakaran Pandiyan
1 sibling, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-06-14 0:04 UTC (permalink / raw)
To: Lucas De Marchi, Dhinakaran Pandiyan; +Cc: intel-gfx
Em Qua, 2018-06-13 às 15:23 -0700, Lucas De Marchi escreveu:
> On Tue, May 29, 2018 at 05:04:58PM -0700, Lucas De Marchi wrote:
> > On Thu, May 24, 2018 at 05:43:24PM -0700, Lucas De Marchi wrote:
> > > On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan
> > > wrote:
> > > > On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > > > > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > > > > >
> > > > > > From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > > > >
> > > > > > This patch addresses Interrupts from south display engine
> > > > > > (SDE).
> > > > > >
> > > > > > ICP has two registers - SHOTPLUG_CTL_DDI and
> > > > > > SHOTPLUG_CTL_TC.
> > > > > > Introduce these registers and their intended values.
> > > > > >
> > > > > > Introduce icp_irq_handler().
> > > > > >
> > > > > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > > > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > > > > [Paulo: coding style bikesheds and rebases].
> > > > > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/i915_irq.c | 134
> > > > > > +++++++++++++++++++++++++++++++++++++++-
> > > > > > drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++
> > > > > > 2 files changed, 172 insertions(+), 2 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > index 9bcec5fdb9d0..6b109991786f 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > @@ -122,6 +122,15 @@ static const u32
> > > > > > hpd_tc_gen11[HPD_NUM_PINS] =
> > > > > > {
> > > > > > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > > > > > };
> > > > > >
> > > > > > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > > > > > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > > > > > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > > > > > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > > > > > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > > > > > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > > > > > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > > > > > +};
> > > > > > +
> > > > > > /* IIR can theoretically queue up two events. Be paranoid.
> > > > > > */
> > > > > > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > > > > > I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff);
> > > > > > \
> > > > > > @@ -1586,6 +1595,34 @@ static bool
> > > > > > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > > > > > }
> > > > > > }
> > > > > >
> > > > > > +static bool icp_ddi_port_hotplug_long_detect(enum port
> > > > > > port, u32
> > > > > > val)
> > > > > > +{
> > > > > > + switch (port) {
> > > > > > + case PORT_A:
> > > > > > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > > > > > + case PORT_B:
> > > > > > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > > > > > + default:
> > > > > > + return false;
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > > > +static bool icp_tc_port_hotplug_long_detect(enum port
> > > > > > port, u32
> > > > > > val)
> > > > > > +{
> > > > > > + switch (port) {
> > > > > > + case PORT_C:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > > > > > + case PORT_D:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > > > > > + case PORT_E:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > > > > > + case PORT_F:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > > > > > + default:
> > > > > > + return false;
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > > > static bool spt_port_hotplug2_long_detect(enum port port,
> > > > > > u32 val)
> > > > > > {
> > > > > > switch (port) {
> > > > > > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > > > > > drm_i915_private *dev_priv, u32 pch_iir)
> > > > > > cpt_serr_int_handler(dev_priv);
> > > > > > }
> > > > > >
> > > > > > +static void icp_irq_handler(struct drm_i915_private
> > > > > > *dev_priv, u32
> > > > > > pch_iir)
> > > > > > +{
> > > > > > + u32 ddi_hotplug_trigger = pch_iir &
> > > > > > ICP_SDE_DDI_MASK;
> > > > > > + u32 tc_hotplug_trigger = pch_iir &
> > > > > > ICP_SDE_TC_MASK;
> > > > > > + u32 pin_mask = 0, long_mask = 0;
> > > > > > +
> > > > > > + if (ddi_hotplug_trigger) {
> > > > > > + u32 dig_hotplug_reg;
> > > > > > +
> > > > > > + dig_hotplug_reg =
> > > > > > I915_READ(SHOTPLUG_CTL_DDI);
> > > > > > + I915_WRITE(SHOTPLUG_CTL_DDI,
> > > > > > dig_hotplug_reg);
> > > > > > +
> > > > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > > > &long_mask,
> > > > > > + ddi_hotplug_trigger,
> > > > > > + dig_hotplug_reg,
> > > > > > hpd_icp,
> > > > > > + icp_ddi_port_hotplug_lo
> > > > > > ng_detec
> > > > > > t);
> > > > > > + }
> > > > > > +
> > > > > > + if (tc_hotplug_trigger) {
> > > > > > + u32 dig_hotplug_reg;
> > > > > > +
> > > > > > + dig_hotplug_reg =
> > > > > > I915_READ(SHOTPLUG_CTL_TC);
> > > > > > + I915_WRITE(SHOTPLUG_CTL_TC,
> > > > > > dig_hotplug_reg);
> > > > > > +
> > > > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > > > &long_mask,
> > > > > > + tc_hotplug_trigger,
> > > > > > + dig_hotplug_reg,
> > > > > > hpd_icp,
> > > > > > + icp_tc_port_hotplug_lon
> > > > > > g_detect
> > > > > > );
> > > > > > + }
> > > > > > +
> > > > > > + if (pin_mask)
> > > > > > + intel_hpd_irq_handler(dev_priv, pin_mask,
> > > > > > long_mask);
> > > > > > +
> > > > > > + if (pch_iir & ICP_GMBUS)
> > > > > > + gmbus_irq_handler(dev_priv);
> > > > > > +}
> > > > > > +
> > > > > > static void spt_irq_handler(struct drm_i915_private
> > > > > > *dev_priv, u32
> > > > > > pch_iir)
> > > > > > {
> > > > > > u32 hotplug_trigger = pch_iir &
> > > > > > SDE_HOTPLUG_MASK_SPT &
> > > > > > @@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct
> > > > > > drm_i915_private
> > > > > > *dev_priv, u32 master_ctl)
> > > > > > I915_WRITE(SDEIIR, iir);
> > > > > > ret = IRQ_HANDLED;
> > > > > >
> > > > > > - if (HAS_PCH_SPT(dev_priv) ||
> > > > > > HAS_PCH_KBP(dev_priv) ||
> > > > > > - HAS_PCH_CNP(dev_priv))
> > > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > > + icp_irq_handler(dev_priv,
> > > > > > iir);
> >
> > to be clear on what I was saying... See the context just above: we
> > read
> > and write SDEIIR to get/clear the interrupt bits. Yet you are
> > defining a
> > ICP_SDE_IIR that has to be the same value. To avoid any confusion,
> > I
> > think it's better to stay with SDEIIR and just change the bit
> > definition.
>
> Dk, any news on this?
>
> Lucas De Marchi
>
> >
> >
> > > > > > + else if (HAS_PCH_SPT(dev_priv) ||
> > > > > > + HAS_PCH_KBP(dev_priv) ||
> > > > > > + HAS_PCH_CNP(dev_priv))
> > > > > > spt_irq_handler(dev_priv,
> > > > > > iir);
> > > > > > else
> > > > > > cpt_irq_handler(dev_priv,
> > > > > > iir);
> > > > > > @@ -3548,6 +3625,9 @@ static void gen11_irq_reset(struct
> > > > > > drm_device
> > > > > > *dev)
> > > > > > GEN3_IRQ_RESET(GEN11_DE_HPD_);
> > > > > > GEN3_IRQ_RESET(GEN11_GU_MISC_);
> > > > > > GEN3_IRQ_RESET(GEN8_PCU_);
> > > > > > +
> > > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > > + GEN3_IRQ_RESET(ICP_SDE_);
> > > > > > }
> > > > > >
> > > > > > void gen8_irq_power_well_post_enable(struct
> > > > > > drm_i915_private
> > > > > > *dev_priv,
> > > > > > @@ -3664,6 +3744,35 @@ static void ibx_hpd_irq_setup(struct
> > > > > > drm_i915_private *dev_priv)
> > > > > > ibx_hpd_detection_setup(dev_priv);
> > > > > > }
> > > > > >
> > > > > > +static void icp_hpd_detection_setup(struct
> > > > > > drm_i915_private
> > > > > > *dev_priv)
> > > > > > +{
> > > > > > + u32 hotplug;
> > > > > > +
> > > > > > + hotplug = I915_READ(SHOTPLUG_CTL_DDI);
> > > > > > + hotplug |= ICP_DDIA_HPD_ENABLE |
> > > > > > + ICP_DDIB_HPD_ENABLE;
> > > > > > + I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
> > > > > > +
> > > > > > + hotplug = I915_READ(SHOTPLUG_CTL_TC);
> > > > > > + hotplug |= ICP_TC_HPD_ENABLE(PORT_TC1) |
> > > > > > + ICP_TC_HPD_ENABLE(PORT_TC2) |
> > > > > > + ICP_TC_HPD_ENABLE(PORT_TC3) |
> > > > > > + ICP_TC_HPD_ENABLE(PORT_TC4);
> > > > > > + I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
> > > > > > +}
> > > > > > +
> > > > > > +static void icp_hpd_irq_setup(struct drm_i915_private
> > > > > > *dev_priv)
> > > > > > +{
> > > > > > + u32 hotplug_irqs, enabled_irqs;
> > > > > > +
> > > > > > + hotplug_irqs = ICP_SDE_DDI_MASK | ICP_SDE_TC_MASK;
> > > > > > + enabled_irqs = intel_hpd_enabled_irqs(dev_priv,
> > > > > > hpd_icp);
> > > > > > +
> > > > > > + ibx_display_interrupt_update(dev_priv,
> > > > > > hotplug_irqs,
> > > > > > enabled_irqs);
> > > > > > +
> > > > > > + icp_hpd_detection_setup(dev_priv);
> > > > > > +}
> > > > > > +
> > > > > > static void gen11_hpd_detection_setup(struct
> > > > > > drm_i915_private
> > > > > > *dev_priv)
> > > > > > {
> > > > > > u32 hotplug;
> > > > > > @@ -3690,6 +3799,9 @@ static void
> > > > > > gen11_hpd_irq_setup(struct
> > > > > > drm_i915_private *dev_priv)
> > > > > > POSTING_READ(GEN11_DE_HPD_IMR);
> > > > > >
> > > > > > gen11_hpd_detection_setup(dev_priv);
> > > > > > +
> > > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > > + icp_hpd_irq_setup(dev_priv);
> > > > > > }
> > > > > >
> > > > > > static void spt_hpd_detection_setup(struct
> > > > > > drm_i915_private
> > > > > > *dev_priv)
> > > > > > @@ -4121,11 +4233,29 @@ static void
> > > > > > gen11_gt_irq_postinstall(struct
> > > > > > drm_i915_private *dev_priv)
> > > > > > I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> > > > > > }
> > > > > >
> > > > > > +static void icp_irq_postinstall(struct drm_device *dev)
> > > > > > +{
> > > > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > > + u32 mask = ICP_GMBUS;
> > > > > > +
> > > > > > + WARN_ON(I915_READ(ICP_SDE_IER) != 0);
> > > > > > + I915_WRITE(ICP_SDE_IER, 0xffffffff);
> > > > > > + POSTING_READ(ICP_SDE_IER);
> > > > > > +
> > > > > > + gen3_assert_iir_is_zero(dev_priv, ICP_SDE_IIR);
> > > > > > + I915_WRITE(ICP_SDE_IMR, ~mask);
> > > > > > +
> > > > > > + icp_hpd_detection_setup(dev_priv);
> > > > > > +}
> > > > > > +
> > > > > > static int gen11_irq_postinstall(struct drm_device *dev)
> > > > > > {
> > > > > > struct drm_i915_private *dev_priv = dev-
> > > > > > >dev_private;
> > > > > > u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> > > > > >
> > > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > > + icp_irq_postinstall(dev);
> > > > > > +
> > > > > > gen11_gt_irq_postinstall(dev_priv);
> > > > > > gen8_de_irq_postinstall(dev_priv);
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > index 19600097581f..28ce96ce0484 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > @@ -7460,6 +7460,46 @@ enum {
> > > > > > #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
> > > > > > #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
> > > > > >
> > > > > > +/* ICP */
> > > > > > +#define ICP_SDE_ISR _MMIO(0xc4000)
> > > > > > +#define ICP_SDE_IMR _MMIO(0xc4004)
> > > > > > +#define ICP_SDE_IIR _MMIO(0xc4008)
> > > > > > +#define ICP_SDE_IER _MMIO(0xc400c)
> > > > >
> > > > > These are exactly the same registers as SDE{ISR,IMR,IIR,IER}.
> > > > > For all
> > > > > the other platforms what we do is rather postfix the platform
> > > > > name.
> > > > >
> > > > > I think we should follow what they do here.
I agree, there's no need to have an alias and this can indeed make the
code harder to read. I'd vote to just remove it, but if we indeed to
chose to do it, we can do something like:
#define ICP_SDE_ISR SDE_ISR
But I think it's worth keeping the bit definitions separate since
they're very different. Perhaps we should keep the comment to explain
that the ICP registers are below:
#define registers_from_before (x < y)
/* ICP: */
#define registers_from_icp (x < y)
> > > > >
> > > > >
> > > > > >
> > > > > > +#define ICP_TC4_HOTPLUG (1 << 27)
> > > > > > +#define ICP_TC3_HOTPLUG (1 << 26)
> > > > > > +#define ICP_TC2_HOTPLUG (1 << 25)
> > > > > > +#define ICP_TC1_HOTPLUG (1 << 24)
> > > > > > +#define ICP_GMBUS (1 << 23)
> > > > > > +#define ICP_DDIB_HOTPLUG (1 << 17)
> > > > > > +#define ICP_DDIA_HOTPLUG (1 << 16)
> > > > >
> > > > > so these would become SDE_TC4_HOTPLUG_ICP and so on.
> > > > >
I don't have strong opinions here, I'd go with whatever. Just a notice
that ICP is an SDE, so we have some ugly redundancy here. But yeah, our
standard is weird: registers new to a platform have the platform name
as a prefix, bits new to a platform have the platform name as a
suffix...
> > > >
> > > > The reason I preferred this naming for gen-11 is it is
> > > > symmetric to the
> > > > corresponding definitions in the north engine.
> > > >
> > > > For example,
> > > > +#define GEN11_DE_HPD_ISR _MMIO(0x44470)
> > > > +#define GEN11_DE_HPD_IMR _MMIO(0x44474)
> > > > +#define GEN11_DE_HPD_IIR _MMIO(0x44478)
> > > > +#define GEN11_DE_HPD_IER _MMIO(0x4447c)
> > > > +#define GEN11_TC4_HOTPLUG (1 << 19)
> > > > +#define GEN11_TC3_HOTPLUG (1 << 18)
> > > > +#define GEN11_TC2_HOTPLUG (1 << 17)
> > > > +#define GEN11_TC1_HOTPLUG (1 << 16)
> > > >
> > > > With interrupts getting routed to north or south engines for
> > > > the same
> > > > port, this naming scheme makes the duality clearer IMO.
> > >
> > > Still the register is the same as SDEISR and there are places in
> > > which we
> > > read it expecting to be the same number.
> > >
> > > Only the bits are different, so name the bits differently as it
> > > is for
> > > other platforms. I think of the symmetry here just and accident
> > > of
> > > life expecting to be different if north and south engines don't
> > > have the
> > > same ports.
> >
> > This is on gen8_de_irq_handler() which is still used for gen11.
> >
> > Lucas De Marchi
> >
> > >
> > > Lucas De Marchi
> > >
> > > >
> > > >
> > > > > >
> > > > > > +
> > > > > > +#define ICP_SDE_DDI_MASK (ICP_DDIB_HOTPLUG
> > > > > > |
> > > > > > \
> > > > > > + ICP_DDIA_HOTPLUG)
> > > > > > +
> > > > > > +#define ICP_SDE_TC_MASK (ICP_TC4_HO
> > > > > > TPLUG |
> > > > > > \
> > > > > > + ICP_TC3_HOTPLUG |
> > > > > >
> > > > > > \
> > > > > > + ICP_TC2_HOTPLUG |
> > > > > >
> > > > > > \
> > > > > > + ICP_TC1_HOTPLUG)
> > > > > > +
> > > > > > +#define SHOTPLUG_CTL_DDI _MMIO(0xc4
> > > > > > 030)
> > > > > > /* SHOTPLUG_CTL */
> > > > >
> > > > > This also seems to reuse what we have defined as
> > > > > PCH_PORT_HOTPLUG
> > > > > with a
> > > > > comment to SHOTPLUG_CTL there, although here I tend to be in
> > > > > favor of
> > > > > using the current real name of the register (SHOTPLUG_CTL).
> > > >
> > > > The real name I see is SHOTPLUG_CTL_DDI for ICP.
> > > >
> > > > I don't believe we should attempt to make these definitions
> > > > consistent
> > > > with previous platforms over making them consistent with each
> > > > other.
The thing to keep in mind here is that ICP split this register in two:
SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC, so I'd be in favor of never using
just SHOTPLUG_CTL.
> > > >
> > > >
> > > > >
> > > > > The rest looks good to me.
> > > > >
> > > > > Lucas De Marchi
> > > > >
> > > > > >
> > > > > > +#define ICP_DDIB_HPD_ENABLE (1 <<
> > > > > > 7)
> > > > > > +#define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
> > > > > > +#define ICP_DDIB_HPD_NO_DETECT (0 << 4)
> > > > > > +#define ICP_DDIB_HPD_SHORT_DETECT (1 <<
> > > > > > 4)
> > > > > > +#define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
> > > > > > +#define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
> > > > > > +#define ICP_DDIA_HPD_ENABLE (1 <<
> > > > > > 3)
> > > > > > +#define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
> > > > > > +#define ICP_DDIA_HPD_NO_DETECT (0 << 0)
> > > > > > +#define ICP_DDIA_HPD_SHORT_DETECT (1 <<
> > > > > > 0)
> > > > > > +#define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
> > > > > > +#define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
> > > > > > +
> > > > > > +#define SHOTPLUG_CTL_TC _MM
> > > > > > IO(0xc40
> > > > > > 34)
> > > > > > +#define ICP_TC_HPD_ENABLE(tc_port) (8 <<
> > > > > > (tc_port) * 4)
> > > > > > +#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 <<
> > > > > > (tc_port) *
> > > > > > 4)
> > > > > > +#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 <<
> > > > > > (tc_port)
> > > > > > * 4)
> > > > > > +
> > > > > > #define PCH_GPIOA _MMIO(0xc5010)
> > > > > > #define PCH_GPIOB _MMIO(0xc5014)
> > > > > > #define PCH_GPIOC _MMIO(0xc5018)
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^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 05/24] drm/i915/icp: Add Interrupt Support
2018-06-13 22:23 ` Lucas De Marchi
2018-06-14 0:04 ` Paulo Zanoni
@ 2018-06-14 2:21 ` Dhinakaran Pandiyan
2018-06-18 19:10 ` Anusha Srivatsa
1 sibling, 1 reply; 127+ messages in thread
From: Dhinakaran Pandiyan @ 2018-06-14 2:21 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Paulo Zanoni
On Wed, 2018-06-13 at 15:23 -0700, Lucas De Marchi wrote:
> On Tue, May 29, 2018 at 05:04:58PM -0700, Lucas De Marchi wrote:
> >
> > On Thu, May 24, 2018 at 05:43:24PM -0700, Lucas De Marchi wrote:
> > >
> > > On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan
> > > wrote:
> > > >
> > > > On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > > > >
> > > > > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > > > > >
> > > > > >
> > > > > > From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > > > >
> > > > > > This patch addresses Interrupts from south display engine
> > > > > > (SDE).
> > > > > >
> > > > > > ICP has two registers - SHOTPLUG_CTL_DDI and
> > > > > > SHOTPLUG_CTL_TC.
> > > > > > Introduce these registers and their intended values.
> > > > > >
> > > > > > Introduce icp_irq_handler().
> > > > > >
> > > > > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > > > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > > > > [Paulo: coding style bikesheds and rebases].
> > > > > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/i915_irq.c | 134
> > > > > > +++++++++++++++++++++++++++++++++++++++-
> > > > > > drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++
> > > > > > 2 files changed, 172 insertions(+), 2 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > index 9bcec5fdb9d0..6b109991786f 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > @@ -122,6 +122,15 @@ static const u32
> > > > > > hpd_tc_gen11[HPD_NUM_PINS] =
> > > > > > {
> > > > > > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > > > > > };
> > > > > >
> > > > > > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > > > > > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > > > > > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > > > > > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > > > > > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > > > > > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > > > > > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > > > > > +};
> > > > > > +
> > > > > > /* IIR can theoretically queue up two events. Be paranoid.
> > > > > > */
> > > > > > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > > > > > I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff);
> > > > > > \
> > > > > > @@ -1586,6 +1595,34 @@ static bool
> > > > > > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > > > > > }
> > > > > > }
> > > > > >
> > > > > > +static bool icp_ddi_port_hotplug_long_detect(enum port
> > > > > > port, u32
> > > > > > val)
> > > > > > +{
> > > > > > + switch (port) {
> > > > > > + case PORT_A:
> > > > > > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > > > > > + case PORT_B:
> > > > > > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > > > > > + default:
> > > > > > + return false;
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > > > +static bool icp_tc_port_hotplug_long_detect(enum port
> > > > > > port, u32
> > > > > > val)
> > > > > > +{
> > > > > > + switch (port) {
> > > > > > + case PORT_C:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > > > > > + case PORT_D:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > > > > > + case PORT_E:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > > > > > + case PORT_F:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > > > > > + default:
> > > > > > + return false;
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > > > static bool spt_port_hotplug2_long_detect(enum port port,
> > > > > > u32 val)
> > > > > > {
> > > > > > switch (port) {
> > > > > > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > > > > > drm_i915_private *dev_priv, u32 pch_iir)
> > > > > > cpt_serr_int_handler(dev_priv);
> > > > > > }
> > > > > >
> > > > > > +static void icp_irq_handler(struct drm_i915_private
> > > > > > *dev_priv, u32
> > > > > > pch_iir)
> > > > > > +{
> > > > > > + u32 ddi_hotplug_trigger = pch_iir &
> > > > > > ICP_SDE_DDI_MASK;
> > > > > > + u32 tc_hotplug_trigger = pch_iir &
> > > > > > ICP_SDE_TC_MASK;
> > > > > > + u32 pin_mask = 0, long_mask = 0;
> > > > > > +
> > > > > > + if (ddi_hotplug_trigger) {
> > > > > > + u32 dig_hotplug_reg;
> > > > > > +
> > > > > > + dig_hotplug_reg =
> > > > > > I915_READ(SHOTPLUG_CTL_DDI);
> > > > > > + I915_WRITE(SHOTPLUG_CTL_DDI,
> > > > > > dig_hotplug_reg);
> > > > > > +
> > > > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > > > &long_mask,
> > > > > > + ddi_hotplug_trigger,
> > > > > > + dig_hotplug_reg,
> > > > > > hpd_icp,
> > > > > > + icp_ddi_port_hotplug_lo
> > > > > > ng_detec
> > > > > > t);
> > > > > > + }
> > > > > > +
> > > > > > + if (tc_hotplug_trigger) {
> > > > > > + u32 dig_hotplug_reg;
> > > > > > +
> > > > > > + dig_hotplug_reg =
> > > > > > I915_READ(SHOTPLUG_CTL_TC);
> > > > > > + I915_WRITE(SHOTPLUG_CTL_TC,
> > > > > > dig_hotplug_reg);
> > > > > > +
> > > > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > > > &long_mask,
> > > > > > + tc_hotplug_trigger,
> > > > > > + dig_hotplug_reg,
> > > > > > hpd_icp,
> > > > > > + icp_tc_port_hotplug_lon
> > > > > > g_detect
> > > > > > );
> > > > > > + }
> > > > > > +
> > > > > > + if (pin_mask)
> > > > > > + intel_hpd_irq_handler(dev_priv, pin_mask,
> > > > > > long_mask);
> > > > > > +
> > > > > > + if (pch_iir & ICP_GMBUS)
> > > > > > + gmbus_irq_handler(dev_priv);
> > > > > > +}
> > > > > > +
> > > > > > static void spt_irq_handler(struct drm_i915_private
> > > > > > *dev_priv, u32
> > > > > > pch_iir)
> > > > > > {
> > > > > > u32 hotplug_trigger = pch_iir &
> > > > > > SDE_HOTPLUG_MASK_SPT &
> > > > > > @@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct
> > > > > > drm_i915_private
> > > > > > *dev_priv, u32 master_ctl)
> > > > > > I915_WRITE(SDEIIR, iir);
> > > > > > ret = IRQ_HANDLED;
> > > > > >
> > > > > > - if (HAS_PCH_SPT(dev_priv) ||
> > > > > > HAS_PCH_KBP(dev_priv) ||
> > > > > > - HAS_PCH_CNP(dev_priv))
> > > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > > + icp_irq_handler(dev_priv,
> > > > > > iir);
> > to be clear on what I was saying... See the context just above: we
> > read
> > and write SDEIIR to get/clear the interrupt bits. Yet you are
> > defining a
> > ICP_SDE_IIR that has to be the same value. To avoid any confusion,
> > I
> > think it's better to stay with SDEIIR and just change the bit
> > definition.
> Dk, any news on this?
SDEIIR is fine by me. The patch author has to make the required
changes, I just reviewed the patch :)
>
> Lucas De Marchi
>
> >
> >
> >
> > >
> > > >
> > > > >
> > > > > >
> > > > > > + else if (HAS_PCH_SPT(dev_priv) ||
> > > > > > + HAS_PCH_KBP(dev_priv) ||
> > > > > > + HAS_PCH_CNP(dev_priv))
> > > > > > spt_irq_handler(dev_priv,
> > > > > > iir);
> > > > > > else
> > > > > > cpt_irq_handler(dev_priv,
> > > > > > iir);
> > > > > > @@ -3548,6 +3625,9 @@ static void gen11_irq_reset(struct
> > > > > > drm_device
> > > > > > *dev)
> > > > > > GEN3_IRQ_RESET(GEN11_DE_HPD_);
> > > > > > GEN3_IRQ_RESET(GEN11_GU_MISC_);
> > > > > > GEN3_IRQ_RESET(GEN8_PCU_);
> > > > > > +
> > > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > > + GEN3_IRQ_RESET(ICP_SDE_);
> > > > > > }
> > > > > >
> > > > > > void gen8_irq_power_well_post_enable(struct
> > > > > > drm_i915_private
> > > > > > *dev_priv,
> > > > > > @@ -3664,6 +3744,35 @@ static void ibx_hpd_irq_setup(struct
> > > > > > drm_i915_private *dev_priv)
> > > > > > ibx_hpd_detection_setup(dev_priv);
> > > > > > }
> > > > > >
> > > > > > +static void icp_hpd_detection_setup(struct
> > > > > > drm_i915_private
> > > > > > *dev_priv)
> > > > > > +{
> > > > > > + u32 hotplug;
> > > > > > +
> > > > > > + hotplug = I915_READ(SHOTPLUG_CTL_DDI);
> > > > > > + hotplug |= ICP_DDIA_HPD_ENABLE |
> > > > > > + ICP_DDIB_HPD_ENABLE;
> > > > > > + I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
> > > > > > +
> > > > > > + hotplug = I915_READ(SHOTPLUG_CTL_TC);
> > > > > > + hotplug |= ICP_TC_HPD_ENABLE(PORT_TC1) |
> > > > > > + ICP_TC_HPD_ENABLE(PORT_TC2) |
> > > > > > + ICP_TC_HPD_ENABLE(PORT_TC3) |
> > > > > > + ICP_TC_HPD_ENABLE(PORT_TC4);
> > > > > > + I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
> > > > > > +}
> > > > > > +
> > > > > > +static void icp_hpd_irq_setup(struct drm_i915_private
> > > > > > *dev_priv)
> > > > > > +{
> > > > > > + u32 hotplug_irqs, enabled_irqs;
> > > > > > +
> > > > > > + hotplug_irqs = ICP_SDE_DDI_MASK | ICP_SDE_TC_MASK;
> > > > > > + enabled_irqs = intel_hpd_enabled_irqs(dev_priv,
> > > > > > hpd_icp);
> > > > > > +
> > > > > > + ibx_display_interrupt_update(dev_priv,
> > > > > > hotplug_irqs,
> > > > > > enabled_irqs);
> > > > > > +
> > > > > > + icp_hpd_detection_setup(dev_priv);
> > > > > > +}
> > > > > > +
> > > > > > static void gen11_hpd_detection_setup(struct
> > > > > > drm_i915_private
> > > > > > *dev_priv)
> > > > > > {
> > > > > > u32 hotplug;
> > > > > > @@ -3690,6 +3799,9 @@ static void
> > > > > > gen11_hpd_irq_setup(struct
> > > > > > drm_i915_private *dev_priv)
> > > > > > POSTING_READ(GEN11_DE_HPD_IMR);
> > > > > >
> > > > > > gen11_hpd_detection_setup(dev_priv);
> > > > > > +
> > > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > > + icp_hpd_irq_setup(dev_priv);
> > > > > > }
> > > > > >
> > > > > > static void spt_hpd_detection_setup(struct
> > > > > > drm_i915_private
> > > > > > *dev_priv)
> > > > > > @@ -4121,11 +4233,29 @@ static void
> > > > > > gen11_gt_irq_postinstall(struct
> > > > > > drm_i915_private *dev_priv)
> > > > > > I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> > > > > > }
> > > > > >
> > > > > > +static void icp_irq_postinstall(struct drm_device *dev)
> > > > > > +{
> > > > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > > + u32 mask = ICP_GMBUS;
> > > > > > +
> > > > > > + WARN_ON(I915_READ(ICP_SDE_IER) != 0);
> > > > > > + I915_WRITE(ICP_SDE_IER, 0xffffffff);
> > > > > > + POSTING_READ(ICP_SDE_IER);
> > > > > > +
> > > > > > + gen3_assert_iir_is_zero(dev_priv, ICP_SDE_IIR);
> > > > > > + I915_WRITE(ICP_SDE_IMR, ~mask);
> > > > > > +
> > > > > > + icp_hpd_detection_setup(dev_priv);
> > > > > > +}
> > > > > > +
> > > > > > static int gen11_irq_postinstall(struct drm_device *dev)
> > > > > > {
> > > > > > struct drm_i915_private *dev_priv = dev-
> > > > > > >dev_private;
> > > > > > u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> > > > > >
> > > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > > + icp_irq_postinstall(dev);
> > > > > > +
> > > > > > gen11_gt_irq_postinstall(dev_priv);
> > > > > > gen8_de_irq_postinstall(dev_priv);
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > index 19600097581f..28ce96ce0484 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > @@ -7460,6 +7460,46 @@ enum {
> > > > > > #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
> > > > > > #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
> > > > > >
> > > > > > +/* ICP */
> > > > > > +#define ICP_SDE_ISR _MMIO(0xc4000)
> > > > > > +#define ICP_SDE_IMR _MMIO(0xc4004)
> > > > > > +#define ICP_SDE_IIR _MMIO(0xc4008)
> > > > > > +#define ICP_SDE_IER _MMIO(0xc400c)
> > > > > These are exactly the same registers as SDE{ISR,IMR,IIR,IER}.
> > > > > For all
> > > > > the other platforms what we do is rather postfix the platform
> > > > > name.
> > > > >
> > > > > I think we should follow what they do here.
> > > > >
> > > > >
> > > > > >
> > > > > >
> > > > > > +#define ICP_TC4_HOTPLUG (1 << 27)
> > > > > > +#define ICP_TC3_HOTPLUG (1 << 26)
> > > > > > +#define ICP_TC2_HOTPLUG (1 << 25)
> > > > > > +#define ICP_TC1_HOTPLUG (1 << 24)
> > > > > > +#define ICP_GMBUS (1 << 23)
> > > > > > +#define ICP_DDIB_HOTPLUG (1 << 17)
> > > > > > +#define ICP_DDIA_HOTPLUG (1 << 16)
> > > > > so these would become SDE_TC4_HOTPLUG_ICP and so on.
> > > > >
> > > > The reason I preferred this naming for gen-11 is it is
> > > > symmetric to the
> > > > corresponding definitions in the north engine.
> > > >
> > > > For example,
> > > > +#define GEN11_DE_HPD_ISR _MMIO(0x44470)
> > > > +#define GEN11_DE_HPD_IMR _MMIO(0x44474)
> > > > +#define GEN11_DE_HPD_IIR _MMIO(0x44478)
> > > > +#define GEN11_DE_HPD_IER _MMIO(0x4447c)
> > > > +#define GEN11_TC4_HOTPLUG (1 << 19)
> > > > +#define GEN11_TC3_HOTPLUG (1 << 18)
> > > > +#define GEN11_TC2_HOTPLUG (1 << 17)
> > > > +#define GEN11_TC1_HOTPLUG (1 << 16)
> > > >
> > > > With interrupts getting routed to north or south engines for
> > > > the same
> > > > port, this naming scheme makes the duality clearer IMO.
> > > Still the register is the same as SDEISR and there are places in
> > > which we
> > > read it expecting to be the same number.
> > >
> > > Only the bits are different, so name the bits differently as it
> > > is for
> > > other platforms. I think of the symmetry here just and accident
> > > of
> > > life expecting to be different if north and south engines don't
> > > have the
> > > same ports.
> > This is on gen8_de_irq_handler() which is still used for gen11.
> >
> > Lucas De Marchi
> >
> > >
> > >
> > > Lucas De Marchi
> > >
> > > >
> > > >
> > > >
> > > > >
> > > > > >
> > > > > >
> > > > > > +
> > > > > > +#define ICP_SDE_DDI_MASK (ICP_DDIB_HOTPLUG
> > > > > > |
> > > > > > \
> > > > > > + ICP_DDIA_HOTPLUG)
> > > > > > +
> > > > > > +#define ICP_SDE_TC_MASK (ICP_TC4_HO
> > > > > > TPLUG |
> > > > > > \
> > > > > > + ICP_TC3_HOTPLUG |
> > > > > >
> > > > > > \
> > > > > > + ICP_TC2_HOTPLUG |
> > > > > >
> > > > > > \
> > > > > > + ICP_TC1_HOTPLUG)
> > > > > > +
> > > > > > +#define SHOTPLUG_CTL_DDI _MMIO(0xc4
> > > > > > 030)
> > > > > > /* SHOTPLUG_CTL */
> > > > > This also seems to reuse what we have defined as
> > > > > PCH_PORT_HOTPLUG
> > > > > with a
> > > > > comment to SHOTPLUG_CTL there, although here I tend to be in
> > > > > favor of
> > > > > using the current real name of the register (SHOTPLUG_CTL).
> > > > The real name I see is SHOTPLUG_CTL_DDI for ICP.
> > > >
> > > > I don't believe we should attempt to make these definitions
> > > > consistent
> > > > with previous platforms over making them consistent with each
> > > > other.
> > > >
If you want to retain the original definition PCH_HOTPLUG, appending to
the existing comment that the register is called SHOTPLUG_CTL_DDI on
ICP would be nice.
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^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 05/24] drm/i915/icp: Add Interrupt Support
2018-06-14 2:21 ` Dhinakaran Pandiyan
@ 2018-06-18 19:10 ` Anusha Srivatsa
0 siblings, 0 replies; 127+ messages in thread
From: Anusha Srivatsa @ 2018-06-18 19:10 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx, Paulo Zanoni
On Wed, Jun 13, 2018 at 07:21:54PM -0700, Dhinakaran Pandiyan wrote:
> On Wed, 2018-06-13 at 15:23 -0700, Lucas De Marchi wrote:
> > On Tue, May 29, 2018 at 05:04:58PM -0700, Lucas De Marchi wrote:
> > >
> > > On Thu, May 24, 2018 at 05:43:24PM -0700, Lucas De Marchi wrote:
> > > >
> > > > On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan
> > > > wrote:
> > > > >
> > > > > On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > > > > >
> > > > > > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > > > > > >
> > > > > > >
> > > > > > > From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > > > > >
> > > > > > > This patch addresses Interrupts from south display engine
> > > > > > > (SDE).
> > > > > > >
> > > > > > > ICP has two registers - SHOTPLUG_CTL_DDI and
> > > > > > > SHOTPLUG_CTL_TC.
> > > > > > > Introduce these registers and their intended values.
> > > > > > >
> > > > > > > Introduce icp_irq_handler().
> > > > > > >
> > > > > > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > > > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > > > > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > > > > > [Paulo: coding style bikesheds and rebases].
> > > > > > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > > > > ---
> > > > > > > drivers/gpu/drm/i915/i915_irq.c | 134
> > > > > > > +++++++++++++++++++++++++++++++++++++++-
> > > > > > > drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++
> > > > > > > 2 files changed, 172 insertions(+), 2 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > > index 9bcec5fdb9d0..6b109991786f 100644
> > > > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > > @@ -122,6 +122,15 @@ static const u32
> > > > > > > hpd_tc_gen11[HPD_NUM_PINS] =
> > > > > > > {
> > > > > > > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > > > > > > };
> > > > > > >
> > > > > > > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > > > > > > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > > > > > > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > > > > > > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > > > > > > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > > > > > > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > > > > > > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > > > > > > +};
> > > > > > > +
> > > > > > > /* IIR can theoretically queue up two events. Be paranoid.
> > > > > > > */
> > > > > > > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > > > > > > I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff);
> > > > > > > \
> > > > > > > @@ -1586,6 +1595,34 @@ static bool
> > > > > > > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > > > > > > }
> > > > > > > }
> > > > > > >
> > > > > > > +static bool icp_ddi_port_hotplug_long_detect(enum port
> > > > > > > port, u32
> > > > > > > val)
> > > > > > > +{
> > > > > > > + switch (port) {
> > > > > > > + case PORT_A:
> > > > > > > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > > > > > > + case PORT_B:
> > > > > > > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > > > > > > + default:
> > > > > > > + return false;
> > > > > > > + }
> > > > > > > +}
> > > > > > > +
> > > > > > > +static bool icp_tc_port_hotplug_long_detect(enum port
> > > > > > > port, u32
> > > > > > > val)
> > > > > > > +{
> > > > > > > + switch (port) {
> > > > > > > + case PORT_C:
> > > > > > > + return val &
> > > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > > > > > > + case PORT_D:
> > > > > > > + return val &
> > > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > > > > > > + case PORT_E:
> > > > > > > + return val &
> > > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > > > > > > + case PORT_F:
> > > > > > > + return val &
> > > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > > > > > > + default:
> > > > > > > + return false;
> > > > > > > + }
> > > > > > > +}
> > > > > > > +
> > > > > > > static bool spt_port_hotplug2_long_detect(enum port port,
> > > > > > > u32 val)
> > > > > > > {
> > > > > > > switch (port) {
> > > > > > > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > > > > > > drm_i915_private *dev_priv, u32 pch_iir)
> > > > > > > cpt_serr_int_handler(dev_priv);
> > > > > > > }
> > > > > > >
> > > > > > > +static void icp_irq_handler(struct drm_i915_private
> > > > > > > *dev_priv, u32
> > > > > > > pch_iir)
> > > > > > > +{
> > > > > > > + u32 ddi_hotplug_trigger = pch_iir &
> > > > > > > ICP_SDE_DDI_MASK;
> > > > > > > + u32 tc_hotplug_trigger = pch_iir &
> > > > > > > ICP_SDE_TC_MASK;
> > > > > > > + u32 pin_mask = 0, long_mask = 0;
> > > > > > > +
> > > > > > > + if (ddi_hotplug_trigger) {
> > > > > > > + u32 dig_hotplug_reg;
> > > > > > > +
> > > > > > > + dig_hotplug_reg =
> > > > > > > I915_READ(SHOTPLUG_CTL_DDI);
> > > > > > > + I915_WRITE(SHOTPLUG_CTL_DDI,
> > > > > > > dig_hotplug_reg);
> > > > > > > +
> > > > > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > > > > &long_mask,
> > > > > > > + ddi_hotplug_trigger,
> > > > > > > + dig_hotplug_reg,
> > > > > > > hpd_icp,
> > > > > > > + icp_ddi_port_hotplug_lo
> > > > > > > ng_detec
> > > > > > > t);
> > > > > > > + }
> > > > > > > +
> > > > > > > + if (tc_hotplug_trigger) {
> > > > > > > + u32 dig_hotplug_reg;
> > > > > > > +
> > > > > > > + dig_hotplug_reg =
> > > > > > > I915_READ(SHOTPLUG_CTL_TC);
> > > > > > > + I915_WRITE(SHOTPLUG_CTL_TC,
> > > > > > > dig_hotplug_reg);
> > > > > > > +
> > > > > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > > > > &long_mask,
> > > > > > > + tc_hotplug_trigger,
> > > > > > > + dig_hotplug_reg,
> > > > > > > hpd_icp,
> > > > > > > + icp_tc_port_hotplug_lon
> > > > > > > g_detect
> > > > > > > );
> > > > > > > + }
> > > > > > > +
> > > > > > > + if (pin_mask)
> > > > > > > + intel_hpd_irq_handler(dev_priv, pin_mask,
> > > > > > > long_mask);
> > > > > > > +
> > > > > > > + if (pch_iir & ICP_GMBUS)
> > > > > > > + gmbus_irq_handler(dev_priv);
> > > > > > > +}
> > > > > > > +
> > > > > > > static void spt_irq_handler(struct drm_i915_private
> > > > > > > *dev_priv, u32
> > > > > > > pch_iir)
> > > > > > > {
> > > > > > > u32 hotplug_trigger = pch_iir &
> > > > > > > SDE_HOTPLUG_MASK_SPT &
> > > > > > > @@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct
> > > > > > > drm_i915_private
> > > > > > > *dev_priv, u32 master_ctl)
> > > > > > > I915_WRITE(SDEIIR, iir);
> > > > > > > ret = IRQ_HANDLED;
> > > > > > >
> > > > > > > - if (HAS_PCH_SPT(dev_priv) ||
> > > > > > > HAS_PCH_KBP(dev_priv) ||
> > > > > > > - HAS_PCH_CNP(dev_priv))
> > > > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > > > + icp_irq_handler(dev_priv,
> > > > > > > iir);
> > > to be clear on what I was saying... See the context just above: we
> > > read
> > > and write SDEIIR to get/clear the interrupt bits. Yet you are
> > > defining a
> > > ICP_SDE_IIR that has to be the same value. To avoid any confusion,
> > > I
> > > think it's better to stay with SDEIIR and just change the bit
> > > definition.
> > Dk, any news on this?
Lucas, Dk, thanks for the review.
Sorry for the late response.
Yes, i see that the registers are exactly the same. better to reuse the
original SDE{} and have only new bit definitions in place.
I shall remove the ICP_SDE{} register defines.
> SDEIIR is fine by me. The patch author has to make the required
> changes, I just reviewed the patch :)
>
> >
> > Lucas De Marchi
> >
> > >
> > >
> > >
> > > >
> > > > >
> > > > > >
> > > > > > >
> > > > > > > + else if (HAS_PCH_SPT(dev_priv) ||
> > > > > > > + HAS_PCH_KBP(dev_priv) ||
> > > > > > > + HAS_PCH_CNP(dev_priv))
> > > > > > > spt_irq_handler(dev_priv,
> > > > > > > iir);
> > > > > > > else
> > > > > > > cpt_irq_handler(dev_priv,
> > > > > > > iir);
> > > > > > > @@ -3548,6 +3625,9 @@ static void gen11_irq_reset(struct
> > > > > > > drm_device
> > > > > > > *dev)
> > > > > > > GEN3_IRQ_RESET(GEN11_DE_HPD_);
> > > > > > > GEN3_IRQ_RESET(GEN11_GU_MISC_);
> > > > > > > GEN3_IRQ_RESET(GEN8_PCU_);
> > > > > > > +
> > > > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > > > + GEN3_IRQ_RESET(ICP_SDE_);
> > > > > > > }
> > > > > > >
> > > > > > > void gen8_irq_power_well_post_enable(struct
> > > > > > > drm_i915_private
> > > > > > > *dev_priv,
> > > > > > > @@ -3664,6 +3744,35 @@ static void ibx_hpd_irq_setup(struct
> > > > > > > drm_i915_private *dev_priv)
> > > > > > > ibx_hpd_detection_setup(dev_priv);
> > > > > > > }
> > > > > > >
> > > > > > > +static void icp_hpd_detection_setup(struct
> > > > > > > drm_i915_private
> > > > > > > *dev_priv)
> > > > > > > +{
> > > > > > > + u32 hotplug;
> > > > > > > +
> > > > > > > + hotplug = I915_READ(SHOTPLUG_CTL_DDI);
> > > > > > > + hotplug |= ICP_DDIA_HPD_ENABLE |
> > > > > > > + ICP_DDIB_HPD_ENABLE;
> > > > > > > + I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
> > > > > > > +
> > > > > > > + hotplug = I915_READ(SHOTPLUG_CTL_TC);
> > > > > > > + hotplug |= ICP_TC_HPD_ENABLE(PORT_TC1) |
> > > > > > > + ICP_TC_HPD_ENABLE(PORT_TC2) |
> > > > > > > + ICP_TC_HPD_ENABLE(PORT_TC3) |
> > > > > > > + ICP_TC_HPD_ENABLE(PORT_TC4);
> > > > > > > + I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
> > > > > > > +}
> > > > > > > +
> > > > > > > +static void icp_hpd_irq_setup(struct drm_i915_private
> > > > > > > *dev_priv)
> > > > > > > +{
> > > > > > > + u32 hotplug_irqs, enabled_irqs;
> > > > > > > +
> > > > > > > + hotplug_irqs = ICP_SDE_DDI_MASK | ICP_SDE_TC_MASK;
> > > > > > > + enabled_irqs = intel_hpd_enabled_irqs(dev_priv,
> > > > > > > hpd_icp);
> > > > > > > +
> > > > > > > + ibx_display_interrupt_update(dev_priv,
> > > > > > > hotplug_irqs,
> > > > > > > enabled_irqs);
> > > > > > > +
> > > > > > > + icp_hpd_detection_setup(dev_priv);
> > > > > > > +}
> > > > > > > +
> > > > > > > static void gen11_hpd_detection_setup(struct
> > > > > > > drm_i915_private
> > > > > > > *dev_priv)
> > > > > > > {
> > > > > > > u32 hotplug;
> > > > > > > @@ -3690,6 +3799,9 @@ static void
> > > > > > > gen11_hpd_irq_setup(struct
> > > > > > > drm_i915_private *dev_priv)
> > > > > > > POSTING_READ(GEN11_DE_HPD_IMR);
> > > > > > >
> > > > > > > gen11_hpd_detection_setup(dev_priv);
> > > > > > > +
> > > > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > > > + icp_hpd_irq_setup(dev_priv);
> > > > > > > }
> > > > > > >
> > > > > > > static void spt_hpd_detection_setup(struct
> > > > > > > drm_i915_private
> > > > > > > *dev_priv)
> > > > > > > @@ -4121,11 +4233,29 @@ static void
> > > > > > > gen11_gt_irq_postinstall(struct
> > > > > > > drm_i915_private *dev_priv)
> > > > > > > I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> > > > > > > }
> > > > > > >
> > > > > > > +static void icp_irq_postinstall(struct drm_device *dev)
> > > > > > > +{
> > > > > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > > > + u32 mask = ICP_GMBUS;
> > > > > > > +
> > > > > > > + WARN_ON(I915_READ(ICP_SDE_IER) != 0);
> > > > > > > + I915_WRITE(ICP_SDE_IER, 0xffffffff);
> > > > > > > + POSTING_READ(ICP_SDE_IER);
> > > > > > > +
> > > > > > > + gen3_assert_iir_is_zero(dev_priv, ICP_SDE_IIR);
> > > > > > > + I915_WRITE(ICP_SDE_IMR, ~mask);
> > > > > > > +
> > > > > > > + icp_hpd_detection_setup(dev_priv);
> > > > > > > +}
> > > > > > > +
> > > > > > > static int gen11_irq_postinstall(struct drm_device *dev)
> > > > > > > {
> > > > > > > struct drm_i915_private *dev_priv = dev-
> > > > > > > >dev_private;
> > > > > > > u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> > > > > > >
> > > > > > > + if (HAS_PCH_ICP(dev_priv))
> > > > > > > + icp_irq_postinstall(dev);
> > > > > > > +
> > > > > > > gen11_gt_irq_postinstall(dev_priv);
> > > > > > > gen8_de_irq_postinstall(dev_priv);
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > index 19600097581f..28ce96ce0484 100644
> > > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > @@ -7460,6 +7460,46 @@ enum {
> > > > > > > #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
> > > > > > > #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
> > > > > > >
> > > > > > > +/* ICP */
> > > > > > > +#define ICP_SDE_ISR _MMIO(0xc4000)
> > > > > > > +#define ICP_SDE_IMR _MMIO(0xc4004)
> > > > > > > +#define ICP_SDE_IIR _MMIO(0xc4008)
> > > > > > > +#define ICP_SDE_IER _MMIO(0xc400c)
> > > > > > These are exactly the same registers as SDE{ISR,IMR,IIR,IER}.
> > > > > > For all
> > > > > > the other platforms what we do is rather postfix the platform
> > > > > > name.
> > > > > >
> > > > > > I think we should follow what they do here.
> > > > > >
> > > > > >
> > > > > > >
> > > > > > >
> > > > > > > +#define ICP_TC4_HOTPLUG (1 << 27)
> > > > > > > +#define ICP_TC3_HOTPLUG (1 << 26)
> > > > > > > +#define ICP_TC2_HOTPLUG (1 << 25)
> > > > > > > +#define ICP_TC1_HOTPLUG (1 << 24)
> > > > > > > +#define ICP_GMBUS (1 << 23)
> > > > > > > +#define ICP_DDIB_HOTPLUG (1 << 17)
> > > > > > > +#define ICP_DDIA_HOTPLUG (1 << 16)
> > > > > > so these would become SDE_TC4_HOTPLUG_ICP and so on.
> > > > > >
> > > > > The reason I preferred this naming for gen-11 is it is
> > > > > symmetric to the
> > > > > corresponding definitions in the north engine.
> > > > >
> > > > > For example,
> > > > > +#define GEN11_DE_HPD_ISR _MMIO(0x44470)
> > > > > +#define GEN11_DE_HPD_IMR _MMIO(0x44474)
> > > > > +#define GEN11_DE_HPD_IIR _MMIO(0x44478)
> > > > > +#define GEN11_DE_HPD_IER _MMIO(0x4447c)
> > > > > +#define GEN11_TC4_HOTPLUG (1 << 19)
> > > > > +#define GEN11_TC3_HOTPLUG (1 << 18)
> > > > > +#define GEN11_TC2_HOTPLUG (1 << 17)
> > > > > +#define GEN11_TC1_HOTPLUG (1 << 16)
I see that changing ICP_TC4_HOTPLUG to SDE_TC4_HOTPLUG_ICP will align it with rest
of platform. looking at BSpec though the bitfield is named "Hotplug TypeC Port n".
Following that maybe SDE_HOTPLUG_TC4_ICP will be a good option.
This will break the symmetry with the registers in north display though....
> > > > > With interrupts getting routed to north or south engines for
> > > > > the same
> > > > > port, this naming scheme makes the duality clearer IMO.
> > > > Still the register is the same as SDEISR and there are places in
> > > > which we
> > > > read it expecting to be the same number.
> > > >
> > > > Only the bits are different, so name the bits differently as it
> > > > is for
> > > > other platforms. I think of the symmetry here just and accident
> > > > of
> > > > life expecting to be different if north and south engines don't
> > > > have the
> > > > same ports.
> > > This is on gen8_de_irq_handler() which is still used for gen11.
> > > Lucas De Marchi
> > >
> > > >
> > > >
> > > > Lucas De Marchi
> > > >
> > > > >
> > > > >
> > > > >
> > > > > >
> > > > > > >
> > > > > > >
> > > > > > > +
> > > > > > > +#define ICP_SDE_DDI_MASK (ICP_DDIB_HOTPLUG
> > > > > > > |
> > > > > > > \
> > > > > > > + ICP_DDIA_HOTPLUG)
> > > > > > > +
> > > > > > > +#define ICP_SDE_TC_MASK (ICP_TC4_HO
> > > > > > > TPLUG |
> > > > > > > \
> > > > > > > + ICP_TC3_HOTPLUG |
> > > > > > >
> > > > > > > \
> > > > > > > + ICP_TC2_HOTPLUG |
> > > > > > >
> > > > > > > \
> > > > > > > + ICP_TC1_HOTPLUG)
> > > > > > > +
> > > > > > > +#define SHOTPLUG_CTL_DDI _MMIO(0xc4
> > > > > > > 030)
> > > > > > > /* SHOTPLUG_CTL */
> > > > > > This also seems to reuse what we have defined as
> > > > > > PCH_PORT_HOTPLUG
> > > > > > with a
> > > > > > comment to SHOTPLUG_CTL there, although here I tend to be in
> > > > > > favor of
> > > > > > using the current real name of the register (SHOTPLUG_CTL).
> > > > > The real name I see is SHOTPLUG_CTL_DDI for ICP.
That is correct.
> > > > > I don't believe we should attempt to make these definitions
> > > > > consistent
> > > > > with previous platforms over making them consistent with each
> > > > > other.
> > > > >
> If you want to retain the original definition PCH_HOTPLUG, appending to
> the existing comment that the register is called SHOTPLUG_CTL_DDI on
> ICP would be nice.
So have the PCH_HOTPLUG define and the new SHOTPLUG_CTL_DDI with comment
addressing that they are the same registers but keeping the name consistent with BSpec
should suffice?
Thanks,
Anusha
__ _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Anusha Srivatsa
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (4 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 05/24] drm/i915/icp: Add Interrupt Support Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-05-25 0:26 ` Paulo Zanoni
` (2 more replies)
2018-05-22 0:25 ` [PATCH 07/24] drm/i915/icl: Add DDI HDMI level selection for ICL Paulo Zanoni
` (34 subsequent siblings)
40 siblings, 3 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Manasi Navare <manasi.d.navare@intel.com>
DFLEXDPMLE register is required to tell the FIA hardware which
main links of DP are enabled on TCC Connectors. FIA uses this
information to program PHY to Controller signal mapping.
This register is applicable in both TC connector's Alternate mode
as well as DP connector mode.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 28ce96ce0484..7f27fe2e38c7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1990,6 +1990,11 @@ enum i915_power_well_id {
_ICL_PORT_COMP_DW10_A, \
_ICL_PORT_COMP_DW10_B)
+/* ICL PHY DFLEX registers */
+#define ICL_PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
+#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
+#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
+
/* BXT PHY Ref registers */
#define _PORT_REF_DW3_A 0x16218C
#define _PORT_REF_DW3_BC 0x6C18C
--
2.14.3
_______________________________________________
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^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE
2018-05-22 0:25 ` [PATCH 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE Paulo Zanoni
@ 2018-05-25 0:26 ` Paulo Zanoni
2018-05-25 16:14 ` Lucas De Marchi
2018-05-25 18:52 ` [PATCH v2 " Manasi Navare
2018-05-25 19:03 ` [PATCH v3 06/24] drm/i915/icl: " Manasi Navare
2 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-25 0:26 UTC (permalink / raw)
To: intel-gfx
Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> From: Manasi Navare <manasi.d.navare@intel.com>
>
> DFLEXDPMLE register is required to tell the FIA hardware which
> main links of DP are enabled on TCC Connectors. FIA uses this
> information to program PHY to Controller signal mapping.
> This register is applicable in both TC connector's Alternate mode
> as well as DP connector mode.
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 28ce96ce0484..7f27fe2e38c7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1990,6 +1990,11 @@ enum i915_power_well_id {
> _ICL_PORT_COMP_DW
> 10_A, \
> _ICL_PORT_COMP_DW
> 10_B)
>
> +/* ICL PHY DFLEX registers */
> +#define ICL_PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
We can probably remove the ICL_ prefix since the register did not exist
before.
With or without that:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Note: the patch that uses the register was removed from the series due
to some problems identified. Will be upstreamed as soon as it's fixed.
> +#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
> +#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
> +
> /* BXT PHY Ref registers */
> #define _PORT_REF_DW3_A 0x16218C
> #define _PORT_REF_DW3_BC 0x6C18C
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE
2018-05-25 0:26 ` Paulo Zanoni
@ 2018-05-25 16:14 ` Lucas De Marchi
2018-05-25 16:58 ` Manasi Navare
0 siblings, 1 reply; 127+ messages in thread
From: Lucas De Marchi @ 2018-05-25 16:14 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Thu, May 24, 2018 at 05:26:38PM -0700, Paulo Zanoni wrote:
> Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> > From: Manasi Navare <manasi.d.navare@intel.com>
> >
> > DFLEXDPMLE register is required to tell the FIA hardware which
> > main links of DP are enabled on TCC Connectors. FIA uses this
> > information to program PHY to Controller signal mapping.
> > This register is applicable in both TC connector's Alternate mode
> > as well as DP connector mode.
> >
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Animesh Manna <animesh.manna@intel.com>
> > Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 28ce96ce0484..7f27fe2e38c7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1990,6 +1990,11 @@ enum i915_power_well_id {
> > _ICL_PORT_COMP_DW
> > 10_A, \
> > _ICL_PORT_COMP_DW
> > 10_B)
> >
> > +/* ICL PHY DFLEX registers */
> > +#define ICL_PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
>
> We can probably remove the ICL_ prefix since the register did not exist
> before.
And while at it s/ICL/icl/ in the commit message?
Lucas De Marchi
>
> With or without that:
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Note: the patch that uses the register was removed from the series due
> to some problems identified. Will be upstreamed as soon as it's fixed.
>
> > +#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
> > +#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
> > +
> > /* BXT PHY Ref registers */
> > #define _PORT_REF_DW3_A 0x16218C
> > #define _PORT_REF_DW3_BC 0x6C18C
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE
2018-05-25 16:14 ` Lucas De Marchi
@ 2018-05-25 16:58 ` Manasi Navare
0 siblings, 0 replies; 127+ messages in thread
From: Manasi Navare @ 2018-05-25 16:58 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Paulo Zanoni
On Fri, May 25, 2018 at 09:14:57AM -0700, Lucas De Marchi wrote:
> On Thu, May 24, 2018 at 05:26:38PM -0700, Paulo Zanoni wrote:
> > Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> > > From: Manasi Navare <manasi.d.navare@intel.com>
> > >
> > > DFLEXDPMLE register is required to tell the FIA hardware which
> > > main links of DP are enabled on TCC Connectors. FIA uses this
> > > information to program PHY to Controller signal mapping.
> > > This register is applicable in both TC connector's Alternate mode
> > > as well as DP connector mode.
> > >
> > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > Cc: Animesh Manna <animesh.manna@intel.com>
> > > Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> > > 1 file changed, 5 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 28ce96ce0484..7f27fe2e38c7 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -1990,6 +1990,11 @@ enum i915_power_well_id {
> > > _ICL_PORT_COMP_DW
> > > 10_A, \
> > > _ICL_PORT_COMP_DW
> > > 10_B)
> > >
> > > +/* ICL PHY DFLEX registers */
> > > +#define ICL_PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> >
> > We can probably remove the ICL_ prefix since the register did not exist
> > before.
>
Yes I agree this ICL prefix should be removed like I did for all the MG PHY regs too.
> And while at it s/ICL/icl/ in the commit message?
>
> Lucas De Marchi
>
And yes will change this as well in the commit message.
Thanks for the review.
Manasi
> >
> > With or without that:
> > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > Note: the patch that uses the register was removed from the series due
> > to some problems identified. Will be upstreamed as soon as it's fixed.
> >
> > > +#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
> > > +#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
> > > +
> > > /* BXT PHY Ref registers */
> > > #define _PORT_REF_DW3_A 0x16218C
> > > #define _PORT_REF_DW3_BC 0x6C18C
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH v2 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE
2018-05-22 0:25 ` [PATCH 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE Paulo Zanoni
2018-05-25 0:26 ` Paulo Zanoni
@ 2018-05-25 18:52 ` Manasi Navare
2018-05-25 19:03 ` [PATCH v3 06/24] drm/i915/icl: " Manasi Navare
2 siblings, 0 replies; 127+ messages in thread
From: Manasi Navare @ 2018-05-25 18:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
DFLEXDPMLE register is required to tell the FIA hardware which
main links of DP are enabled on TCC Connectors. FIA uses this
information to program PHY to Controller signal mapping.
This register is applicable in both TC connector's Alternate mode
as well as DP connector mode.
v2:
* Remove _ICL prefix since the reg is first introduced
in ICL (Paulo)
* s/ICL/icl in commit message (Lucas)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6953419..01573e8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1990,6 +1990,11 @@ enum i915_power_well_id {
_ICL_PORT_COMP_DW10_A, \
_ICL_PORT_COMP_DW10_B)
+/* ICL PHY DFLEX registers */
+#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
+#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
+#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
+
/* BXT PHY Ref registers */
#define _PORT_REF_DW3_A 0x16218C
#define _PORT_REF_DW3_BC 0x6C18C
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* [PATCH v3 06/24] drm/i915/icl: Add register definition for DFLEXDPMLE
2018-05-22 0:25 ` [PATCH 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE Paulo Zanoni
2018-05-25 0:26 ` Paulo Zanoni
2018-05-25 18:52 ` [PATCH v2 " Manasi Navare
@ 2018-05-25 19:03 ` Manasi Navare
2 siblings, 0 replies; 127+ messages in thread
From: Manasi Navare @ 2018-05-25 19:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
DFLEXDPMLE register is required to tell the FIA hardware which
main links of DP are enabled on TCC Connectors. FIA uses this
information to program PHY to Controller signal mapping.
This register is applicable in both TC connector's Alternate mode
as well as DP connector mode.
v2:
* Remove _ICL prefix since the reg is first introduced
in ICL (Paulo)
* s/ICL/icl in commit message (Lucas)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6953419..01573e8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1990,6 +1990,11 @@ enum i915_power_well_id {
_ICL_PORT_COMP_DW10_A, \
_ICL_PORT_COMP_DW10_B)
+/* ICL PHY DFLEX registers */
+#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
+#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
+#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
+
/* BXT PHY Ref registers */
#define _PORT_REF_DW3_A 0x16218C
#define _PORT_REF_DW3_BC 0x6C18C
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH 07/24] drm/i915/icl: Add DDI HDMI level selection for ICL
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (5 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-05-25 16:26 ` Lucas De Marchi
2018-05-22 0:25 ` [PATCH 08/24] drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin Paulo Zanoni
` (33 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi, Paulo Zanoni
From: Manasi Navare <manasi.d.navare@intel.com>
This patch adds a proper HDMI DDI entry level for vswing
programming sequences on ICL.
Spec doesn't specify any default for HDMI tables,
so let's pick the last entry as the default for now
to stay consistent with older platform like CNL.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rakshmi Bhatia <rakshmi.bhatia@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1665bc588241..d8ae82001f83 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -915,7 +915,14 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
- if (IS_CANNONLAKE(dev_priv)) {
+ if (IS_ICELAKE(dev_priv)) {
+ if (port == PORT_A || port == PORT_B)
+ icl_get_combo_buf_trans(dev_priv, port,
+ INTEL_OUTPUT_HDMI, &n_entries);
+ else
+ n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
+ default_entry = n_entries - 1;
+ } else if (IS_CANNONLAKE(dev_priv)) {
cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
default_entry = n_entries - 1;
} else if (IS_GEN9_LP(dev_priv)) {
--
2.14.3
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^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 07/24] drm/i915/icl: Add DDI HDMI level selection for ICL
2018-05-22 0:25 ` [PATCH 07/24] drm/i915/icl: Add DDI HDMI level selection for ICL Paulo Zanoni
@ 2018-05-25 16:26 ` Lucas De Marchi
2018-06-01 22:32 ` Paulo Zanoni
0 siblings, 1 reply; 127+ messages in thread
From: Lucas De Marchi @ 2018-05-25 16:26 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Rodrigo Vivi
On Mon, May 21, 2018 at 05:25:41PM -0700, Paulo Zanoni wrote:
> From: Manasi Navare <manasi.d.navare@intel.com>
>
> This patch adds a proper HDMI DDI entry level for vswing
> programming sequences on ICL.
>
> Spec doesn't specify any default for HDMI tables,
> so let's pick the last entry as the default for now
> to stay consistent with older platform like CNL.
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rakshmi Bhatia <rakshmi.bhatia@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 1665bc588241..d8ae82001f83 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -915,7 +915,14 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>
> level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>
> - if (IS_CANNONLAKE(dev_priv)) {
> + if (IS_ICELAKE(dev_priv)) {
> + if (port == PORT_A || port == PORT_B)
This should be using the helper you introduced in patch 3. Either a
'if (!intel_port_is_tc()' or add a 'if (intel_port_is_combo)'.
With that,
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> + icl_get_combo_buf_trans(dev_priv, port,
> + INTEL_OUTPUT_HDMI, &n_entries);
> + else
> + n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
> + default_entry = n_entries - 1;
> + } else if (IS_CANNONLAKE(dev_priv)) {
> cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
> default_entry = n_entries - 1;
> } else if (IS_GEN9_LP(dev_priv)) {
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 07/24] drm/i915/icl: Add DDI HDMI level selection for ICL
2018-05-25 16:26 ` Lucas De Marchi
@ 2018-06-01 22:32 ` Paulo Zanoni
2018-06-11 23:51 ` Lucas De Marchi
0 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-06-01 22:32 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Rodrigo Vivi
Em Sex, 2018-05-25 às 09:26 -0700, Lucas De Marchi escreveu:
> On Mon, May 21, 2018 at 05:25:41PM -0700, Paulo Zanoni wrote:
> > From: Manasi Navare <manasi.d.navare@intel.com>
> >
> > This patch adds a proper HDMI DDI entry level for vswing
> > programming sequences on ICL.
> >
> > Spec doesn't specify any default for HDMI tables,
> > so let's pick the last entry as the default for now
> > to stay consistent with older platform like CNL.
> >
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Rakshmi Bhatia <rakshmi.bhatia@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 9 ++++++++-
> > 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 1665bc588241..d8ae82001f83 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -915,7 +915,14 @@ static int intel_ddi_hdmi_level(struct
> > drm_i915_private *dev_priv, enum port por
> >
> > level = dev_priv-
> > >vbt.ddi_port_info[port].hdmi_level_shift;
> >
> > - if (IS_CANNONLAKE(dev_priv)) {
> > + if (IS_ICELAKE(dev_priv)) {
> > + if (port == PORT_A || port == PORT_B)
>
> This should be using the helper you introduced in patch 3. Either a
> 'if (!intel_port_is_tc()' or add a 'if (intel_port_is_combo)'.
>
> With that,
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
I don't think the !intel_port_is_tc() is a good call, and we don't have
the intel_port_is_combo() as part of the ICL series, although we could
have done it. Perhaps when we actually submit the patch adding
intel_port_is_combo() then we can fix this issue on that patch? It
would also help justifying the patch's existence.
>
> Lucas De Marchi
>
> > + icl_get_combo_buf_trans(dev_priv, port,
> > + INTEL_OUTPUT_HDMI,
> > &n_entries);
> > + else
> > + n_entries =
> > ARRAY_SIZE(icl_mg_phy_ddi_translations);
> > + default_entry = n_entries - 1;
> > + } else if (IS_CANNONLAKE(dev_priv)) {
> > cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
> > default_entry = n_entries - 1;
> > } else if (IS_GEN9_LP(dev_priv)) {
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 07/24] drm/i915/icl: Add DDI HDMI level selection for ICL
2018-06-01 22:32 ` Paulo Zanoni
@ 2018-06-11 23:51 ` Lucas De Marchi
0 siblings, 0 replies; 127+ messages in thread
From: Lucas De Marchi @ 2018-06-11 23:51 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Rodrigo Vivi
On Fri, Jun 1, 2018 at 3:32 PM Paulo Zanoni <paulo.r.zanoni@intel.com> wrote:
>
> Em Sex, 2018-05-25 às 09:26 -0700, Lucas De Marchi escreveu:
> > On Mon, May 21, 2018 at 05:25:41PM -0700, Paulo Zanoni wrote:
> > > From: Manasi Navare <manasi.d.navare@intel.com>
> > >
> > > This patch adds a proper HDMI DDI entry level for vswing
> > > programming sequences on ICL.
> > >
> > > Spec doesn't specify any default for HDMI tables,
> > > so let's pick the last entry as the default for now
> > > to stay consistent with older platform like CNL.
> > >
> > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > Cc: Rakshmi Bhatia <rakshmi.bhatia@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_ddi.c | 9 ++++++++-
> > > 1 file changed, 8 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > index 1665bc588241..d8ae82001f83 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -915,7 +915,14 @@ static int intel_ddi_hdmi_level(struct
> > > drm_i915_private *dev_priv, enum port por
> > >
> > > level = dev_priv-
> > > >vbt.ddi_port_info[port].hdmi_level_shift;
> > >
> > > - if (IS_CANNONLAKE(dev_priv)) {
> > > + if (IS_ICELAKE(dev_priv)) {
> > > + if (port == PORT_A || port == PORT_B)
> >
> > This should be using the helper you introduced in patch 3. Either a
> > 'if (!intel_port_is_tc()' or add a 'if (intel_port_is_combo)'.
> >
> > With that,
> >
> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> I don't think the !intel_port_is_tc() is a good call, and we don't have
> the intel_port_is_combo() as part of the ICL series, although we could
> have done it. Perhaps when we actually submit the patch adding
> intel_port_is_combo() then we can fix this issue on that patch? It
ok, I stand my r-b without it.
Lucas De Marchi
> would also help justifying the patch's existence.
>
> >
> > Lucas De Marchi
> >
> > > + icl_get_combo_buf_trans(dev_priv, port,
> > > + INTEL_OUTPUT_HDMI,
> > > &n_entries);
> > > + else
> > > + n_entries =
> > > ARRAY_SIZE(icl_mg_phy_ddi_translations);
> > > + default_entry = n_entries - 1;
> > > + } else if (IS_CANNONLAKE(dev_priv)) {
> > > cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
> > > default_entry = n_entries - 1;
> > > } else if (IS_GEN9_LP(dev_priv)) {
> > > --
> > > 2.14.3
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 08/24] drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (6 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 07/24] drm/i915/icl: Add DDI HDMI level selection for ICL Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-05-23 19:43 ` James Ausmus
2018-05-22 0:25 ` [PATCH 09/24] drm/i915/icl: Add Icelake PCH detection Paulo Zanoni
` (32 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Jani Nikula, Rodrigo Vivi
From: "Sripada, Radhakrishna" <radhakrishna.sripada@intel.com>
On ICL we need to map VBT DDC Pin to BSpec DDC Pin.
Adding ICL Pin Values.
According to VBT
Block 2 (General Bytes Definition)
DDC Bus
+----------+-----------+--------------------+
| DDI Type | VBT Value | BSpec Mapped Value |
+----------+-----------+--------------------+
| DDI-A | 0x1 | 0x1 |
| DDI-B | 0x2 | 0x2 |
| PORT-1 | 0x4 | 0x9 |
| PORT-2 | 0x5 | 0xA |
| PORT-3 | 0x6 | 0xB |
| PORT-4 | 0x7 | 0xC |
+----------+-----------+--------------------+
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
[Paulo: checkpatch fixes.]
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_bios.c | 35 +++++++++++++++++++++++++++--------
drivers/gpu/drm/i915/intel_vbt_defs.h | 6 ++++++
2 files changed, 33 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 54270bdde100..34e9bca36c14 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1197,18 +1197,37 @@ static const u8 cnp_ddc_pin_map[] = {
[DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */
};
+static const u8 icp_ddc_pin_map[] = {
+ [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+ [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+ [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
+ [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
+ [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
+ [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
+};
+
static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
{
- if (HAS_PCH_CNP(dev_priv)) {
- if (vbt_pin < ARRAY_SIZE(cnp_ddc_pin_map)) {
- return cnp_ddc_pin_map[vbt_pin];
- } else {
- DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", vbt_pin);
- return 0;
- }
+ const u8 *ddc_pin_map;
+ int n_entries;
+
+ if (HAS_PCH_ICP(dev_priv)) {
+ ddc_pin_map = icp_ddc_pin_map;
+ n_entries = ARRAY_SIZE(icp_ddc_pin_map);
+ } else if (HAS_PCH_CNP(dev_priv)) {
+ ddc_pin_map = cnp_ddc_pin_map;
+ n_entries = ARRAY_SIZE(cnp_ddc_pin_map);
+ } else {
+ /* Assuming direct map */
+ return vbt_pin;
}
- return vbt_pin;
+ if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0)
+ return ddc_pin_map[vbt_pin];
+
+ DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n",
+ vbt_pin);
+ return 0;
}
static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index 458468237b5f..7c798c18600e 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -318,6 +318,12 @@ enum vbt_gmbus_ddi {
DDC_BUS_DDI_C,
DDC_BUS_DDI_D,
DDC_BUS_DDI_F,
+ ICL_DDC_BUS_DDI_A = 0x1,
+ ICL_DDC_BUS_DDI_B,
+ ICL_DDC_BUS_PORT_1 = 0x4,
+ ICL_DDC_BUS_PORT_2,
+ ICL_DDC_BUS_PORT_3,
+ ICL_DDC_BUS_PORT_4,
};
#define VBT_DP_MAX_LINK_RATE_HBR3 0
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 08/24] drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
2018-05-22 0:25 ` [PATCH 08/24] drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin Paulo Zanoni
@ 2018-05-23 19:43 ` James Ausmus
0 siblings, 0 replies; 127+ messages in thread
From: James Ausmus @ 2018-05-23 19:43 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: Jani Nikula, intel-gfx, Rodrigo Vivi
On Mon, May 21, 2018 at 05:25:42PM -0700, Paulo Zanoni wrote:
> From: "Sripada, Radhakrishna" <radhakrishna.sripada@intel.com>
>
> On ICL we need to map VBT DDC Pin to BSpec DDC Pin.
> Adding ICL Pin Values.
>
> According to VBT
> Block 2 (General Bytes Definition)
> DDC Bus
>
> +----------+-----------+--------------------+
> | DDI Type | VBT Value | BSpec Mapped Value |
> +----------+-----------+--------------------+
> | DDI-A | 0x1 | 0x1 |
> | DDI-B | 0x2 | 0x2 |
> | PORT-1 | 0x4 | 0x9 |
> | PORT-2 | 0x5 | 0xA |
> | PORT-3 | 0x6 | 0xB |
> | PORT-4 | 0x7 | 0xC |
> +----------+-----------+--------------------+
>
> Cc: James Ausmus <james.ausmus@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Clinton Taylor <clinton.a.taylor@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> [Paulo: checkpatch fixes.]
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Matches BSpec, looks good!
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/intel_bios.c | 35 +++++++++++++++++++++++++++--------
> drivers/gpu/drm/i915/intel_vbt_defs.h | 6 ++++++
> 2 files changed, 33 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 54270bdde100..34e9bca36c14 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1197,18 +1197,37 @@ static const u8 cnp_ddc_pin_map[] = {
> [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */
> };
>
> +static const u8 icp_ddc_pin_map[] = {
> + [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
> + [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
> + [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
> + [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
> + [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
> + [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
> +};
> +
> static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
> {
> - if (HAS_PCH_CNP(dev_priv)) {
> - if (vbt_pin < ARRAY_SIZE(cnp_ddc_pin_map)) {
> - return cnp_ddc_pin_map[vbt_pin];
> - } else {
> - DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", vbt_pin);
> - return 0;
> - }
> + const u8 *ddc_pin_map;
> + int n_entries;
> +
> + if (HAS_PCH_ICP(dev_priv)) {
> + ddc_pin_map = icp_ddc_pin_map;
> + n_entries = ARRAY_SIZE(icp_ddc_pin_map);
> + } else if (HAS_PCH_CNP(dev_priv)) {
> + ddc_pin_map = cnp_ddc_pin_map;
> + n_entries = ARRAY_SIZE(cnp_ddc_pin_map);
> + } else {
> + /* Assuming direct map */
> + return vbt_pin;
> }
>
> - return vbt_pin;
> + if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0)
> + return ddc_pin_map[vbt_pin];
> +
> + DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n",
> + vbt_pin);
> + return 0;
> }
>
> static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
> index 458468237b5f..7c798c18600e 100644
> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> @@ -318,6 +318,12 @@ enum vbt_gmbus_ddi {
> DDC_BUS_DDI_C,
> DDC_BUS_DDI_D,
> DDC_BUS_DDI_F,
> + ICL_DDC_BUS_DDI_A = 0x1,
> + ICL_DDC_BUS_DDI_B,
> + ICL_DDC_BUS_PORT_1 = 0x4,
> + ICL_DDC_BUS_PORT_2,
> + ICL_DDC_BUS_PORT_3,
> + ICL_DDC_BUS_PORT_4,
> };
>
> #define VBT_DP_MAX_LINK_RATE_HBR3 0
> --
> 2.14.3
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 09/24] drm/i915/icl: Add Icelake PCH detection
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (7 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 08/24] drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-05-25 0:29 ` Paulo Zanoni
2018-05-22 0:25 ` [PATCH 10/24] drm/i915/icl: add icelake_get_ddi_pll() Paulo Zanoni
` (31 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
This patch adds the support to detect PCH_ICP.
Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9c449b8d8eab..7b6f64321f11 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -233,6 +233,8 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
+ else if (IS_ICELAKE(dev_priv))
+ id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
if (id)
DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 09/24] drm/i915/icl: Add Icelake PCH detection
2018-05-22 0:25 ` [PATCH 09/24] drm/i915/icl: Add Icelake PCH detection Paulo Zanoni
@ 2018-05-25 0:29 ` Paulo Zanoni
0 siblings, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-25 0:29 UTC (permalink / raw)
To: intel-gfx
Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> This patch adds the support to detect PCH_ICP.
>
> Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 9c449b8d8eab..7b6f64321f11 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -233,6 +233,8 @@ intel_virt_detect_pch(const struct
> drm_i915_private *dev_priv)
> id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
> else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
> id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
> + else if (IS_ICELAKE(dev_priv))
> + id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
>
> if (id)
> DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 10/24] drm/i915/icl: add icelake_get_ddi_pll()
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (8 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 09/24] drm/i915/icl: Add Icelake PCH detection Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-06-13 23:15 ` Lucas De Marchi
2018-05-22 0:25 ` [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs Paulo Zanoni
` (30 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Implement the hardware state readout code.
Thanks to Animesh Manna for spotting this problem.
Cc: Animesh Manna <animesh.manna@intel.com>
Credits-to: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 42 +++++++++++++++++++++++++++++++++++-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 64593b0fbebd..d5a19c1b3b20 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9146,6 +9146,44 @@ static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
}
+static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
+ enum port port,
+ struct intel_crtc_state *pipe_config)
+{
+ enum intel_dpll_id id;
+ u32 temp;
+
+ /* TODO: TBT pll not implemented. */
+ switch (port) {
+ case PORT_A:
+ case PORT_B:
+ temp = I915_READ(DPCLKA_CFGCR0_ICL) &
+ DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+ id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
+
+ if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
+ return;
+ break;
+ case PORT_C:
+ id = DPLL_ID_ICL_MGPLL1;
+ break;
+ case PORT_D:
+ id = DPLL_ID_ICL_MGPLL2;
+ break;
+ case PORT_E:
+ id = DPLL_ID_ICL_MGPLL3;
+ break;
+ case PORT_F:
+ id = DPLL_ID_ICL_MGPLL4;
+ break;
+ default:
+ MISSING_CASE(port);
+ return;
+ }
+
+ pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
+}
+
static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
enum port port,
struct intel_crtc_state *pipe_config)
@@ -9333,7 +9371,9 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
- if (IS_CANNONLAKE(dev_priv))
+ if (IS_ICELAKE(dev_priv))
+ icelake_get_ddi_pll(dev_priv, port, pipe_config);
+ else if (IS_CANNONLAKE(dev_priv))
cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_GEN9_BC(dev_priv))
skylake_get_ddi_pll(dev_priv, port, pipe_config);
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 10/24] drm/i915/icl: add icelake_get_ddi_pll()
2018-05-22 0:25 ` [PATCH 10/24] drm/i915/icl: add icelake_get_ddi_pll() Paulo Zanoni
@ 2018-06-13 23:15 ` Lucas De Marchi
2018-06-13 23:51 ` Paulo Zanoni
0 siblings, 1 reply; 127+ messages in thread
From: Lucas De Marchi @ 2018-06-13 23:15 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Mon, May 21, 2018 at 05:25:44PM -0700, Paulo Zanoni wrote:
> Implement the hardware state readout code.
>
> Thanks to Animesh Manna for spotting this problem.
>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Credits-to: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 42 +++++++++++++++++++++++++++++++++++-
> 1 file changed, 41 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 64593b0fbebd..d5a19c1b3b20 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9146,6 +9146,44 @@ static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
> pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
> }
>
> +static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
> + enum port port,
> + struct intel_crtc_state *pipe_config)
> +{
> + enum intel_dpll_id id;
> + u32 temp;
> +
> + /* TODO: TBT pll not implemented. */
> + switch (port) {
> + case PORT_A:
> + case PORT_B:
> + temp = I915_READ(DPCLKA_CFGCR0_ICL) &
> + DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> + id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
This could be simpler:
temp = I915_READ(DPCLKA_CFGCR0_ICL) >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
id = temp & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(0);
But this ship has sailed, aka MASK above requires the port and
hardcoding 0 doesn't make it better IMO.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> +
> + if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
> + return;
> + break;
> + case PORT_C:
> + id = DPLL_ID_ICL_MGPLL1;
> + break;
> + case PORT_D:
> + id = DPLL_ID_ICL_MGPLL2;
> + break;
> + case PORT_E:
> + id = DPLL_ID_ICL_MGPLL3;
> + break;
> + case PORT_F:
> + id = DPLL_ID_ICL_MGPLL4;
> + break;
> + default:
> + MISSING_CASE(port);
> + return;
> + }
> +
> + pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
> +}
> +
> static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
> enum port port,
> struct intel_crtc_state *pipe_config)
> @@ -9333,7 +9371,9 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>
> port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
>
> - if (IS_CANNONLAKE(dev_priv))
> + if (IS_ICELAKE(dev_priv))
> + icelake_get_ddi_pll(dev_priv, port, pipe_config);
> + else if (IS_CANNONLAKE(dev_priv))
> cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
> else if (IS_GEN9_BC(dev_priv))
> skylake_get_ddi_pll(dev_priv, port, pipe_config);
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 10/24] drm/i915/icl: add icelake_get_ddi_pll()
2018-06-13 23:15 ` Lucas De Marchi
@ 2018-06-13 23:51 ` Paulo Zanoni
2018-06-13 23:55 ` Lucas De Marchi
0 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-06-13 23:51 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
Em Qua, 2018-06-13 às 16:15 -0700, Lucas De Marchi escreveu:
> On Mon, May 21, 2018 at 05:25:44PM -0700, Paulo Zanoni wrote:
> > Implement the hardware state readout code.
> >
> > Thanks to Animesh Manna for spotting this problem.
> >
> > Cc: Animesh Manna <animesh.manna@intel.com>
> > Credits-to: Animesh Manna <animesh.manna@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 42
> > +++++++++++++++++++++++++++++++++++-
> > 1 file changed, 41 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 64593b0fbebd..d5a19c1b3b20 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -9146,6 +9146,44 @@ static void cannonlake_get_ddi_pll(struct
> > drm_i915_private *dev_priv,
> > pipe_config->shared_dpll =
> > intel_get_shared_dpll_by_id(dev_priv, id);
> > }
> >
> > +static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
> > + enum port port,
> > + struct intel_crtc_state
> > *pipe_config)
> > +{
> > + enum intel_dpll_id id;
> > + u32 temp;
> > +
> > + /* TODO: TBT pll not implemented. */
> > + switch (port) {
> > + case PORT_A:
> > + case PORT_B:
> > + temp = I915_READ(DPCLKA_CFGCR0_ICL) &
> > + DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> > + id = temp >>
> > DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
>
> This could be simpler:
>
> temp = I915_READ(DPCLKA_CFGCR0_ICL) >>
> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> id = temp & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(0);
I fail to understand why this is simpler... The same operations, just
on a different order.
>
> But this ship has sailed, aka MASK above requires the port and
> hardcoding 0 doesn't make it better IMO.
>
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
Thanks!
>
> Lucas De Marchi
>
> > +
> > + if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id !=
> > DPLL_ID_ICL_DPLL1))
> > + return;
> > + break;
> > + case PORT_C:
> > + id = DPLL_ID_ICL_MGPLL1;
> > + break;
> > + case PORT_D:
> > + id = DPLL_ID_ICL_MGPLL2;
> > + break;
> > + case PORT_E:
> > + id = DPLL_ID_ICL_MGPLL3;
> > + break;
> > + case PORT_F:
> > + id = DPLL_ID_ICL_MGPLL4;
> > + break;
> > + default:
> > + MISSING_CASE(port);
> > + return;
> > + }
> > +
> > + pipe_config->shared_dpll =
> > intel_get_shared_dpll_by_id(dev_priv, id);
> > +}
> > +
> > static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
> > enum port port,
> > struct intel_crtc_state
> > *pipe_config)
> > @@ -9333,7 +9371,9 @@ static void haswell_get_ddi_port_state(struct
> > intel_crtc *crtc,
> >
> > port = (tmp & TRANS_DDI_PORT_MASK) >>
> > TRANS_DDI_PORT_SHIFT;
> >
> > - if (IS_CANNONLAKE(dev_priv))
> > + if (IS_ICELAKE(dev_priv))
> > + icelake_get_ddi_pll(dev_priv, port, pipe_config);
> > + else if (IS_CANNONLAKE(dev_priv))
> > cannonlake_get_ddi_pll(dev_priv, port,
> > pipe_config);
> > else if (IS_GEN9_BC(dev_priv))
> > skylake_get_ddi_pll(dev_priv, port, pipe_config);
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 10/24] drm/i915/icl: add icelake_get_ddi_pll()
2018-06-13 23:51 ` Paulo Zanoni
@ 2018-06-13 23:55 ` Lucas De Marchi
0 siblings, 0 replies; 127+ messages in thread
From: Lucas De Marchi @ 2018-06-13 23:55 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Wed, Jun 13, 2018 at 04:51:57PM -0700, Paulo Zanoni wrote:
> Em Qua, 2018-06-13 às 16:15 -0700, Lucas De Marchi escreveu:
> > On Mon, May 21, 2018 at 05:25:44PM -0700, Paulo Zanoni wrote:
> > > Implement the hardware state readout code.
> > >
> > > Thanks to Animesh Manna for spotting this problem.
> > >
> > > Cc: Animesh Manna <animesh.manna@intel.com>
> > > Credits-to: Animesh Manna <animesh.manna@intel.com>
> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 42
> > > +++++++++++++++++++++++++++++++++++-
> > > 1 file changed, 41 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 64593b0fbebd..d5a19c1b3b20 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -9146,6 +9146,44 @@ static void cannonlake_get_ddi_pll(struct
> > > drm_i915_private *dev_priv,
> > > pipe_config->shared_dpll =
> > > intel_get_shared_dpll_by_id(dev_priv, id);
> > > }
> > >
> > > +static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
> > > + enum port port,
> > > + struct intel_crtc_state
> > > *pipe_config)
> > > +{
> > > + enum intel_dpll_id id;
> > > + u32 temp;
> > > +
> > > + /* TODO: TBT pll not implemented. */
> > > + switch (port) {
> > > + case PORT_A:
> > > + case PORT_B:
> > > + temp = I915_READ(DPCLKA_CFGCR0_ICL) &
> > > + DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> > > + id = temp >>
> > > DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> >
> > This could be simpler:
> >
> > temp = I915_READ(DPCLKA_CFGCR0_ICL) >>
> > DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> > id = temp & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(0);
>
> I fail to understand why this is simpler... The same operations, just
> on a different order.
If you open up the macros you will see there are more operations on what
we are doing right now... and we wouldn't need to depend on the port for
this if we had done this way. However we already depend on having the
port as an argument in other places, so there's nothing to do
differently on this particular patch.
Lucas De Marchi
>
>
> >
> > But this ship has sailed, aka MASK above requires the port and
> > hardcoding 0 doesn't make it better IMO.
> >
> >
> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >
>
> Thanks!
>
> >
> > Lucas De Marchi
> >
> > > +
> > > + if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id !=
> > > DPLL_ID_ICL_DPLL1))
> > > + return;
> > > + break;
> > > + case PORT_C:
> > > + id = DPLL_ID_ICL_MGPLL1;
> > > + break;
> > > + case PORT_D:
> > > + id = DPLL_ID_ICL_MGPLL2;
> > > + break;
> > > + case PORT_E:
> > > + id = DPLL_ID_ICL_MGPLL3;
> > > + break;
> > > + case PORT_F:
> > > + id = DPLL_ID_ICL_MGPLL4;
> > > + break;
> > > + default:
> > > + MISSING_CASE(port);
> > > + return;
> > > + }
> > > +
> > > + pipe_config->shared_dpll =
> > > intel_get_shared_dpll_by_id(dev_priv, id);
> > > +}
> > > +
> > > static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
> > > enum port port,
> > > struct intel_crtc_state
> > > *pipe_config)
> > > @@ -9333,7 +9371,9 @@ static void haswell_get_ddi_port_state(struct
> > > intel_crtc *crtc,
> > >
> > > port = (tmp & TRANS_DDI_PORT_MASK) >>
> > > TRANS_DDI_PORT_SHIFT;
> > >
> > > - if (IS_CANNONLAKE(dev_priv))
> > > + if (IS_ICELAKE(dev_priv))
> > > + icelake_get_ddi_pll(dev_priv, port, pipe_config);
> > > + else if (IS_CANNONLAKE(dev_priv))
> > > cannonlake_get_ddi_pll(dev_priv, port,
> > > pipe_config);
> > > else if (IS_GEN9_BC(dev_priv))
> > > skylake_get_ddi_pll(dev_priv, port, pipe_config);
> > > --
> > > 2.14.3
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs.
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (9 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 10/24] drm/i915/icl: add icelake_get_ddi_pll() Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-05-22 11:44 ` Mika Kahola
` (2 more replies)
2018-05-22 0:25 ` [PATCH 12/24] drm/i915/icl: Calculate link clock using the new registers Paulo Zanoni
` (29 subsequent siblings)
40 siblings, 3 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Paulo Zanoni, Rodrigo Vivi
From: Manasi Navare <manasi.d.navare@intel.com>
PLLs are the source clocks for the DDIs so in order
to determine the ddi clock we need to check the PLL
configuration.
This gets a little tricky for ICL since there is
no register bit that maps directly to the link clock.
So this patch creates a separate function in intel_dpll_mgr.c
to obtain the write array PLL Params and compares the set
pll_params with the table to get the corresponding link
clock.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gpu/drm/i915/intel_ddi.c | 26 ++++++++++++++
drivers/gpu/drm/i915/intel_dpll_mgr.c | 66 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 ++
4 files changed, 97 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7f27fe2e38c7..26903cffabf6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9182,13 +9182,16 @@ enum skl_power_gate {
#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
+#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
+#define DPLL_CFGCR1_KDIV_SHIFT (6)
#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
#define DPLL_CFGCR1_KDIV_1 (1 << 6)
#define DPLL_CFGCR1_KDIV_2 (2 << 6)
#define DPLL_CFGCR1_KDIV_4 (4 << 6)
#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
+#define DPLL_CFGCR1_PDIV_SHIFT (2)
#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
#define DPLL_CFGCR1_PDIV_2 (1 << 2)
#define DPLL_CFGCR1_PDIV_3 (2 << 2)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index d8ae82001f83..0d8bed8e2200 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1458,6 +1458,30 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
}
+static void icl_ddi_clock_get(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ int link_clock = 0;
+ uint32_t pll_id;
+
+ pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
+ if (port == PORT_A || port == PORT_B) {
+ if (encoder->type == INTEL_OUTPUT_HDMI)
+ link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
+ else
+ link_clock = icl_calc_dp_combo_pll_link(dev_priv,
+ pll_id);
+ } else {
+ /* FIXME - Add for MG PLL */
+ WARN(1, "MG PLL clock_get code not implemented yet\n");
+ }
+
+ pipe_config->port_clock = link_clock;
+ ddi_dotclock_get(pipe_config);
+}
+
static void cnl_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -1651,6 +1675,8 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
bxt_ddi_clock_get(encoder, pipe_config);
else if (IS_CANNONLAKE(dev_priv))
cnl_ddi_clock_get(encoder, pipe_config);
+ else if (IS_ICELAKE(dev_priv))
+ icl_ddi_clock_get(encoder, pipe_config);
}
void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 383fbc15113d..3cc837f74ffb 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2525,6 +2525,72 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
return true;
}
+int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
+ uint32_t pll_id)
+{
+ uint32_t cfgcr0, cfgcr1;
+ uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;
+ const struct skl_wrpll_params *params;
+ int index, n_entries, link_clock = 0;
+
+ /* Read back values from DPLL CFGCR registers */
+ cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
+ cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
+
+ dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;
+ dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
+ DPLL_CFGCR0_DCO_FRACTION_SHIFT;
+ pdiv = (cfgcr1 & DPLL_CFGCR1_PDIV_MASK) >> DPLL_CFGCR1_PDIV_SHIFT;
+ kdiv = (cfgcr1 & DPLL_CFGCR1_KDIV_MASK) >> DPLL_CFGCR1_KDIV_SHIFT;
+ qdiv_mode = (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) >>
+ DPLL_CFGCR1_QDIV_MODE_SHIFT;
+ qdiv_ratio = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
+ DPLL_CFGCR1_QDIV_RATIO_SHIFT;
+
+ params = dev_priv->cdclk.hw.ref == 24000 ?
+ icl_dp_combo_pll_24MHz_values :
+ icl_dp_combo_pll_19_2MHz_values;
+ n_entries = ARRAY_SIZE(icl_dp_combo_pll_24MHz_values);
+
+ for (index = 0; index < n_entries; index++) {
+ if (dco_integer == params[index].dco_integer &&
+ dco_fraction == params[index].dco_fraction &&
+ pdiv == params[index].pdiv &&
+ kdiv == params[index].kdiv &&
+ qdiv_mode == params[index].qdiv_mode &&
+ qdiv_ratio == params[index].qdiv_ratio)
+ break;
+ }
+ WARN(index == n_entries, "Invalid PLL Parameters");
+
+ /* Map PLL Index to Link Clock */
+ switch (index) {
+ case 0:
+ link_clock = 540000;
+ break;
+ case 1:
+ link_clock = 270000;
+ break;
+ case 2:
+ link_clock = 162000;
+ break;
+ case 3:
+ link_clock = 324000;
+ break;
+ case 4:
+ link_clock = 432000;
+ break;
+ case 5:
+ link_clock = 432000;
+ break;
+ case 6:
+ link_clock = 810000;
+ break;
+ }
+
+ return link_clock;
+}
+
static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)
{
return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index 7a0cd564a9ee..78915057d2e6 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -336,5 +336,7 @@ void intel_shared_dpll_init(struct drm_device *dev);
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state);
+int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
+ uint32_t pll_id);
#endif /* _INTEL_DPLL_MGR_H_ */
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs.
2018-05-22 0:25 ` [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs Paulo Zanoni
@ 2018-05-22 11:44 ` Mika Kahola
2018-05-23 5:48 ` Lucas De Marchi
2018-05-23 21:54 ` Paulo Zanoni
2018-05-23 21:15 ` Paulo Zanoni
2018-05-23 22:44 ` [PATCH v2 " Paulo Zanoni
2 siblings, 2 replies; 127+ messages in thread
From: Mika Kahola @ 2018-05-22 11:44 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
On Mon, 2018-05-21 at 17:25 -0700, Paulo Zanoni wrote:
> From: Manasi Navare <manasi.d.navare@intel.com>
>
> PLLs are the source clocks for the DDIs so in order
> to determine the ddi clock we need to check the PLL
> configuration.
>
> This gets a little tricky for ICL since there is
> no register bit that maps directly to the link clock.
> So this patch creates a separate function in intel_dpll_mgr.c
> to obtain the write array PLL Params and compares the set
> pll_params with the table to get the corresponding link
> clock.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 ++
> drivers/gpu/drm/i915/intel_ddi.c | 26 ++++++++++++++
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 66
> +++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 ++
> 4 files changed, 97 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 7f27fe2e38c7..26903cffabf6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9182,13 +9182,16 @@ enum skl_power_gate {
> #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
> #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
> #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
> +#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
> #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
> #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
> +#define DPLL_CFGCR1_KDIV_SHIFT (6)
> #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
> #define DPLL_CFGCR1_KDIV_1 (1 << 6)
> #define DPLL_CFGCR1_KDIV_2 (2 << 6)
> #define DPLL_CFGCR1_KDIV_4 (4 << 6)
> #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
> +#define DPLL_CFGCR1_PDIV_SHIFT (2)
> #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
> #define DPLL_CFGCR1_PDIV_2 (1 << 2)
> #define DPLL_CFGCR1_PDIV_3 (2 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index d8ae82001f83..0d8bed8e2200 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1458,6 +1458,30 @@ static void ddi_dotclock_get(struct
> intel_crtc_state *pipe_config)
> pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> }
>
> +static void icl_ddi_clock_get(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> + enum port port = encoder->port;
> + int link_clock = 0;
> + uint32_t pll_id;
> +
> + pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> >shared_dpll);
> + if (port == PORT_A || port == PORT_B) {
> + if (encoder->type == INTEL_OUTPUT_HDMI)
> + link_clock = cnl_calc_wrpll_link(dev_priv,
> pll_id);
> + else
> + link_clock =
> icl_calc_dp_combo_pll_link(dev_priv,
> + pll_
> id);
> + } else {
> + /* FIXME - Add for MG PLL */
> + WARN(1, "MG PLL clock_get code not implemented
> yet\n");
> + }
> +
> + pipe_config->port_clock = link_clock;
> + ddi_dotclock_get(pipe_config);
> +}
> +
> static void cnl_ddi_clock_get(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> @@ -1651,6 +1675,8 @@ static void intel_ddi_clock_get(struct
> intel_encoder *encoder,
> bxt_ddi_clock_get(encoder, pipe_config);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_ddi_clock_get(encoder, pipe_config);
> + else if (IS_ICELAKE(dev_priv))
> + icl_ddi_clock_get(encoder, pipe_config);
> }
>
> void intel_ddi_set_pipe_settings(const struct intel_crtc_state
> *crtc_state)
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 383fbc15113d..3cc837f74ffb 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2525,6 +2525,72 @@ static bool icl_calc_dpll_state(struct
> intel_crtc_state *crtc_state,
> return true;
> }
>
> +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> + uint32_t pll_id)
> +{
> + uint32_t cfgcr0, cfgcr1;
> + uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer,
> dco_fraction;
> + const struct skl_wrpll_params *params;
> + int index, n_entries, link_clock = 0;
> +
> + /* Read back values from DPLL CFGCR registers */
> + cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> + cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> +
> + dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;
> + dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> + DPLL_CFGCR0_DCO_FRACTION_SHIFT;
> + pdiv = (cfgcr1 & DPLL_CFGCR1_PDIV_MASK) >>
> DPLL_CFGCR1_PDIV_SHIFT;
> + kdiv = (cfgcr1 & DPLL_CFGCR1_KDIV_MASK) >>
> DPLL_CFGCR1_KDIV_SHIFT;
> + qdiv_mode = (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) >>
> + DPLL_CFGCR1_QDIV_MODE_SHIFT;
> + qdiv_ratio = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
> + DPLL_CFGCR1_QDIV_RATIO_SHIFT;
> +
> + params = dev_priv->cdclk.hw.ref == 24000 ?
> + icl_dp_combo_pll_24MHz_values :
> + icl_dp_combo_pll_19_2MHz_values;
> + n_entries = ARRAY_SIZE(icl_dp_combo_pll_24MHz_values);
> +
> + for (index = 0; index < n_entries; index++) {
> + if (dco_integer == params[index].dco_integer &&
> + dco_fraction == params[index].dco_fraction &&
> + pdiv == params[index].pdiv &&
> + kdiv == params[index].kdiv &&
> + qdiv_mode == params[index].qdiv_mode &&
> + qdiv_ratio == params[index].qdiv_ratio)
> + break;
> + }
> + WARN(index == n_entries, "Invalid PLL Parameters");
> +
> + /* Map PLL Index to Link Clock */
> + switch (index) {
> + case 0:
> + link_clock = 540000;
> + break;
> + case 1:
> + link_clock = 270000;
> + break;
> + case 2:
> + link_clock = 162000;
> + break;
> + case 3:
> + link_clock = 324000;
> + break;
> + case 4:
> + link_clock = 432000;
> + break;
> + case 5:
> + link_clock = 432000;
> + break;
> + case 6:
> + link_clock = 810000;
> + break;
Just to play it safe, we could add
default:
MISSING_CASE();
}
here and return with some default link clock value.
> +
> + return link_clock;
> +}
> +
> static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)
> {
> return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index 7a0cd564a9ee..78915057d2e6 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -336,5 +336,7 @@ void intel_shared_dpll_init(struct drm_device
> *dev);
>
> void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> struct intel_dpll_hw_state *hw_state);
> +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> + uint32_t pll_id);
>
> #endif /* _INTEL_DPLL_MGR_H_ */
--
Mika Kahola - Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs.
2018-05-22 11:44 ` Mika Kahola
@ 2018-05-23 5:48 ` Lucas De Marchi
2018-05-23 21:54 ` Paulo Zanoni
1 sibling, 0 replies; 127+ messages in thread
From: Lucas De Marchi @ 2018-05-23 5:48 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx, Paulo Zanoni, Rodrigo Vivi
On Tue, May 22, 2018 at 02:44:43PM +0300, Mika Kahola wrote:
> On Mon, 2018-05-21 at 17:25 -0700, Paulo Zanoni wrote:
> > From: Manasi Navare <manasi.d.navare@intel.com>
> >
> > PLLs are the source clocks for the DDIs so in order
> > to determine the ddi clock we need to check the PLL
> > configuration.
> >
> > This gets a little tricky for ICL since there is
> > no register bit that maps directly to the link clock.
> > So this patch creates a separate function in intel_dpll_mgr.c
> > to obtain the write array PLL Params and compares the set
> > pll_params with the table to get the corresponding link
> > clock.
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 3 ++
> > drivers/gpu/drm/i915/intel_ddi.c | 26 ++++++++++++++
> > drivers/gpu/drm/i915/intel_dpll_mgr.c | 66
> > +++++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 ++
> > 4 files changed, 97 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 7f27fe2e38c7..26903cffabf6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9182,13 +9182,16 @@ enum skl_power_gate {
> > #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
> > #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
> > #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
> > +#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
> > #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
> > #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
> > +#define DPLL_CFGCR1_KDIV_SHIFT (6)
> > #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
> > #define DPLL_CFGCR1_KDIV_1 (1 << 6)
> > #define DPLL_CFGCR1_KDIV_2 (2 << 6)
> > #define DPLL_CFGCR1_KDIV_4 (4 << 6)
> > #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
> > +#define DPLL_CFGCR1_PDIV_SHIFT (2)
> > #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
> > #define DPLL_CFGCR1_PDIV_2 (1 << 2)
> > #define DPLL_CFGCR1_PDIV_3 (2 << 2)
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index d8ae82001f83..0d8bed8e2200 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1458,6 +1458,30 @@ static void ddi_dotclock_get(struct
> > intel_crtc_state *pipe_config)
> > pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> > }
> >
> > +static void icl_ddi_clock_get(struct intel_encoder *encoder,
> > + struct intel_crtc_state *pipe_config)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(encoder-
> > >base.dev);
> > + enum port port = encoder->port;
> > + int link_clock = 0;
> > + uint32_t pll_id;
> > +
> > + pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> > >shared_dpll);
> > + if (port == PORT_A || port == PORT_B) {
> > + if (encoder->type == INTEL_OUTPUT_HDMI)
> > + link_clock = cnl_calc_wrpll_link(dev_priv,
> > pll_id);
> > + else
> > + link_clock =
> > icl_calc_dp_combo_pll_link(dev_priv,
> > + pll_
> > id);
> > + } else {
> > + /* FIXME - Add for MG PLL */
> > + WARN(1, "MG PLL clock_get code not implemented
> > yet\n");
> > + }
> > +
> > + pipe_config->port_clock = link_clock;
> > + ddi_dotclock_get(pipe_config);
> > +}
> > +
> > static void cnl_ddi_clock_get(struct intel_encoder *encoder,
> > struct intel_crtc_state *pipe_config)
> > {
> > @@ -1651,6 +1675,8 @@ static void intel_ddi_clock_get(struct
> > intel_encoder *encoder,
> > bxt_ddi_clock_get(encoder, pipe_config);
> > else if (IS_CANNONLAKE(dev_priv))
> > cnl_ddi_clock_get(encoder, pipe_config);
> > + else if (IS_ICELAKE(dev_priv))
> > + icl_ddi_clock_get(encoder, pipe_config);
> > }
> >
> > void intel_ddi_set_pipe_settings(const struct intel_crtc_state
> > *crtc_state)
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index 383fbc15113d..3cc837f74ffb 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -2525,6 +2525,72 @@ static bool icl_calc_dpll_state(struct
> > intel_crtc_state *crtc_state,
> > return true;
> > }
> >
> > +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> > + uint32_t pll_id)
> > +{
> > + uint32_t cfgcr0, cfgcr1;
> > + uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer,
> > dco_fraction;
> > + const struct skl_wrpll_params *params;
> > + int index, n_entries, link_clock = 0;
> > +
> > + /* Read back values from DPLL CFGCR registers */
> > + cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> > + cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> > +
> > + dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;
> > + dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> > + DPLL_CFGCR0_DCO_FRACTION_SHIFT;
> > + pdiv = (cfgcr1 & DPLL_CFGCR1_PDIV_MASK) >>
> > DPLL_CFGCR1_PDIV_SHIFT;
> > + kdiv = (cfgcr1 & DPLL_CFGCR1_KDIV_MASK) >>
> > DPLL_CFGCR1_KDIV_SHIFT;
> > + qdiv_mode = (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) >>
> > + DPLL_CFGCR1_QDIV_MODE_SHIFT;
> > + qdiv_ratio = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
> > + DPLL_CFGCR1_QDIV_RATIO_SHIFT;
> > +
> > + params = dev_priv->cdclk.hw.ref == 24000 ?
> > + icl_dp_combo_pll_24MHz_values :
> > + icl_dp_combo_pll_19_2MHz_values;
> > + n_entries = ARRAY_SIZE(icl_dp_combo_pll_24MHz_values);
> > +
> > + for (index = 0; index < n_entries; index++) {
> > + if (dco_integer == params[index].dco_integer &&
> > + dco_fraction == params[index].dco_fraction &&
> > + pdiv == params[index].pdiv &&
> > + kdiv == params[index].kdiv &&
> > + qdiv_mode == params[index].qdiv_mode &&
> > + qdiv_ratio == params[index].qdiv_ratio)
> > + break;
> > + }
> > + WARN(index == n_entries, "Invalid PLL Parameters");
> > +
> > + /* Map PLL Index to Link Clock */
> > + switch (index) {
> > + case 0:
> > + link_clock = 540000;
> > + break;
> > + case 1:
> > + link_clock = 270000;
> > + break;
> > + case 2:
> > + link_clock = 162000;
> > + break;
> > + case 3:
> > + link_clock = 324000;
> > + break;
> > + case 4:
> > + link_clock = 432000;
> > + break;
> > + case 5:
> > + link_clock = 432000;
> > + break;
> > + case 6:
> > + link_clock = 810000;
> > + break;
> Just to play it safe, we could add
>
> default:
> MISSING_CASE();
> }
>
> here and return with some default link clock value.
There will already be a warning above when index == n_entries. And then
we will return 0.
>
> > +
> > + return link_clock;
> > +}
> > +
> > static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)
> > {
> > return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > index 7a0cd564a9ee..78915057d2e6 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > @@ -336,5 +336,7 @@ void intel_shared_dpll_init(struct drm_device
> > *dev);
> >
> > void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> > struct intel_dpll_hw_state *hw_state);
> > +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> > + uint32_t pll_id);
> >
> > #endif /* _INTEL_DPLL_MGR_H_ */
> --
> Mika Kahola - Intel OTC
>
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^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs.
2018-05-22 11:44 ` Mika Kahola
2018-05-23 5:48 ` Lucas De Marchi
@ 2018-05-23 21:54 ` Paulo Zanoni
1 sibling, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-23 21:54 UTC (permalink / raw)
To: mika.kahola, intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
Em Ter, 2018-05-22 às 14:44 +0300, Mika Kahola escreveu:
> On Mon, 2018-05-21 at 17:25 -0700, Paulo Zanoni wrote:
> > From: Manasi Navare <manasi.d.navare@intel.com>
> >
> > PLLs are the source clocks for the DDIs so in order
> > to determine the ddi clock we need to check the PLL
> > configuration.
> >
> > This gets a little tricky for ICL since there is
> > no register bit that maps directly to the link clock.
> > So this patch creates a separate function in intel_dpll_mgr.c
> > to obtain the write array PLL Params and compares the set
> > pll_params with the table to get the corresponding link
> > clock.
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 3 ++
> > drivers/gpu/drm/i915/intel_ddi.c | 26 ++++++++++++++
> > drivers/gpu/drm/i915/intel_dpll_mgr.c | 66
> > +++++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 ++
> > 4 files changed, 97 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 7f27fe2e38c7..26903cffabf6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9182,13 +9182,16 @@ enum skl_power_gate {
> > #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
> > #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
> > #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
> > +#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
> > #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
> > #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
> > +#define DPLL_CFGCR1_KDIV_SHIFT (6)
> > #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
> > #define DPLL_CFGCR1_KDIV_1 (1 << 6)
> > #define DPLL_CFGCR1_KDIV_2 (2 << 6)
> > #define DPLL_CFGCR1_KDIV_4 (4 << 6)
> > #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
> > +#define DPLL_CFGCR1_PDIV_SHIFT (2)
> > #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
> > #define DPLL_CFGCR1_PDIV_2 (1 << 2)
> > #define DPLL_CFGCR1_PDIV_3 (2 << 2)
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index d8ae82001f83..0d8bed8e2200 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1458,6 +1458,30 @@ static void ddi_dotclock_get(struct
> > intel_crtc_state *pipe_config)
> > pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> > }
> >
> > +static void icl_ddi_clock_get(struct intel_encoder *encoder,
> > + struct intel_crtc_state
> > *pipe_config)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(encoder-
> > > base.dev);
> >
> > + enum port port = encoder->port;
> > + int link_clock = 0;
> > + uint32_t pll_id;
> > +
> > + pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> > > shared_dpll);
> >
> > + if (port == PORT_A || port == PORT_B) {
> > + if (encoder->type == INTEL_OUTPUT_HDMI)
> > + link_clock = cnl_calc_wrpll_link(dev_priv,
> > pll_id);
> > + else
> > + link_clock =
> > icl_calc_dp_combo_pll_link(dev_priv,
> > + pl
> > l_
> > id);
> > + } else {
> > + /* FIXME - Add for MG PLL */
> > + WARN(1, "MG PLL clock_get code not implemented
> > yet\n");
> > + }
> > +
> > + pipe_config->port_clock = link_clock;
> > + ddi_dotclock_get(pipe_config);
> > +}
> > +
> > static void cnl_ddi_clock_get(struct intel_encoder *encoder,
> > struct intel_crtc_state
> > *pipe_config)
> > {
> > @@ -1651,6 +1675,8 @@ static void intel_ddi_clock_get(struct
> > intel_encoder *encoder,
> > bxt_ddi_clock_get(encoder, pipe_config);
> > else if (IS_CANNONLAKE(dev_priv))
> > cnl_ddi_clock_get(encoder, pipe_config);
> > + else if (IS_ICELAKE(dev_priv))
> > + icl_ddi_clock_get(encoder, pipe_config);
> > }
> >
> > void intel_ddi_set_pipe_settings(const struct intel_crtc_state
> > *crtc_state)
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index 383fbc15113d..3cc837f74ffb 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -2525,6 +2525,72 @@ static bool icl_calc_dpll_state(struct
> > intel_crtc_state *crtc_state,
> > return true;
> > }
> >
> > +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> > + uint32_t pll_id)
> > +{
> > + uint32_t cfgcr0, cfgcr1;
> > + uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer,
> > dco_fraction;
> > + const struct skl_wrpll_params *params;
> > + int index, n_entries, link_clock = 0;
> > +
> > + /* Read back values from DPLL CFGCR registers */
> > + cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> > + cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> > +
> > + dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;
> > + dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> > + DPLL_CFGCR0_DCO_FRACTION_SHIFT;
> > + pdiv = (cfgcr1 & DPLL_CFGCR1_PDIV_MASK) >>
> > DPLL_CFGCR1_PDIV_SHIFT;
> > + kdiv = (cfgcr1 & DPLL_CFGCR1_KDIV_MASK) >>
> > DPLL_CFGCR1_KDIV_SHIFT;
> > + qdiv_mode = (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) >>
> > + DPLL_CFGCR1_QDIV_MODE_SHIFT;
> > + qdiv_ratio = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
> > + DPLL_CFGCR1_QDIV_RATIO_SHIFT;
> > +
> > + params = dev_priv->cdclk.hw.ref == 24000 ?
> > + icl_dp_combo_pll_24MHz_values :
> > + icl_dp_combo_pll_19_2MHz_values;
> > + n_entries = ARRAY_SIZE(icl_dp_combo_pll_24MHz_values);
> > +
> > + for (index = 0; index < n_entries; index++) {
> > + if (dco_integer == params[index].dco_integer &&
> > + dco_fraction == params[index].dco_fraction &&
> > + pdiv == params[index].pdiv &&
> > + kdiv == params[index].kdiv &&
> > + qdiv_mode == params[index].qdiv_mode &&
> > + qdiv_ratio == params[index].qdiv_ratio)
> > + break;
> > + }
> > + WARN(index == n_entries, "Invalid PLL Parameters");
> > +
> > + /* Map PLL Index to Link Clock */
> > + switch (index) {
> > + case 0:
> > + link_clock = 540000;
> > + break;
> > + case 1:
> > + link_clock = 270000;
> > + break;
> > + case 2:
> > + link_clock = 162000;
> > + break;
> > + case 3:
> > + link_clock = 324000;
> > + break;
> > + case 4:
> > + link_clock = 432000;
> > + break;
> > + case 5:
> > + link_clock = 432000;
> > + break;
> > + case 6:
> > + link_clock = 810000;
> > + break;
>
> Just to play it safe, we could add
>
> default:
> MISSING_CASE();
> }
>
> here and return with some default link clock value.
In this case the WARN above should be triggered and we'll return 0 (due
to link_clock being initialized to 0 at definition), but I would
prefer if our code was a little more explicit like you're suggesting,
especially removing the zero initialization, which only serves to hide
details like that.
Also, the table is wrong: it has 432 twice and is missing 216 and 648.
>
> > +
> > + return link_clock;
> > +}
> > +
> > static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)
> > {
> > return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > index 7a0cd564a9ee..78915057d2e6 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > @@ -336,5 +336,7 @@ void intel_shared_dpll_init(struct drm_device
> > *dev);
> >
> > void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> > struct intel_dpll_hw_state
> > *hw_state);
> > +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> > + uint32_t pll_id);
> >
> > #endif /* _INTEL_DPLL_MGR_H_ */
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^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs.
2018-05-22 0:25 ` [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs Paulo Zanoni
2018-05-22 11:44 ` Mika Kahola
@ 2018-05-23 21:15 ` Paulo Zanoni
2018-05-23 22:44 ` [PATCH v2 " Paulo Zanoni
2 siblings, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-23 21:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Dhinakaran Pandiyan, Rodrigo Vivi
Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> From: Manasi Navare <manasi.d.navare@intel.com>
>
> PLLs are the source clocks for the DDIs so in order
> to determine the ddi clock we need to check the PLL
> configuration.
>
> This gets a little tricky for ICL since there is
> no register bit that maps directly to the link clock.
> So this patch creates a separate function in intel_dpll_mgr.c
> to obtain the write array PLL Params and compares the set
> pll_params with the table to get the corresponding link
> clock.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 ++
> drivers/gpu/drm/i915/intel_ddi.c | 26 ++++++++++++++
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 66
> +++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 ++
> 4 files changed, 97 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 7f27fe2e38c7..26903cffabf6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9182,13 +9182,16 @@ enum skl_power_gate {
> #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
> #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
> #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
> +#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
> #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
> #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
> +#define DPLL_CFGCR1_KDIV_SHIFT (6)
> #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
> #define DPLL_CFGCR1_KDIV_1 (1 << 6)
> #define DPLL_CFGCR1_KDIV_2 (2 << 6)
> #define DPLL_CFGCR1_KDIV_4 (4 << 6)
> #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
> +#define DPLL_CFGCR1_PDIV_SHIFT (2)
> #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
> #define DPLL_CFGCR1_PDIV_2 (1 << 2)
> #define DPLL_CFGCR1_PDIV_3 (2 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index d8ae82001f83..0d8bed8e2200 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1458,6 +1458,30 @@ static void ddi_dotclock_get(struct
> intel_crtc_state *pipe_config)
> pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> }
>
> +static void icl_ddi_clock_get(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> + enum port port = encoder->port;
> + int link_clock = 0;
> + uint32_t pll_id;
> +
> + pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> >shared_dpll);
> + if (port == PORT_A || port == PORT_B) {
> + if (encoder->type == INTEL_OUTPUT_HDMI)
I just found that some time ago DK had spotted this check is wrong and
intel_crtc_has_type() should be used here. New version will be sent.
> + link_clock = cnl_calc_wrpll_link(dev_priv,
> pll_id);
> + else
> + link_clock =
> icl_calc_dp_combo_pll_link(dev_priv,
> + pll_
> id);
> + } else {
> + /* FIXME - Add for MG PLL */
> + WARN(1, "MG PLL clock_get code not implemented
> yet\n");
> + }
> +
> + pipe_config->port_clock = link_clock;
> + ddi_dotclock_get(pipe_config);
> +}
> +
> static void cnl_ddi_clock_get(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> @@ -1651,6 +1675,8 @@ static void intel_ddi_clock_get(struct
> intel_encoder *encoder,
> bxt_ddi_clock_get(encoder, pipe_config);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_ddi_clock_get(encoder, pipe_config);
> + else if (IS_ICELAKE(dev_priv))
> + icl_ddi_clock_get(encoder, pipe_config);
> }
>
> void intel_ddi_set_pipe_settings(const struct intel_crtc_state
> *crtc_state)
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 383fbc15113d..3cc837f74ffb 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2525,6 +2525,72 @@ static bool icl_calc_dpll_state(struct
> intel_crtc_state *crtc_state,
> return true;
> }
>
> +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> + uint32_t pll_id)
> +{
> + uint32_t cfgcr0, cfgcr1;
> + uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer,
> dco_fraction;
> + const struct skl_wrpll_params *params;
> + int index, n_entries, link_clock = 0;
> +
> + /* Read back values from DPLL CFGCR registers */
> + cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> + cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> +
> + dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;
> + dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> + DPLL_CFGCR0_DCO_FRACTION_SHIFT;
> + pdiv = (cfgcr1 & DPLL_CFGCR1_PDIV_MASK) >>
> DPLL_CFGCR1_PDIV_SHIFT;
> + kdiv = (cfgcr1 & DPLL_CFGCR1_KDIV_MASK) >>
> DPLL_CFGCR1_KDIV_SHIFT;
> + qdiv_mode = (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) >>
> + DPLL_CFGCR1_QDIV_MODE_SHIFT;
> + qdiv_ratio = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
> + DPLL_CFGCR1_QDIV_RATIO_SHIFT;
> +
> + params = dev_priv->cdclk.hw.ref == 24000 ?
> + icl_dp_combo_pll_24MHz_values :
> + icl_dp_combo_pll_19_2MHz_values;
> + n_entries = ARRAY_SIZE(icl_dp_combo_pll_24MHz_values);
> +
> + for (index = 0; index < n_entries; index++) {
> + if (dco_integer == params[index].dco_integer &&
> + dco_fraction == params[index].dco_fraction &&
> + pdiv == params[index].pdiv &&
> + kdiv == params[index].kdiv &&
> + qdiv_mode == params[index].qdiv_mode &&
> + qdiv_ratio == params[index].qdiv_ratio)
> + break;
> + }
> + WARN(index == n_entries, "Invalid PLL Parameters");
> +
> + /* Map PLL Index to Link Clock */
> + switch (index) {
> + case 0:
> + link_clock = 540000;
> + break;
> + case 1:
> + link_clock = 270000;
> + break;
> + case 2:
> + link_clock = 162000;
> + break;
> + case 3:
> + link_clock = 324000;
> + break;
> + case 4:
> + link_clock = 432000;
> + break;
> + case 5:
> + link_clock = 432000;
> + break;
> + case 6:
> + link_clock = 810000;
> + break;
> + }
> +
> + return link_clock;
> +}
> +
> static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)
> {
> return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index 7a0cd564a9ee..78915057d2e6 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -336,5 +336,7 @@ void intel_shared_dpll_init(struct drm_device
> *dev);
>
> void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> struct intel_dpll_hw_state *hw_state);
> +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> + uint32_t pll_id);
>
> #endif /* _INTEL_DPLL_MGR_H_ */
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^ permalink raw reply [flat|nested] 127+ messages in thread* [PATCH v2 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs.
2018-05-22 0:25 ` [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs Paulo Zanoni
2018-05-22 11:44 ` Mika Kahola
2018-05-23 21:15 ` Paulo Zanoni
@ 2018-05-23 22:44 ` Paulo Zanoni
2018-05-24 13:12 ` Mika Kahola
2 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-23 22:44 UTC (permalink / raw)
To: intel-gfx
Cc: Paulo Zanoni, Lucas De Marchi, Dhinakaran Pandiyan, Rodrigo Vivi
From: Manasi Navare <manasi.d.navare@intel.com>
PLLs are the source clocks for the DDIs so in order
to determine the ddi clock we need to check the PLL
configuration.
This gets a little tricky for ICL since there is
no register bit that maps directly to the link clock.
So this patch creates a separate function in intel_dpll_mgr.c
to obtain the write array PLL Params and compares the set
pll_params with the table to get the corresponding link
clock.
v2:
- Fix the encoder type check (DK).
- Improve our error checking, return a sane value (Mika, Paulo).
- Fix table entries (Paulo).
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
[Paulo: implement v2]
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gpu/drm/i915/intel_ddi.c | 26 +++++++++++++
drivers/gpu/drm/i915/intel_dpll_mgr.c | 70 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +
4 files changed, 101 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index de6fcdb4948f..7c6346542a52 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9174,13 +9174,16 @@ enum skl_power_gate {
#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
+#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
+#define DPLL_CFGCR1_KDIV_SHIFT (6)
#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
#define DPLL_CFGCR1_KDIV_1 (1 << 6)
#define DPLL_CFGCR1_KDIV_2 (2 << 6)
#define DPLL_CFGCR1_KDIV_4 (4 << 6)
#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
+#define DPLL_CFGCR1_PDIV_SHIFT (2)
#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
#define DPLL_CFGCR1_PDIV_2 (1 << 2)
#define DPLL_CFGCR1_PDIV_3 (2 << 2)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f6b2c0ec4e97..0e0b726e3a49 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1429,6 +1429,30 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
}
+static void icl_ddi_clock_get(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ int link_clock = 0;
+ uint32_t pll_id;
+
+ pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
+ if (port == PORT_A || port == PORT_B) {
+ if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
+ link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
+ else
+ link_clock = icl_calc_dp_combo_pll_link(dev_priv,
+ pll_id);
+ } else {
+ /* FIXME - Add for MG PLL */
+ WARN(1, "MG PLL clock_get code not implemented yet\n");
+ }
+
+ pipe_config->port_clock = link_clock;
+ ddi_dotclock_get(pipe_config);
+}
+
static void cnl_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -1622,6 +1646,8 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
bxt_ddi_clock_get(encoder, pipe_config);
else if (IS_CANNONLAKE(dev_priv))
cnl_ddi_clock_get(encoder, pipe_config);
+ else if (IS_ICELAKE(dev_priv))
+ icl_ddi_clock_get(encoder, pipe_config);
}
void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 383fbc15113d..07bdbf2582ba 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2525,6 +2525,76 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
return true;
}
+int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
+ uint32_t pll_id)
+{
+ uint32_t cfgcr0, cfgcr1;
+ uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;
+ const struct skl_wrpll_params *params;
+ int index, n_entries, link_clock;
+
+ /* Read back values from DPLL CFGCR registers */
+ cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
+ cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
+
+ dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;
+ dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
+ DPLL_CFGCR0_DCO_FRACTION_SHIFT;
+ pdiv = (cfgcr1 & DPLL_CFGCR1_PDIV_MASK) >> DPLL_CFGCR1_PDIV_SHIFT;
+ kdiv = (cfgcr1 & DPLL_CFGCR1_KDIV_MASK) >> DPLL_CFGCR1_KDIV_SHIFT;
+ qdiv_mode = (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) >>
+ DPLL_CFGCR1_QDIV_MODE_SHIFT;
+ qdiv_ratio = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
+ DPLL_CFGCR1_QDIV_RATIO_SHIFT;
+
+ params = dev_priv->cdclk.hw.ref == 24000 ?
+ icl_dp_combo_pll_24MHz_values :
+ icl_dp_combo_pll_19_2MHz_values;
+ n_entries = ARRAY_SIZE(icl_dp_combo_pll_24MHz_values);
+
+ for (index = 0; index < n_entries; index++) {
+ if (dco_integer == params[index].dco_integer &&
+ dco_fraction == params[index].dco_fraction &&
+ pdiv == params[index].pdiv &&
+ kdiv == params[index].kdiv &&
+ qdiv_mode == params[index].qdiv_mode &&
+ qdiv_ratio == params[index].qdiv_ratio)
+ break;
+ }
+
+ /* Map PLL Index to Link Clock */
+ switch (index) {
+ default:
+ MISSING_CASE(index);
+ case 0:
+ link_clock = 540000;
+ break;
+ case 1:
+ link_clock = 270000;
+ break;
+ case 2:
+ link_clock = 162000;
+ break;
+ case 3:
+ link_clock = 324000;
+ break;
+ case 4:
+ link_clock = 216000;
+ break;
+ case 5:
+ link_clock = 432000;
+ break;
+ case 6:
+ link_clock = 648000;
+ break;
+ case 7:
+ link_clock = 810000;
+ break;
+ }
+
+ return link_clock;
+}
+
static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)
{
return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index 7a0cd564a9ee..78915057d2e6 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -336,5 +336,7 @@ void intel_shared_dpll_init(struct drm_device *dev);
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state);
+int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
+ uint32_t pll_id);
#endif /* _INTEL_DPLL_MGR_H_ */
--
2.14.3
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^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH v2 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs.
2018-05-23 22:44 ` [PATCH v2 " Paulo Zanoni
@ 2018-05-24 13:12 ` Mika Kahola
0 siblings, 0 replies; 127+ messages in thread
From: Mika Kahola @ 2018-05-24 13:12 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx
Cc: Lucas De Marchi, Dhinakaran Pandiyan, Rodrigo Vivi
Patch look ok to me.
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
On Wed, 2018-05-23 at 15:44 -0700, Paulo Zanoni wrote:
> From: Manasi Navare <manasi.d.navare@intel.com>
>
> PLLs are the source clocks for the DDIs so in order
> to determine the ddi clock we need to check the PLL
> configuration.
>
> This gets a little tricky for ICL since there is
> no register bit that maps directly to the link clock.
> So this patch creates a separate function in intel_dpll_mgr.c
> to obtain the write array PLL Params and compares the set
> pll_params with the table to get the corresponding link
> clock.
>
> v2:
> - Fix the encoder type check (DK).
> - Improve our error checking, return a sane value (Mika, Paulo).
> - Fix table entries (Paulo).
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> [Paulo: implement v2]
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 ++
> drivers/gpu/drm/i915/intel_ddi.c | 26 +++++++++++++
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 70
> +++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +
> 4 files changed, 101 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index de6fcdb4948f..7c6346542a52 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9174,13 +9174,16 @@ enum skl_power_gate {
> #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
> #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
> #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
> +#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
> #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
> #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
> +#define DPLL_CFGCR1_KDIV_SHIFT (6)
> #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
> #define DPLL_CFGCR1_KDIV_1 (1 << 6)
> #define DPLL_CFGCR1_KDIV_2 (2 << 6)
> #define DPLL_CFGCR1_KDIV_4 (4 << 6)
> #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
> +#define DPLL_CFGCR1_PDIV_SHIFT (2)
> #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
> #define DPLL_CFGCR1_PDIV_2 (1 << 2)
> #define DPLL_CFGCR1_PDIV_3 (2 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index f6b2c0ec4e97..0e0b726e3a49 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1429,6 +1429,30 @@ static void ddi_dotclock_get(struct
> intel_crtc_state *pipe_config)
> pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> }
>
> +static void icl_ddi_clock_get(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> + enum port port = encoder->port;
> + int link_clock = 0;
> + uint32_t pll_id;
> +
> + pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> >shared_dpll);
> + if (port == PORT_A || port == PORT_B) {
> + if (intel_crtc_has_type(pipe_config,
> INTEL_OUTPUT_HDMI))
> + link_clock = cnl_calc_wrpll_link(dev_priv,
> pll_id);
> + else
> + link_clock =
> icl_calc_dp_combo_pll_link(dev_priv,
> + pll_
> id);
> + } else {
> + /* FIXME - Add for MG PLL */
> + WARN(1, "MG PLL clock_get code not implemented
> yet\n");
> + }
> +
> + pipe_config->port_clock = link_clock;
> + ddi_dotclock_get(pipe_config);
> +}
> +
> static void cnl_ddi_clock_get(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> @@ -1622,6 +1646,8 @@ static void intel_ddi_clock_get(struct
> intel_encoder *encoder,
> bxt_ddi_clock_get(encoder, pipe_config);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_ddi_clock_get(encoder, pipe_config);
> + else if (IS_ICELAKE(dev_priv))
> + icl_ddi_clock_get(encoder, pipe_config);
> }
>
> void intel_ddi_set_pipe_settings(const struct intel_crtc_state
> *crtc_state)
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 383fbc15113d..07bdbf2582ba 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2525,6 +2525,76 @@ static bool icl_calc_dpll_state(struct
> intel_crtc_state *crtc_state,
> return true;
> }
>
> +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> + uint32_t pll_id)
> +{
> + uint32_t cfgcr0, cfgcr1;
> + uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer,
> dco_fraction;
> + const struct skl_wrpll_params *params;
> + int index, n_entries, link_clock;
> +
> + /* Read back values from DPLL CFGCR registers */
> + cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> + cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> +
> + dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;
> + dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> + DPLL_CFGCR0_DCO_FRACTION_SHIFT;
> + pdiv = (cfgcr1 & DPLL_CFGCR1_PDIV_MASK) >>
> DPLL_CFGCR1_PDIV_SHIFT;
> + kdiv = (cfgcr1 & DPLL_CFGCR1_KDIV_MASK) >>
> DPLL_CFGCR1_KDIV_SHIFT;
> + qdiv_mode = (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) >>
> + DPLL_CFGCR1_QDIV_MODE_SHIFT;
> + qdiv_ratio = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
> + DPLL_CFGCR1_QDIV_RATIO_SHIFT;
> +
> + params = dev_priv->cdclk.hw.ref == 24000 ?
> + icl_dp_combo_pll_24MHz_values :
> + icl_dp_combo_pll_19_2MHz_values;
> + n_entries = ARRAY_SIZE(icl_dp_combo_pll_24MHz_values);
> +
> + for (index = 0; index < n_entries; index++) {
> + if (dco_integer == params[index].dco_integer &&
> + dco_fraction == params[index].dco_fraction &&
> + pdiv == params[index].pdiv &&
> + kdiv == params[index].kdiv &&
> + qdiv_mode == params[index].qdiv_mode &&
> + qdiv_ratio == params[index].qdiv_ratio)
> + break;
> + }
> +
> + /* Map PLL Index to Link Clock */
> + switch (index) {
> + default:
> + MISSING_CASE(index);
> + case 0:
> + link_clock = 540000;
> + break;
> + case 1:
> + link_clock = 270000;
> + break;
> + case 2:
> + link_clock = 162000;
> + break;
> + case 3:
> + link_clock = 324000;
> + break;
> + case 4:
> + link_clock = 216000;
> + break;
> + case 5:
> + link_clock = 432000;
> + break;
> + case 6:
> + link_clock = 648000;
> + break;
> + case 7:
> + link_clock = 810000;
> + break;
> + }
> +
> + return link_clock;
> +}
> +
> static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)
> {
> return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index 7a0cd564a9ee..78915057d2e6 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -336,5 +336,7 @@ void intel_shared_dpll_init(struct drm_device
> *dev);
>
> void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> struct intel_dpll_hw_state *hw_state);
> +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> + uint32_t pll_id);
>
> #endif /* _INTEL_DPLL_MGR_H_ */
--
Mika Kahola - Intel OTC
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 12/24] drm/i915/icl: Calculate link clock using the new registers
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (10 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-05-25 0:33 ` Paulo Zanoni
2018-05-22 0:25 ` [PATCH 13/24] drm/i915/icl: unconditionally init DDI for every port Paulo Zanoni
` (28 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
From: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Start using the new registers for ICL and on.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0d8bed8e2200..32e7482b64dd 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1381,8 +1381,13 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
uint32_t cfgcr0, cfgcr1;
uint32_t p0, p1, p2, dco_freq, ref_clock;
- cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
- cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
+ if (INTEL_GEN(dev_priv) >= 11) {
+ cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
+ cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
+ } else {
+ cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
+ cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
+ }
p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
--
2.14.3
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^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 12/24] drm/i915/icl: Calculate link clock using the new registers
2018-05-22 0:25 ` [PATCH 12/24] drm/i915/icl: Calculate link clock using the new registers Paulo Zanoni
@ 2018-05-25 0:33 ` Paulo Zanoni
0 siblings, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-25 0:33 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> From: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
>
> Start using the new registers for ICL and on.
I previously put this patch in a series that did not make use of
cnl_calc_wrpll_link() for ICL yet. This series makes ICL run
cnl_calc_wrpll_link(), so this patch makes sense now.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 0d8bed8e2200..32e7482b64dd 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1381,8 +1381,13 @@ static int cnl_calc_wrpll_link(struct
> drm_i915_private *dev_priv,
> uint32_t cfgcr0, cfgcr1;
> uint32_t p0, p1, p2, dco_freq, ref_clock;
>
> - cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
> - cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
> + if (INTEL_GEN(dev_priv) >= 11) {
> + cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> + cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> + } else {
> + cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
> + cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
> + }
>
> p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
> p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 13/24] drm/i915/icl: unconditionally init DDI for every port
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (11 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 12/24] drm/i915/icl: Calculate link clock using the new registers Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-06-13 23:34 ` Lucas De Marchi
2018-05-22 0:25 ` [PATCH 14/24] drm/i915/icl: start adding the TBT pll Paulo Zanoni
` (27 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
On ICP, port present straps are no longer supported. Software should
determine the presence through BIOS VBT, hotplug or other mechanisms.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d5a19c1b3b20..528d9f9c456d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13965,7 +13965,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (intel_crt_present(dev_priv))
intel_crt_init(dev_priv);
- if (IS_GEN9_LP(dev_priv)) {
+ if (IS_ICELAKE(dev_priv)) {
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_C);
+ intel_ddi_init(dev_priv, PORT_D);
+ intel_ddi_init(dev_priv, PORT_E);
+ intel_ddi_init(dev_priv, PORT_F);
+ } else if (IS_GEN9_LP(dev_priv)) {
/*
* FIXME: Broxton doesn't support port detection via the
* DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 13/24] drm/i915/icl: unconditionally init DDI for every port
2018-05-22 0:25 ` [PATCH 13/24] drm/i915/icl: unconditionally init DDI for every port Paulo Zanoni
@ 2018-06-13 23:34 ` Lucas De Marchi
2018-06-13 23:47 ` Paulo Zanoni
0 siblings, 1 reply; 127+ messages in thread
From: Lucas De Marchi @ 2018-06-13 23:34 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Mon, May 21, 2018 at 05:25:47PM -0700, Paulo Zanoni wrote:
> On ICP, port present straps are no longer supported. Software should
ICP?? Doesn't it make more sense to say on ICL here?
> determine the presence through BIOS VBT, hotplug or other mechanisms.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d5a19c1b3b20..528d9f9c456d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13965,7 +13965,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> if (intel_crt_present(dev_priv))
> intel_crt_init(dev_priv);
>
> - if (IS_GEN9_LP(dev_priv)) {
> + if (IS_ICELAKE(dev_priv)) {
> + intel_ddi_init(dev_priv, PORT_A);
> + intel_ddi_init(dev_priv, PORT_B);
> + intel_ddi_init(dev_priv, PORT_C);
> + intel_ddi_init(dev_priv, PORT_D);
> + intel_ddi_init(dev_priv, PORT_E);
> + intel_ddi_init(dev_priv, PORT_F);
> + } else if (IS_GEN9_LP(dev_priv)) {
> /*
> * FIXME: Broxton doesn't support port detection via the
> * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 13/24] drm/i915/icl: unconditionally init DDI for every port
2018-06-13 23:34 ` Lucas De Marchi
@ 2018-06-13 23:47 ` Paulo Zanoni
0 siblings, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-06-13 23:47 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
Em Qua, 2018-06-13 às 16:34 -0700, Lucas De Marchi escreveu:
> On Mon, May 21, 2018 at 05:25:47PM -0700, Paulo Zanoni wrote:
> > On ICP, port present straps are no longer supported. Software
> > should
>
> ICP?? Doesn't it make more sense to say on ICL here?
The register that used to have the port present straps was in the PCH,
it's SFUSE_STRAP. I'll reword the commit message to explicitly mention
it, since the wording on the commit message is basically what's written
on the SFUSE_TRAP page.
>
> > determine the presence through BIOS VBT, hotplug or other
> > mechanisms.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
Thanks a lot,
Paulo
> Lucas De Marchi
>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 9 ++++++++-
> > 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index d5a19c1b3b20..528d9f9c456d 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -13965,7 +13965,14 @@ static void intel_setup_outputs(struct
> > drm_i915_private *dev_priv)
> > if (intel_crt_present(dev_priv))
> > intel_crt_init(dev_priv);
> >
> > - if (IS_GEN9_LP(dev_priv)) {
> > + if (IS_ICELAKE(dev_priv)) {
> > + intel_ddi_init(dev_priv, PORT_A);
> > + intel_ddi_init(dev_priv, PORT_B);
> > + intel_ddi_init(dev_priv, PORT_C);
> > + intel_ddi_init(dev_priv, PORT_D);
> > + intel_ddi_init(dev_priv, PORT_E);
> > + intel_ddi_init(dev_priv, PORT_F);
> > + } else if (IS_GEN9_LP(dev_priv)) {
> > /*
> > * FIXME: Broxton doesn't support port detection
> > via the
> > * DDI_BUF_CTL_A or SFUSE_STRAP registers, find
> > another way to
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 14/24] drm/i915/icl: start adding the TBT pll
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (12 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 13/24] drm/i915/icl: unconditionally init DDI for every port Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-06-14 0:37 ` Lucas De Marchi
2018-05-22 0:25 ` [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers Paulo Zanoni
` (26 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
This commit just adds the register addresses and the basic skeleton of
the code. The next commits will expand on more specific functions.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/intel_dpll_mgr.c | 20 ++++++++++++++++----
drivers/gpu/drm/i915/intel_dpll_mgr.h | 14 +++++++++-----
4 files changed, 47 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 26903cffabf6..ce79913466a7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8878,6 +8878,10 @@ enum skl_power_gate {
#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
#define DDI_CLK_SEL_NONE (0x0 << 28)
#define DDI_CLK_SEL_MG (0x8 << 28)
+#define DDI_CLK_SEL_TBT_162 (0xC << 28)
+#define DDI_CLK_SEL_TBT_270 (0xD << 28)
+#define DDI_CLK_SEL_TBT_540 (0xE << 28)
+#define DDI_CLK_SEL_TBT_810 (0xF << 28)
#define DDI_CLK_SEL_MASK (0xF << 28)
/* Transcoder clock selection */
@@ -9027,6 +9031,8 @@ enum skl_power_gate {
#define PLL_POWER_STATE (1 << 26)
#define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
+#define TBT_PLL_ENABLE _MMIO(0x46020)
+
#define _MG_PLL1_ENABLE 0x46030
#define _MG_PLL2_ENABLE 0x46034
#define _MG_PLL3_ENABLE 0x46038
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 32e7482b64dd..1d5bfec57c33 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1062,6 +1062,8 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
const struct intel_shared_dpll *pll)
{
+ struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+ int clock = crtc->config->port_clock;
const enum intel_dpll_id id = pll->info->id;
switch (id) {
@@ -1070,6 +1072,20 @@ static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
case DPLL_ID_ICL_DPLL0:
case DPLL_ID_ICL_DPLL1:
return DDI_CLK_SEL_NONE;
+ case DPLL_ID_ICL_TBTPLL:
+ switch (clock) {
+ case 162000:
+ return DDI_CLK_SEL_TBT_162;
+ case 270000:
+ return DDI_CLK_SEL_TBT_270;
+ case 540000:
+ return DDI_CLK_SEL_TBT_540;
+ case 810000:
+ return DDI_CLK_SEL_TBT_810;
+ default:
+ MISSING_CASE(clock);
+ break;
+ }
case DPLL_ID_ICL_MGPLL1:
case DPLL_ID_ICL_MGPLL2:
case DPLL_ID_ICL_MGPLL3:
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 3cc837f74ffb..72f15e727d07 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2853,10 +2853,17 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
case PORT_D:
case PORT_E:
case PORT_F:
- min = icl_port_to_mg_pll_id(port);
- max = min;
- ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
- &pll_state);
+ if (0 /* TODO: TBT PLLs */) {
+ min = DPLL_ID_ICL_TBTPLL;
+ max = min;
+ ret = icl_calc_dpll_state(crtc_state, encoder, clock,
+ &pll_state);
+ } else {
+ min = icl_port_to_mg_pll_id(port);
+ max = min;
+ ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
+ &pll_state);
+ }
break;
default:
MISSING_CASE(port);
@@ -2889,6 +2896,8 @@ static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
case DPLL_ID_ICL_DPLL0:
case DPLL_ID_ICL_DPLL1:
return CNL_DPLL_ENABLE(id);
+ case DPLL_ID_ICL_TBTPLL:
+ return TBT_PLL_ENABLE;
case DPLL_ID_ICL_MGPLL1:
case DPLL_ID_ICL_MGPLL2:
case DPLL_ID_ICL_MGPLL3:
@@ -2916,6 +2925,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
switch (id) {
case DPLL_ID_ICL_DPLL0:
case DPLL_ID_ICL_DPLL1:
+ case DPLL_ID_ICL_TBTPLL:
hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
break;
@@ -3002,6 +3012,7 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
switch (id) {
case DPLL_ID_ICL_DPLL0:
case DPLL_ID_ICL_DPLL1:
+ case DPLL_ID_ICL_TBTPLL:
icl_dpll_write(dev_priv, pll);
break;
case DPLL_ID_ICL_MGPLL1:
@@ -3100,6 +3111,7 @@ static const struct intel_shared_dpll_funcs icl_pll_funcs = {
static const struct dpll_info icl_plls[] = {
{ "DPLL 0", &icl_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
{ "DPLL 1", &icl_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "TBT PLL", &icl_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
{ "MG PLL 1", &icl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
{ "MG PLL 2", &icl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
{ "MG PLL 3", &icl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index 78915057d2e6..ba925c7ee482 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -113,24 +113,28 @@ enum intel_dpll_id {
* @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
*/
DPLL_ID_ICL_DPLL1 = 1,
+ /**
+ * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
+ */
+ DPLL_ID_ICL_TBTPLL = 2,
/**
* @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
*/
- DPLL_ID_ICL_MGPLL1 = 2,
+ DPLL_ID_ICL_MGPLL1 = 3,
/**
* @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
*/
- DPLL_ID_ICL_MGPLL2 = 3,
+ DPLL_ID_ICL_MGPLL2 = 4,
/**
* @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
*/
- DPLL_ID_ICL_MGPLL3 = 4,
+ DPLL_ID_ICL_MGPLL3 = 5,
/**
* @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
*/
- DPLL_ID_ICL_MGPLL4 = 5,
+ DPLL_ID_ICL_MGPLL4 = 6,
};
-#define I915_NUM_PLLS 6
+#define I915_NUM_PLLS 7
struct intel_dpll_hw_state {
/* i9xx, pch plls */
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 14/24] drm/i915/icl: start adding the TBT pll
2018-05-22 0:25 ` [PATCH 14/24] drm/i915/icl: start adding the TBT pll Paulo Zanoni
@ 2018-06-14 0:37 ` Lucas De Marchi
0 siblings, 0 replies; 127+ messages in thread
From: Lucas De Marchi @ 2018-06-14 0:37 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Mon, May 21, 2018 at 05:25:48PM -0700, Paulo Zanoni wrote:
> This commit just adds the register addresses and the basic skeleton of
> the code. The next commits will expand on more specific functions.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++++++++++
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 20 ++++++++++++++++----
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 14 +++++++++-----
> 4 files changed, 47 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 26903cffabf6..ce79913466a7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8878,6 +8878,10 @@ enum skl_power_gate {
> #define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
> #define DDI_CLK_SEL_NONE (0x0 << 28)
> #define DDI_CLK_SEL_MG (0x8 << 28)
> +#define DDI_CLK_SEL_TBT_162 (0xC << 28)
> +#define DDI_CLK_SEL_TBT_270 (0xD << 28)
> +#define DDI_CLK_SEL_TBT_540 (0xE << 28)
> +#define DDI_CLK_SEL_TBT_810 (0xF << 28)
> #define DDI_CLK_SEL_MASK (0xF << 28)
>
> /* Transcoder clock selection */
> @@ -9027,6 +9031,8 @@ enum skl_power_gate {
> #define PLL_POWER_STATE (1 << 26)
> #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
>
> +#define TBT_PLL_ENABLE _MMIO(0x46020)
> +
> #define _MG_PLL1_ENABLE 0x46030
> #define _MG_PLL2_ENABLE 0x46034
> #define _MG_PLL3_ENABLE 0x46038
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 32e7482b64dd..1d5bfec57c33 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1062,6 +1062,8 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
> const struct intel_shared_dpll *pll)
> {
> + struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> + int clock = crtc->config->port_clock;
> const enum intel_dpll_id id = pll->info->id;
>
> switch (id) {
> @@ -1070,6 +1072,20 @@ static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
> case DPLL_ID_ICL_DPLL0:
> case DPLL_ID_ICL_DPLL1:
> return DDI_CLK_SEL_NONE;
> + case DPLL_ID_ICL_TBTPLL:
> + switch (clock) {
> + case 162000:
> + return DDI_CLK_SEL_TBT_162;
> + case 270000:
> + return DDI_CLK_SEL_TBT_270;
> + case 540000:
> + return DDI_CLK_SEL_TBT_540;
> + case 810000:
> + return DDI_CLK_SEL_TBT_810;
> + default:
> + MISSING_CASE(clock);
> + break;
> + }
> case DPLL_ID_ICL_MGPLL1:
> case DPLL_ID_ICL_MGPLL2:
> case DPLL_ID_ICL_MGPLL3:
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 3cc837f74ffb..72f15e727d07 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2853,10 +2853,17 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
> case PORT_D:
> case PORT_E:
> case PORT_F:
> - min = icl_port_to_mg_pll_id(port);
> - max = min;
> - ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
> - &pll_state);
> + if (0 /* TODO: TBT PLLs */) {
> + min = DPLL_ID_ICL_TBTPLL;
> + max = min;
> + ret = icl_calc_dpll_state(crtc_state, encoder, clock,
> + &pll_state);
> + } else {
> + min = icl_port_to_mg_pll_id(port);
> + max = min;
> + ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
> + &pll_state);
> + }
> break;
> default:
> MISSING_CASE(port);
> @@ -2889,6 +2896,8 @@ static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
> case DPLL_ID_ICL_DPLL0:
> case DPLL_ID_ICL_DPLL1:
> return CNL_DPLL_ENABLE(id);
> + case DPLL_ID_ICL_TBTPLL:
> + return TBT_PLL_ENABLE;
> case DPLL_ID_ICL_MGPLL1:
> case DPLL_ID_ICL_MGPLL2:
> case DPLL_ID_ICL_MGPLL3:
> @@ -2916,6 +2925,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
> switch (id) {
> case DPLL_ID_ICL_DPLL0:
> case DPLL_ID_ICL_DPLL1:
> + case DPLL_ID_ICL_TBTPLL:
> hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> break;
> @@ -3002,6 +3012,7 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
> switch (id) {
> case DPLL_ID_ICL_DPLL0:
> case DPLL_ID_ICL_DPLL1:
> + case DPLL_ID_ICL_TBTPLL:
> icl_dpll_write(dev_priv, pll);
> break;
> case DPLL_ID_ICL_MGPLL1:
> @@ -3100,6 +3111,7 @@ static const struct intel_shared_dpll_funcs icl_pll_funcs = {
> static const struct dpll_info icl_plls[] = {
> { "DPLL 0", &icl_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> { "DPLL 1", &icl_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> + { "TBT PLL", &icl_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
> { "MG PLL 1", &icl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
> { "MG PLL 2", &icl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
> { "MG PLL 3", &icl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index 78915057d2e6..ba925c7ee482 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -113,24 +113,28 @@ enum intel_dpll_id {
> * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
> */
> DPLL_ID_ICL_DPLL1 = 1,
> + /**
> + * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
> + */
> + DPLL_ID_ICL_TBTPLL = 2,
> /**
> * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
> */
> - DPLL_ID_ICL_MGPLL1 = 2,
> + DPLL_ID_ICL_MGPLL1 = 3,
> /**
> * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
> */
> - DPLL_ID_ICL_MGPLL2 = 3,
> + DPLL_ID_ICL_MGPLL2 = 4,
> /**
> * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
> */
> - DPLL_ID_ICL_MGPLL3 = 4,
> + DPLL_ID_ICL_MGPLL3 = 5,
> /**
> * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
> */
> - DPLL_ID_ICL_MGPLL4 = 5,
> + DPLL_ID_ICL_MGPLL4 = 6,
> };
> -#define I915_NUM_PLLS 6
> +#define I915_NUM_PLLS 7
>
> struct intel_dpll_hw_state {
> /* i9xx, pch plls */
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (13 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 14/24] drm/i915/icl: start adding the TBT pll Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-06-08 20:19 ` Srivatsa, Anusha
2018-06-13 21:42 ` [PATCH v2 " Paulo Zanoni
2018-05-22 0:25 ` [PATCH 16/24] drm/i915/icl: Handle hotplug interrupts for DP over TBT Paulo Zanoni
` (25 subsequent siblings)
40 siblings, 2 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Use the hardcoded tables provided by our spec.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 25 ++++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 72f15e727d07..8a34733de1ea 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2452,6 +2452,16 @@ static const struct skl_wrpll_params icl_dp_combo_pll_19_2MHz_values[] = {
.pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
};
+static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
+ .dco_integer = 0x151, .dco_fraction = 0x4000,
+ .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
+};
+
+static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
+ .dco_integer = 0x1A5, .dco_fraction = 0x7000,
+ .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
+};
+
static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int clock,
struct skl_wrpll_params *pll_params)
{
@@ -2494,6 +2504,14 @@ static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int clock,
return true;
}
+static bool icl_calc_tbt_pll(struct drm_i915_private *dev_priv, int clock,
+ struct skl_wrpll_params *pll_params)
+{
+ *pll_params = dev_priv->cdclk.hw.ref == 24000 ?
+ icl_tbt_pll_24MHz_values : icl_tbt_pll_19_2MHz_values;
+ return true;
+}
+
static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder, int clock,
struct intel_dpll_hw_state *pll_state)
@@ -2501,9 +2519,12 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
uint32_t cfgcr0, cfgcr1;
struct skl_wrpll_params pll_params = { 0 };
+ bool is_tbt = encoder->port >= PORT_C;
bool ret;
- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ if (is_tbt)
+ ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
else
ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params);
@@ -2513,6 +2534,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
pll_params.dco_integer;
+ if (is_tbt)
+ cfgcr0 |= DPLL_CFGCR0_SSC_ENABLE_ICL;
cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers
2018-05-22 0:25 ` [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers Paulo Zanoni
@ 2018-06-08 20:19 ` Srivatsa, Anusha
2018-06-13 21:19 ` Paulo Zanoni
2018-06-13 21:42 ` [PATCH v2 " Paulo Zanoni
1 sibling, 1 reply; 127+ messages in thread
From: Srivatsa, Anusha @ 2018-06-08 20:19 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org; +Cc: Zanoni, Paulo R
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Paulo Zanoni
>Sent: Monday, May 21, 2018 5:26 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Zanoni, Paulo R <paulo.r.zanoni@intel.com>
>Subject: [Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers
>
>Use the hardcoded tables provided by our spec.
>
>Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 25 ++++++++++++++++++++++++-
> 1 file changed, 24 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>index 72f15e727d07..8a34733de1ea 100644
>--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>@@ -2452,6 +2452,16 @@ static const struct skl_wrpll_params
>icl_dp_combo_pll_19_2MHz_values[] = {
> .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0}, };
>
>+static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
>+ .dco_integer = 0x151, .dco_fraction = 0x4000,
>+ .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, };
>+
>+static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
>+ .dco_integer = 0x1A5, .dco_fraction = 0x7000,
>+ .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, };
>+
> static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int clock,
> struct skl_wrpll_params *pll_params) { @@ -
>2494,6 +2504,14 @@ static bool icl_calc_dp_combo_pll(struct drm_i915_private
>*dev_priv, int clock,
> return true;
> }
>
>+static bool icl_calc_tbt_pll(struct drm_i915_private *dev_priv, int clock,
>+ struct skl_wrpll_params *pll_params) {
>+ *pll_params = dev_priv->cdclk.hw.ref == 24000 ?
>+ icl_tbt_pll_24MHz_values : icl_tbt_pll_19_2MHz_values;
>+ return true;
>+}
>+
> static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder, int clock,
> struct intel_dpll_hw_state *pll_state) @@ -
>2501,9 +2519,12 @@ static bool icl_calc_dpll_state(struct intel_crtc_state
>*crtc_state,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> uint32_t cfgcr0, cfgcr1;
> struct skl_wrpll_params pll_params = { 0 };
>+ bool is_tbt = encoder->port >= PORT_C;
> bool ret;
>
>- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>+ if (is_tbt)
>+ ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
>+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
> else
> ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params); @@ -
>2513,6 +2534,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state
>*crtc_state,
>
> cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
> pll_params.dco_integer;
>+ if (is_tbt)
>+ cfgcr0 |= DPLL_CFGCR0_SSC_ENABLE_ICL;
Paulo,
TBT has some TBT specific CFGCR0 registers which needs to be configured here.
Anusha
> cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
> DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
>--
>2.14.3
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers
2018-06-08 20:19 ` Srivatsa, Anusha
@ 2018-06-13 21:19 ` Paulo Zanoni
2018-06-18 19:57 ` Srivatsa, Anusha
0 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-06-13 21:19 UTC (permalink / raw)
To: Srivatsa, Anusha, intel-gfx@lists.freedesktop.org
Em Sex, 2018-06-08 às 13:19 -0700, Srivatsa, Anusha escreveu:
> > -----Original Message-----
> > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On
> > Behalf Of
> > Paulo Zanoni
> > Sent: Monday, May 21, 2018 5:26 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Zanoni, Paulo R <paulo.r.zanoni@intel.com>
> > Subject: [Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT
> > PLL registers
> >
> > Use the hardcoded tables provided by our spec.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dpll_mgr.c | 25
> > ++++++++++++++++++++++++-
> > 1 file changed, 24 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index 72f15e727d07..8a34733de1ea 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -2452,6 +2452,16 @@ static const struct skl_wrpll_params
> > icl_dp_combo_pll_19_2MHz_values[] = {
> > .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio =
> > 0}, };
> >
> > +static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
> > + .dco_integer = 0x151, .dco_fraction = 0x4000,
> > + .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0,
> > .qdiv_ratio = 0, };
> > +
> > +static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values =
> > {
> > + .dco_integer = 0x1A5, .dco_fraction = 0x7000,
> > + .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0,
> > .qdiv_ratio = 0, };
> > +
> > static bool icl_calc_dp_combo_pll(struct drm_i915_private
> > *dev_priv, int clock,
> > struct skl_wrpll_params
> > *pll_params) { @@ -
> > 2494,6 +2504,14 @@ static bool icl_calc_dp_combo_pll(struct
> > drm_i915_private
> > *dev_priv, int clock,
> > return true;
> > }
> >
> > +static bool icl_calc_tbt_pll(struct drm_i915_private *dev_priv,
> > int clock,
> > + struct skl_wrpll_params *pll_params)
> > {
> > + *pll_params = dev_priv->cdclk.hw.ref == 24000 ?
> > + icl_tbt_pll_24MHz_values :
> > icl_tbt_pll_19_2MHz_values;
> > + return true;
> > +}
> > +
> > static bool icl_calc_dpll_state(struct intel_crtc_state
> > *crtc_state,
> > struct intel_encoder *encoder, int
> > clock,
> > struct intel_dpll_hw_state *pll_state)
> > @@ -
> > 2501,9 +2519,12 @@ static bool icl_calc_dpll_state(struct
> > intel_crtc_state
> > *crtc_state,
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > uint32_t cfgcr0, cfgcr1;
> > struct skl_wrpll_params pll_params = { 0 };
> > + bool is_tbt = encoder->port >= PORT_C;
> > bool ret;
> >
> > - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> > + if (is_tbt)
> > + ret = icl_calc_tbt_pll(dev_priv, clock,
> > &pll_params);
> > + else if (intel_crtc_has_type(crtc_state,
> > INTEL_OUTPUT_HDMI))
> > ret = cnl_ddi_calculate_wrpll(clock, dev_priv,
> > &pll_params);
> > else
> > ret = icl_calc_dp_combo_pll(dev_priv, clock,
> > &pll_params); @@ -
> > 2513,6 +2534,8 @@ static bool icl_calc_dpll_state(struct
> > intel_crtc_state
> > *crtc_state,
> >
> > cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
> > pll_params.dco_integer;
> > + if (is_tbt)
> > + cfgcr0 |= DPLL_CFGCR0_SSC_ENABLE_ICL;
>
> Paulo,
> TBT has some TBT specific CFGCR0 registers which needs to be
> configured here.
I did recheck the spec and it says to disable SSC, so the line above is
clearly wrong (did it change since I wrote it?), but I don't see
anything we're failing to set on CFGCR0. Can you please clarify what
you think is missing? Maybe you're referring to something that's on
patch 14?
Thanks,
Paulo
>
> Anusha
> > cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
> > DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers
2018-06-13 21:19 ` Paulo Zanoni
@ 2018-06-18 19:57 ` Srivatsa, Anusha
0 siblings, 0 replies; 127+ messages in thread
From: Srivatsa, Anusha @ 2018-06-18 19:57 UTC (permalink / raw)
To: Zanoni, Paulo R, intel-gfx@lists.freedesktop.org
>-----Original Message-----
>From: Zanoni, Paulo R
>Sent: Wednesday, June 13, 2018 2:19 PM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
>gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT PLL
>registers
>
>Em Sex, 2018-06-08 às 13:19 -0700, Srivatsa, Anusha escreveu:
>> > -----Original Message-----
>> > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On
>> > Behalf Of Paulo Zanoni
>> > Sent: Monday, May 21, 2018 5:26 PM
>> > To: intel-gfx@lists.freedesktop.org
>> > Cc: Zanoni, Paulo R <paulo.r.zanoni@intel.com>
>> > Subject: [Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT PLL
>> > registers
>> >
>> > Use the hardcoded tables provided by our spec.
>> >
>> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/intel_dpll_mgr.c | 25
>> > ++++++++++++++++++++++++-
>> > 1 file changed, 24 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> > index 72f15e727d07..8a34733de1ea 100644
>> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> > @@ -2452,6 +2452,16 @@ static const struct skl_wrpll_params
>> > icl_dp_combo_pll_19_2MHz_values[] = {
>> > .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
>> > };
>> >
>> > +static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
>> > + .dco_integer = 0x151, .dco_fraction = 0x4000,
>> > + .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0,
>> > .qdiv_ratio = 0, };
>> > +
>> > +static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values =
>> > {
>> > + .dco_integer = 0x1A5, .dco_fraction = 0x7000,
>> > + .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0,
>> > .qdiv_ratio = 0, };
>> > +
>> > static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv,
>> > int clock,
>> > struct skl_wrpll_params
>> > *pll_params) { @@ -
>> > 2494,6 +2504,14 @@ static bool icl_calc_dp_combo_pll(struct
>> > drm_i915_private *dev_priv, int clock,
>> > return true;
>> > }
>> >
>> > +static bool icl_calc_tbt_pll(struct drm_i915_private *dev_priv,
>> > int clock,
>> > + struct skl_wrpll_params *pll_params)
>> > {
>> > + *pll_params = dev_priv->cdclk.hw.ref == 24000 ?
>> > + icl_tbt_pll_24MHz_values :
>> > icl_tbt_pll_19_2MHz_values;
>> > + return true;
>> > +}
>> > +
>> > static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
>> > struct intel_encoder *encoder, int clock,
>> > struct intel_dpll_hw_state *pll_state) @@ -
>> > 2501,9 +2519,12 @@ static bool icl_calc_dpll_state(struct
>> > intel_crtc_state *crtc_state,
>> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> > uint32_t cfgcr0, cfgcr1;
>> > struct skl_wrpll_params pll_params = { 0 };
>> > + bool is_tbt = encoder->port >= PORT_C;
>> > bool ret;
>> >
>> > - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>> > + if (is_tbt)
>> > + ret = icl_calc_tbt_pll(dev_priv, clock,
>> > &pll_params);
>> > + else if (intel_crtc_has_type(crtc_state,
>> > INTEL_OUTPUT_HDMI))
>> > ret = cnl_ddi_calculate_wrpll(clock, dev_priv,
>> > &pll_params);
>> > else
>> > ret = icl_calc_dp_combo_pll(dev_priv, clock,
>> > &pll_params); @@ -
>> > 2513,6 +2534,8 @@ static bool icl_calc_dpll_state(struct
>> > intel_crtc_state
>> > *crtc_state,
>> >
>> > cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
>> > pll_params.dco_integer;
>> > + if (is_tbt)
>> > + cfgcr0 |= DPLL_CFGCR0_SSC_ENABLE_ICL;
>>
>> Paulo,
>> TBT has some TBT specific CFGCR0 registers which needs to be
>> configured here.
>
>I did recheck the spec and it says to disable SSC, so the line above is
>clearly wrong (did it change since I wrote it?), but I don't see
>anything we're failing to set on CFGCR0. Can you please clarify what
>you think is missing? Maybe you're referring to something that's on
>patch 14?
Sorry, my mistake. The cfgcro0 registers are being configured here. But yes, like you pointed out, the TBT cfgcr0 register has to be configured by disabling the DDC and enabling dco frequency.
Anusha
>Thanks,
>Paulo
>
>>
>> Anusha
>> > cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
>> > DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
>> > --
>> > 2.14.3
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH v2 15/24] drm/i915/icl: compute the TBT PLL registers
2018-05-22 0:25 ` [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers Paulo Zanoni
2018-06-08 20:19 ` Srivatsa, Anusha
@ 2018-06-13 21:42 ` Paulo Zanoni
1 sibling, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-06-13 21:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Use the hardcoded tables provided by our spec.
v2:
- SSC stays disabled.
- Use intel_port_is_tc().
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 132fe63e042a..205cc723fb26 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2452,6 +2452,16 @@ static const struct skl_wrpll_params icl_dp_combo_pll_19_2MHz_values[] = {
.pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
};
+static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
+ .dco_integer = 0x151, .dco_fraction = 0x4000,
+ .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
+};
+
+static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
+ .dco_integer = 0x1A5, .dco_fraction = 0x7000,
+ .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
+};
+
static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int clock,
struct skl_wrpll_params *pll_params)
{
@@ -2494,6 +2504,14 @@ static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int clock,
return true;
}
+static bool icl_calc_tbt_pll(struct drm_i915_private *dev_priv, int clock,
+ struct skl_wrpll_params *pll_params)
+{
+ *pll_params = dev_priv->cdclk.hw.ref == 24000 ?
+ icl_tbt_pll_24MHz_values : icl_tbt_pll_19_2MHz_values;
+ return true;
+}
+
static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder, int clock,
struct intel_dpll_hw_state *pll_state)
@@ -2503,7 +2521,9 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
struct skl_wrpll_params pll_params = { 0 };
bool ret;
- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ if (intel_port_is_tc(dev_priv, encoder->port))
+ ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
else
ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params);
--
2.14.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH 16/24] drm/i915/icl: Handle hotplug interrupts for DP over TBT
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (14 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-06-14 0:51 ` Lucas De Marchi
2018-05-22 0:25 ` [PATCH 17/24] drm/i915/icl: Add 10-bit support for hdmi Paulo Zanoni
` (24 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Paulo Zanoni
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
This patch enables hotplug interrupts for DP over TBT output on TC
ports. The TBT interrupts are enabled and handled irrespective of the
actual output type which could be DP Alternate, DP over TBT, native DP
or native HDMI.
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 49 ++++++++++++++++++++++++++++++-----------
drivers/gpu/drm/i915/i915_reg.h | 11 ++++++++-
2 files changed, 46 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6b109991786f..9f1b01ca4ed1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -115,11 +115,11 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
};
-static const u32 hpd_tc_gen11[HPD_NUM_PINS] = {
- [HPD_PORT_C] = GEN11_TC1_HOTPLUG,
- [HPD_PORT_D] = GEN11_TC2_HOTPLUG,
- [HPD_PORT_E] = GEN11_TC3_HOTPLUG,
- [HPD_PORT_F] = GEN11_TC4_HOTPLUG
+static const u32 hpd_gen11[HPD_NUM_PINS] = {
+ [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
+ [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
+ [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
+ [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG
};
static const u32 hpd_icp[HPD_NUM_PINS] = {
@@ -2690,20 +2690,35 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
{
u32 pin_mask = 0, long_mask = 0;
- u32 trigger_tc, dig_hotplug_reg;
+ u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
+ u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
- trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
if (trigger_tc) {
+ u32 dig_hotplug_reg;
+
dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
- dig_hotplug_reg, hpd_tc_gen11,
+ dig_hotplug_reg, hpd_gen11,
+ gen11_port_hotplug_long_detect);
+ }
+
+ if (trigger_tbt) {
+ u32 dig_hotplug_reg;
+
+ dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
+ I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
+
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt,
+ dig_hotplug_reg, hpd_gen11,
gen11_port_hotplug_long_detect);
+ }
+
+ if (pin_mask)
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
- } else {
+ else
DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir);
- }
}
static irqreturn_t
@@ -3783,6 +3798,13 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
+
+ hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
+ hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
+ I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
}
static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
@@ -3790,8 +3812,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
u32 hotplug_irqs, enabled_irqs;
u32 val;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_tc_gen11);
- hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK;
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_gen11);
+ hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK;
val = I915_READ(GEN11_DE_HPD_IMR);
val &= ~hotplug_irqs;
@@ -4176,7 +4198,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) >= 11) {
u32 de_hpd_masked = 0;
- u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK;
+ u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
+ GEN11_DE_TBT_HOTPLUG_MASK;
GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables);
gen11_hpd_detection_setup(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ce79913466a7..49a72320e794 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7059,7 +7059,16 @@ enum {
GEN11_TC3_HOTPLUG | \
GEN11_TC2_HOTPLUG | \
GEN11_TC1_HOTPLUG)
-
+#define GEN11_TBT4_HOTPLUG (1 << 3)
+#define GEN11_TBT3_HOTPLUG (1 << 2)
+#define GEN11_TBT2_HOTPLUG (1 << 1)
+#define GEN11_TBT1_HOTPLUG (1 << 0)
+#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \
+ GEN11_TBT3_HOTPLUG | \
+ GEN11_TBT2_HOTPLUG | \
+ GEN11_TBT1_HOTPLUG)
+
+#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
#define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4)
#define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 16/24] drm/i915/icl: Handle hotplug interrupts for DP over TBT
2018-05-22 0:25 ` [PATCH 16/24] drm/i915/icl: Handle hotplug interrupts for DP over TBT Paulo Zanoni
@ 2018-06-14 0:51 ` Lucas De Marchi
0 siblings, 0 replies; 127+ messages in thread
From: Lucas De Marchi @ 2018-06-14 0:51 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Dhinakaran Pandiyan
On Mon, May 21, 2018 at 05:25:50PM -0700, Paulo Zanoni wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>
> This patch enables hotplug interrupts for DP over TBT output on TC
> ports. The TBT interrupts are enabled and handled irrespective of the
> actual output type which could be DP Alternate, DP over TBT, native DP
> or native HDMI.
>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_irq.c | 49 ++++++++++++++++++++++++++++++-----------
> drivers/gpu/drm/i915/i915_reg.h | 11 ++++++++-
> 2 files changed, 46 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 6b109991786f..9f1b01ca4ed1 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -115,11 +115,11 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
> [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
> };
>
> -static const u32 hpd_tc_gen11[HPD_NUM_PINS] = {
> - [HPD_PORT_C] = GEN11_TC1_HOTPLUG,
> - [HPD_PORT_D] = GEN11_TC2_HOTPLUG,
> - [HPD_PORT_E] = GEN11_TC3_HOTPLUG,
> - [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> +static const u32 hpd_gen11[HPD_NUM_PINS] = {
> + [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
> + [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
> + [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
> + [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG
> };
>
> static const u32 hpd_icp[HPD_NUM_PINS] = {
> @@ -2690,20 +2690,35 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
> static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> {
> u32 pin_mask = 0, long_mask = 0;
> - u32 trigger_tc, dig_hotplug_reg;
> + u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
> + u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
>
> - trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
> if (trigger_tc) {
> + u32 dig_hotplug_reg;
> +
> dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
> I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
> - dig_hotplug_reg, hpd_tc_gen11,
> + dig_hotplug_reg, hpd_gen11,
> + gen11_port_hotplug_long_detect);
> + }
> +
> + if (trigger_tbt) {
> + u32 dig_hotplug_reg;
> +
> + dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
> + I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
> +
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt,
> + dig_hotplug_reg, hpd_gen11,
> gen11_port_hotplug_long_detect);
> + }
> +
> + if (pin_mask)
> intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> - } else {
> + else
> DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir);
> - }
> }
>
> static irqreturn_t
> @@ -3783,6 +3798,13 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
> GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
> GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
> I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
> +
> + hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
> + hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
> + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
> + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
> + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
> + I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
> }
>
> static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
> @@ -3790,8 +3812,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
> u32 hotplug_irqs, enabled_irqs;
> u32 val;
>
> - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_tc_gen11);
> - hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK;
> + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_gen11);
> + hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK;
>
> val = I915_READ(GEN11_DE_HPD_IMR);
> val &= ~hotplug_irqs;
> @@ -4176,7 +4198,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>
> if (INTEL_GEN(dev_priv) >= 11) {
> u32 de_hpd_masked = 0;
> - u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK;
> + u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
> + GEN11_DE_TBT_HOTPLUG_MASK;
>
> GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables);
> gen11_hpd_detection_setup(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ce79913466a7..49a72320e794 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7059,7 +7059,16 @@ enum {
> GEN11_TC3_HOTPLUG | \
> GEN11_TC2_HOTPLUG | \
> GEN11_TC1_HOTPLUG)
> -
> +#define GEN11_TBT4_HOTPLUG (1 << 3)
> +#define GEN11_TBT3_HOTPLUG (1 << 2)
> +#define GEN11_TBT2_HOTPLUG (1 << 1)
> +#define GEN11_TBT1_HOTPLUG (1 << 0)
> +#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \
> + GEN11_TBT3_HOTPLUG | \
> + GEN11_TBT2_HOTPLUG | \
> + GEN11_TBT1_HOTPLUG)
> +
> +#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
> #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
> #define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4)
> #define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 17/24] drm/i915/icl: Add 10-bit support for hdmi
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (15 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 16/24] drm/i915/icl: Handle hotplug interrupts for DP over TBT Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-06-20 16:55 ` Ville Syrjälä
2018-05-22 0:25 ` [PATCH 18/24] drm/i915/icl: implement icl_digital_port_connected() Paulo Zanoni
` (23 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
From: "Sripada, Radhakrishna" <radhakrishna.sripada@intel.com>
Starting Icelake silicon supports 10-bpc hdmi to support certain
media workloads. Currently hdmi supports 8 and 12 bpc. Plumbed
in support for 10 bit hdmi.
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 64 +++++++++++++++++++++++++++++----------
1 file changed, 48 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 0ca4cc877520..53ac8bb85218 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1561,14 +1561,23 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
/* check if we can do 8bpc */
status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
- /* if we can't do 8bpc we may still be able to do 12bpc */
- if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi)
- status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi);
+ if (hdmi->has_hdmi_sink && !force_dvi) {
+ /* if we can't do 8bpc we may still be able to do 12bpc */
+ if (status != MODE_OK && !HAS_GMCH_DISPLAY(dev_priv))
+ status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
+ true, force_dvi);
+
+ /* if we can't do 8,12bpc we may still be able to do 10bpc */
+ if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
+ status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
+ true, force_dvi);
+ }
return status;
}
-static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
+static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
+ int bpc)
{
struct drm_i915_private *dev_priv =
to_i915(crtc_state->base.crtc->dev);
@@ -1580,6 +1589,9 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
if (HAS_GMCH_DISPLAY(dev_priv))
return false;
+ if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
+ return false;
+
if (crtc_state->pipe_bpp <= 8*3)
return false;
@@ -1587,7 +1599,7 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
return false;
/*
- * HDMI 12bpc affects the clocks, so it's only possible
+ * HDMI deep color affects the clocks, so it's only possible
* when not cloning with other encoder types.
*/
if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
@@ -1602,16 +1614,24 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
if (crtc_state->ycbcr420) {
const struct drm_hdmi_info *hdmi = &info->hdmi;
- if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
+ if (bpc == 12 && !(hdmi->y420_dc_modes &
+ DRM_EDID_YCBCR420_DC_36))
+ return false;
+ else if (bpc == 10 && !(hdmi->y420_dc_modes &
+ DRM_EDID_YCBCR420_DC_30))
return false;
} else {
- if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36))
+ if (bpc == 12 && !(info->edid_hdmi_dc_modes &
+ DRM_EDID_HDMI_DC_36))
+ return false;
+ else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
+ DRM_EDID_HDMI_DC_30))
return false;
}
}
/* Display WA #1139: glk */
- if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
+ if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
crtc_state->base.adjusted_mode.htotal > 5460)
return false;
@@ -1621,7 +1641,8 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
static bool
intel_hdmi_ycbcr420_config(struct drm_connector *connector,
struct intel_crtc_state *config,
- int *clock_12bpc, int *clock_8bpc)
+ int *clock_12bpc, int *clock_10bpc,
+ int *clock_8bpc)
{
struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
@@ -1633,6 +1654,7 @@ intel_hdmi_ycbcr420_config(struct drm_connector *connector,
/* YCBCR420 TMDS rate requirement is half the pixel clock */
config->port_clock /= 2;
*clock_12bpc /= 2;
+ *clock_10bpc /= 2;
*clock_8bpc /= 2;
config->ycbcr420 = true;
@@ -1660,6 +1682,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
+ int clock_10bpc = clock_8bpc * 5 / 4;
int clock_12bpc = clock_8bpc * 3 / 2;
int desired_bpp;
bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
@@ -1683,12 +1706,14 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
pipe_config->pixel_multiplier = 2;
clock_8bpc *= 2;
+ clock_10bpc *= 2;
clock_12bpc *= 2;
}
if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
- &clock_12bpc, &clock_8bpc)) {
+ &clock_12bpc, &clock_10bpc,
+ &clock_8bpc)) {
DRM_ERROR("Can't support YCBCR420 output\n");
return false;
}
@@ -1706,18 +1731,25 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
}
/*
- * HDMI is either 12 or 8, so if the display lets 10bpc sneak
- * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
- * outputs. We also need to check that the higher clock still fits
- * within limits.
+ * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
+ * to check that the higher clock still fits within limits.
*/
- if (hdmi_12bpc_possible(pipe_config) &&
- hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK) {
+ if (hdmi_deep_color_possible(pipe_config, 12) &&
+ hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
+ true, force_dvi) == MODE_OK) {
DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
desired_bpp = 12*3;
/* Need to adjust the port link by 1.5x for 12bpc. */
pipe_config->port_clock = clock_12bpc;
+ } else if (hdmi_deep_color_possible(pipe_config, 10) &&
+ hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
+ true, force_dvi) == MODE_OK) {
+ DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
+ desired_bpp = 10 * 3;
+
+ /* Need to adjust the port link by 1.25x for 10bpc. */
+ pipe_config->port_clock = clock_10bpc;
} else {
DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
desired_bpp = 8*3;
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 17/24] drm/i915/icl: Add 10-bit support for hdmi
2018-05-22 0:25 ` [PATCH 17/24] drm/i915/icl: Add 10-bit support for hdmi Paulo Zanoni
@ 2018-06-20 16:55 ` Ville Syrjälä
0 siblings, 0 replies; 127+ messages in thread
From: Ville Syrjälä @ 2018-06-20 16:55 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Rodrigo Vivi
On Mon, May 21, 2018 at 05:25:51PM -0700, Paulo Zanoni wrote:
> From: "Sripada, Radhakrishna" <radhakrishna.sripada@intel.com>
>
> Starting Icelake silicon supports 10-bpc hdmi to support certain
> media workloads. Currently hdmi supports 8 and 12 bpc. Plumbed
> in support for 10 bit hdmi.
>
> Cc: James Ausmus <james.ausmus@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Still looks reasoanble to me so
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_hdmi.c | 64 +++++++++++++++++++++++++++++----------
> 1 file changed, 48 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 0ca4cc877520..53ac8bb85218 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1561,14 +1561,23 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
> /* check if we can do 8bpc */
> status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
>
> - /* if we can't do 8bpc we may still be able to do 12bpc */
> - if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi)
> - status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi);
> + if (hdmi->has_hdmi_sink && !force_dvi) {
> + /* if we can't do 8bpc we may still be able to do 12bpc */
> + if (status != MODE_OK && !HAS_GMCH_DISPLAY(dev_priv))
> + status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
> + true, force_dvi);
> +
> + /* if we can't do 8,12bpc we may still be able to do 10bpc */
> + if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
> + status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
> + true, force_dvi);
> + }
>
> return status;
> }
>
> -static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
> +static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
> + int bpc)
> {
> struct drm_i915_private *dev_priv =
> to_i915(crtc_state->base.crtc->dev);
> @@ -1580,6 +1589,9 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
> if (HAS_GMCH_DISPLAY(dev_priv))
> return false;
>
> + if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
> + return false;
> +
> if (crtc_state->pipe_bpp <= 8*3)
> return false;
>
> @@ -1587,7 +1599,7 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
> return false;
>
> /*
> - * HDMI 12bpc affects the clocks, so it's only possible
> + * HDMI deep color affects the clocks, so it's only possible
> * when not cloning with other encoder types.
> */
> if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
> @@ -1602,16 +1614,24 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
> if (crtc_state->ycbcr420) {
> const struct drm_hdmi_info *hdmi = &info->hdmi;
>
> - if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
> + if (bpc == 12 && !(hdmi->y420_dc_modes &
> + DRM_EDID_YCBCR420_DC_36))
> + return false;
> + else if (bpc == 10 && !(hdmi->y420_dc_modes &
> + DRM_EDID_YCBCR420_DC_30))
> return false;
> } else {
> - if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36))
> + if (bpc == 12 && !(info->edid_hdmi_dc_modes &
> + DRM_EDID_HDMI_DC_36))
> + return false;
> + else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
> + DRM_EDID_HDMI_DC_30))
> return false;
> }
> }
>
> /* Display WA #1139: glk */
> - if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
> + if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
> crtc_state->base.adjusted_mode.htotal > 5460)
> return false;
>
> @@ -1621,7 +1641,8 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
> static bool
> intel_hdmi_ycbcr420_config(struct drm_connector *connector,
> struct intel_crtc_state *config,
> - int *clock_12bpc, int *clock_8bpc)
> + int *clock_12bpc, int *clock_10bpc,
> + int *clock_8bpc)
> {
> struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
>
> @@ -1633,6 +1654,7 @@ intel_hdmi_ycbcr420_config(struct drm_connector *connector,
> /* YCBCR420 TMDS rate requirement is half the pixel clock */
> config->port_clock /= 2;
> *clock_12bpc /= 2;
> + *clock_10bpc /= 2;
> *clock_8bpc /= 2;
> config->ycbcr420 = true;
>
> @@ -1660,6 +1682,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
> struct intel_digital_connector_state *intel_conn_state =
> to_intel_digital_connector_state(conn_state);
> int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
> + int clock_10bpc = clock_8bpc * 5 / 4;
> int clock_12bpc = clock_8bpc * 3 / 2;
> int desired_bpp;
> bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
> @@ -1683,12 +1706,14 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
> pipe_config->pixel_multiplier = 2;
> clock_8bpc *= 2;
> + clock_10bpc *= 2;
> clock_12bpc *= 2;
> }
>
> if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
> if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
> - &clock_12bpc, &clock_8bpc)) {
> + &clock_12bpc, &clock_10bpc,
> + &clock_8bpc)) {
> DRM_ERROR("Can't support YCBCR420 output\n");
> return false;
> }
> @@ -1706,18 +1731,25 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
> }
>
> /*
> - * HDMI is either 12 or 8, so if the display lets 10bpc sneak
> - * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
> - * outputs. We also need to check that the higher clock still fits
> - * within limits.
> + * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
> + * to check that the higher clock still fits within limits.
> */
> - if (hdmi_12bpc_possible(pipe_config) &&
> - hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK) {
> + if (hdmi_deep_color_possible(pipe_config, 12) &&
> + hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
> + true, force_dvi) == MODE_OK) {
> DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
> desired_bpp = 12*3;
>
> /* Need to adjust the port link by 1.5x for 12bpc. */
> pipe_config->port_clock = clock_12bpc;
> + } else if (hdmi_deep_color_possible(pipe_config, 10) &&
> + hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
> + true, force_dvi) == MODE_OK) {
> + DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
> + desired_bpp = 10 * 3;
> +
> + /* Need to adjust the port link by 1.25x for 10bpc. */
> + pipe_config->port_clock = clock_10bpc;
> } else {
> DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
> desired_bpp = 8*3;
> --
> 2.14.3
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 18/24] drm/i915/icl: implement icl_digital_port_connected()
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (16 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 17/24] drm/i915/icl: Add 10-bit support for hdmi Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-06-19 22:28 ` Lucas De Marchi
2018-05-22 0:25 ` [PATCH 19/24] drm/i915/icl: store the port type for TC ports Paulo Zanoni
` (22 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
Do like the other functions and check for the ISR bits. We have plans
to add a few more checks in this code in the next patches, that's why
it's a little more verbose than it could be.
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 ++++
drivers/gpu/drm/i915/intel_dp.c | 57 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 49a72320e794..24308d4435f5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7055,6 +7055,7 @@ enum {
#define GEN11_TC3_HOTPLUG (1 << 18)
#define GEN11_TC2_HOTPLUG (1 << 17)
#define GEN11_TC1_HOTPLUG (1 << 16)
+#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG | \
GEN11_TC3_HOTPLUG | \
GEN11_TC2_HOTPLUG | \
@@ -7063,6 +7064,7 @@ enum {
#define GEN11_TBT3_HOTPLUG (1 << 2)
#define GEN11_TBT2_HOTPLUG (1 << 1)
#define GEN11_TBT1_HOTPLUG (1 << 0)
+#define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \
GEN11_TBT3_HOTPLUG | \
GEN11_TBT2_HOTPLUG | \
@@ -7486,6 +7488,9 @@ enum {
#define ICP_GMBUS (1 << 23)
#define ICP_DDIB_HOTPLUG (1 << 17)
#define ICP_DDIA_HOTPLUG (1 << 16)
+#define ICP_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 24))
+#define ICP_DDI_HOTPLUG(port) (1 << ((port) + 16))
+
#define ICP_SDE_DDI_MASK (ICP_DDIB_HOTPLUG | \
ICP_DDIA_HOTPLUG)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 102070940095..b477124717e7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4722,6 +4722,61 @@ static bool bxt_digital_port_connected(struct intel_encoder *encoder)
return I915_READ(GEN8_DE_PORT_ISR) & bit;
}
+static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *intel_dig_port)
+{
+ enum port port = intel_dig_port->base.port;
+
+ return I915_READ(ICP_SDE_ISR) & ICP_DDI_HOTPLUG(port);
+}
+
+static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *intel_dig_port)
+{
+ enum port port = intel_dig_port->base.port;
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+ u32 legacy_bit = ICP_TC_HOTPLUG(tc_port);
+ u32 typec_bit = GEN11_TC_HOTPLUG(tc_port);
+ u32 tbt_bit = GEN11_TBT_HOTPLUG(tc_port);
+ bool is_legacy = false, is_typec = false, is_tbt = false;
+ u32 cpu_isr;
+
+ if (I915_READ(ICP_SDE_ISR) & legacy_bit)
+ is_legacy = true;
+
+ cpu_isr = I915_READ(GEN11_DE_HPD_ISR);
+ if (cpu_isr & typec_bit)
+ is_typec = true;
+ if (cpu_isr & tbt_bit)
+ is_tbt = true;
+
+ WARN_ON(is_legacy + is_typec + is_tbt > 1);
+ if (!is_legacy && !is_typec && !is_tbt)
+ return false;
+
+ return true;
+}
+
+static bool icl_digital_port_connected(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_A:
+ case HPD_PORT_B:
+ return icl_combo_port_connected(dev_priv, dig_port);
+ case HPD_PORT_C:
+ case HPD_PORT_D:
+ case HPD_PORT_E:
+ case HPD_PORT_F:
+ return icl_tc_port_connected(dev_priv, dig_port);
+ default:
+ MISSING_CASE(encoder->hpd_pin);
+ return false;
+ }
+}
+
/*
* intel_digital_port_connected - is the specified port connected?
* @encoder: intel_encoder
@@ -4749,6 +4804,8 @@ bool intel_digital_port_connected(struct intel_encoder *encoder)
return bdw_digital_port_connected(encoder);
else if (IS_GEN9_LP(dev_priv))
return bxt_digital_port_connected(encoder);
+ else if (IS_ICELAKE(dev_priv))
+ return icl_digital_port_connected(encoder);
else
return spt_digital_port_connected(encoder);
}
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 18/24] drm/i915/icl: implement icl_digital_port_connected()
2018-05-22 0:25 ` [PATCH 18/24] drm/i915/icl: implement icl_digital_port_connected() Paulo Zanoni
@ 2018-06-19 22:28 ` Lucas De Marchi
2018-06-20 21:01 ` Paulo Zanoni
0 siblings, 1 reply; 127+ messages in thread
From: Lucas De Marchi @ 2018-06-19 22:28 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Rodrigo Vivi
On Mon, May 21, 2018 at 05:25:52PM -0700, Paulo Zanoni wrote:
> Do like the other functions and check for the ISR bits. We have plans
> to add a few more checks in this code in the next patches, that's why
> it's a little more verbose than it could be.
>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 ++++
> drivers/gpu/drm/i915/intel_dp.c | 57 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 49a72320e794..24308d4435f5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7055,6 +7055,7 @@ enum {
> #define GEN11_TC3_HOTPLUG (1 << 18)
> #define GEN11_TC2_HOTPLUG (1 << 17)
> #define GEN11_TC1_HOTPLUG (1 << 16)
> +#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
> #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG | \
> GEN11_TC3_HOTPLUG | \
> GEN11_TC2_HOTPLUG | \
> @@ -7063,6 +7064,7 @@ enum {
> #define GEN11_TBT3_HOTPLUG (1 << 2)
> #define GEN11_TBT2_HOTPLUG (1 << 1)
> #define GEN11_TBT1_HOTPLUG (1 << 0)
> +#define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
> #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \
> GEN11_TBT3_HOTPLUG | \
> GEN11_TBT2_HOTPLUG | \
> @@ -7486,6 +7488,9 @@ enum {
> #define ICP_GMBUS (1 << 23)
> #define ICP_DDIB_HOTPLUG (1 << 17)
> #define ICP_DDIA_HOTPLUG (1 << 16)
> +#define ICP_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 24))
> +#define ICP_DDI_HOTPLUG(port) (1 << ((port) + 16))
> +
>
> #define ICP_SDE_DDI_MASK (ICP_DDIB_HOTPLUG | \
> ICP_DDIA_HOTPLUG)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 102070940095..b477124717e7 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4722,6 +4722,61 @@ static bool bxt_digital_port_connected(struct intel_encoder *encoder)
> return I915_READ(GEN8_DE_PORT_ISR) & bit;
> }
>
> +static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
> + struct intel_digital_port *intel_dig_port)
> +{
> + enum port port = intel_dig_port->base.port;
> +
> + return I915_READ(ICP_SDE_ISR) & ICP_DDI_HOTPLUG(port);
> +}
> +
> +static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
> + struct intel_digital_port *intel_dig_port)
> +{
> + enum port port = intel_dig_port->base.port;
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + u32 legacy_bit = ICP_TC_HOTPLUG(tc_port);
> + u32 typec_bit = GEN11_TC_HOTPLUG(tc_port);
> + u32 tbt_bit = GEN11_TBT_HOTPLUG(tc_port);
> + bool is_legacy = false, is_typec = false, is_tbt = false;
> + u32 cpu_isr;
why *cpu*_isr? hpd_isr, isr or val would be better IMO
> +
> + if (I915_READ(ICP_SDE_ISR) & legacy_bit)
> + is_legacy = true;
> +
> + cpu_isr = I915_READ(GEN11_DE_HPD_ISR);
> + if (cpu_isr & typec_bit)
> + is_typec = true;
> + if (cpu_isr & tbt_bit)
> + is_tbt = true;
> +
> + WARN_ON(is_legacy + is_typec + is_tbt > 1);
> + if (!is_legacy && !is_typec && !is_tbt)
> + return false;
> +
> + return true;
you know you could "return is_legacy + is_typec + is_tbt;", right? you
are already doing it above, it may make sense to remove the extra
branch. Or not.
Feel free to disagree and push.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> +}
> +
> +static bool icl_digital_port_connected(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> +
> + switch (encoder->hpd_pin) {
> + case HPD_PORT_A:
> + case HPD_PORT_B:
> + return icl_combo_port_connected(dev_priv, dig_port);
> + case HPD_PORT_C:
> + case HPD_PORT_D:
> + case HPD_PORT_E:
> + case HPD_PORT_F:
> + return icl_tc_port_connected(dev_priv, dig_port);
> + default:
> + MISSING_CASE(encoder->hpd_pin);
> + return false;
> + }
> +}
> +
> /*
> * intel_digital_port_connected - is the specified port connected?
> * @encoder: intel_encoder
> @@ -4749,6 +4804,8 @@ bool intel_digital_port_connected(struct intel_encoder *encoder)
> return bdw_digital_port_connected(encoder);
> else if (IS_GEN9_LP(dev_priv))
> return bxt_digital_port_connected(encoder);
> + else if (IS_ICELAKE(dev_priv))
> + return icl_digital_port_connected(encoder);
> else
> return spt_digital_port_connected(encoder);
> }
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 18/24] drm/i915/icl: implement icl_digital_port_connected()
2018-06-19 22:28 ` Lucas De Marchi
@ 2018-06-20 21:01 ` Paulo Zanoni
0 siblings, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-06-20 21:01 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Rodrigo Vivi
Em Ter, 2018-06-19 às 15:28 -0700, Lucas De Marchi escreveu:
> On Mon, May 21, 2018 at 05:25:52PM -0700, Paulo Zanoni wrote:
> > Do like the other functions and check for the ISR bits. We have
> > plans
> > to add a few more checks in this code in the next patches, that's
> > why
> > it's a little more verbose than it could be.
> >
> > Cc: Animesh Manna <animesh.manna@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 5 ++++
> > drivers/gpu/drm/i915/intel_dp.c | 57
> > +++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 62 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 49a72320e794..24308d4435f5 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7055,6 +7055,7 @@ enum {
> > #define GEN11_TC3_HOTPLUG (1 << 18)
> > #define GEN11_TC2_HOTPLUG (1 << 17)
> > #define GEN11_TC1_HOTPLUG (1 << 16)
> > +#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port)
> > + 16))
> > #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLU
> > G | \
> > GEN11_TC3_HOTPLUG
> > | \
> > GEN11_TC2_HOTPLUG
> > | \
> > @@ -7063,6 +7064,7 @@ enum {
> > #define GEN11_TBT3_HOTPLUG (1 << 2)
> > #define GEN11_TBT2_HOTPLUG (1 << 1)
> > #define GEN11_TBT1_HOTPLUG (1 << 0)
> > +#define GEN11_TBT_HOTPLUG(tc_port) (1 <<
> > (tc_port))
> > #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTP
> > LUG | \
> > GEN11_TBT3_HOTPLU
> > G | \
> > GEN11_TBT2_HOTPLU
> > G | \
> > @@ -7486,6 +7488,9 @@ enum {
> > #define ICP_GMBUS (1 << 23)
> > #define ICP_DDIB_HOTPLUG (1 << 17)
> > #define ICP_DDIA_HOTPLUG (1 << 16)
> > +#define ICP_TC_HOTPLUG(tc_port) (1 << ((tc_port) +
> > 24))
> > +#define ICP_DDI_HOTPLUG(port) (1 << ((port) + 16))
> > +
> >
> > #define ICP_SDE_DDI_MASK (ICP_DDIB_HOTPLUG |
> > \
> > ICP_DDIA_HOTPLUG)
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 102070940095..b477124717e7 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4722,6 +4722,61 @@ static bool
> > bxt_digital_port_connected(struct intel_encoder *encoder)
> > return I915_READ(GEN8_DE_PORT_ISR) & bit;
> > }
> >
> > +static bool icl_combo_port_connected(struct drm_i915_private
> > *dev_priv,
> > + struct intel_digital_port
> > *intel_dig_port)
> > +{
> > + enum port port = intel_dig_port->base.port;
> > +
> > + return I915_READ(ICP_SDE_ISR) & ICP_DDI_HOTPLUG(port);
> > +}
> > +
> > +static bool icl_tc_port_connected(struct drm_i915_private
> > *dev_priv,
> > + struct intel_digital_port
> > *intel_dig_port)
> > +{
> > + enum port port = intel_dig_port->base.port;
> > + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> > + u32 legacy_bit = ICP_TC_HOTPLUG(tc_port);
> > + u32 typec_bit = GEN11_TC_HOTPLUG(tc_port);
> > + u32 tbt_bit = GEN11_TBT_HOTPLUG(tc_port);
> > + bool is_legacy = false, is_typec = false, is_tbt = false;
> > + u32 cpu_isr;
>
> why *cpu*_isr? hpd_isr, isr or val would be better IMO
Because we have 2 ISR registers we check, one is on the CPU and the
other is on the PCH. We just don't have a variable for pch_isr because
we don't need. Jusc alling it "isr" or "hpd_isr" would be misleading.
>
> > +
> > + if (I915_READ(ICP_SDE_ISR) & legacy_bit)
> > + is_legacy = true;
> > +
> > + cpu_isr = I915_READ(GEN11_DE_HPD_ISR);
> > + if (cpu_isr & typec_bit)
> > + is_typec = true;
> > + if (cpu_isr & tbt_bit)
> > + is_tbt = true;
> > +
> > + WARN_ON(is_legacy + is_typec + is_tbt > 1);
> > + if (!is_legacy && !is_typec && !is_tbt)
> > + return false;
> > +
> > + return true;
>
> you know you could "return is_legacy + is_typec + is_tbt;", right?
> you
> are already doing it above, it may make sense to remove the extra
> branch. Or not.
Because the next patch adds code between the "return false" and the
last return, so I'd have to change it there.
>
> Feel free to disagree and push.
>
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Thanks,
Paulo
>
>
> Lucas De Marchi
>
> > +}
> > +
> > +static bool icl_digital_port_connected(struct intel_encoder
> > *encoder)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(encoder-
> > >base.dev);
> > + struct intel_digital_port *dig_port =
> > enc_to_dig_port(&encoder->base);
> > +
> > + switch (encoder->hpd_pin) {
> > + case HPD_PORT_A:
> > + case HPD_PORT_B:
> > + return icl_combo_port_connected(dev_priv,
> > dig_port);
> > + case HPD_PORT_C:
> > + case HPD_PORT_D:
> > + case HPD_PORT_E:
> > + case HPD_PORT_F:
> > + return icl_tc_port_connected(dev_priv, dig_port);
> > + default:
> > + MISSING_CASE(encoder->hpd_pin);
> > + return false;
> > + }
> > +}
> > +
> > /*
> > * intel_digital_port_connected - is the specified port connected?
> > * @encoder: intel_encoder
> > @@ -4749,6 +4804,8 @@ bool intel_digital_port_connected(struct
> > intel_encoder *encoder)
> > return bdw_digital_port_connected(encoder);
> > else if (IS_GEN9_LP(dev_priv))
> > return bxt_digital_port_connected(encoder);
> > + else if (IS_ICELAKE(dev_priv))
> > + return icl_digital_port_connected(encoder);
> > else
> > return spt_digital_port_connected(encoder);
> > }
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 19/24] drm/i915/icl: store the port type for TC ports
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (17 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 18/24] drm/i915/icl: implement icl_digital_port_connected() Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-06-14 19:59 ` Rodrigo Vivi
2018-05-22 0:25 ` [PATCH 20/24] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP Paulo Zanoni
` (21 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
The type is detected based on the interrupt ISR bit. Once detected,
it's not supposed to be changed, so we have some sanity checks for
that.
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_display.h | 7 +++++++
drivers/gpu/drm/i915/intel_dp.c | 36 +++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index c88185ed7594..fcedc600706b 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -137,6 +137,13 @@ enum tc_port {
I915_MAX_TC_PORTS
};
+enum tc_port_type {
+ TC_PORT_UNKNOWN = 0,
+ TC_PORT_TYPEC,
+ TC_PORT_TBT,
+ TC_PORT_LEGACY,
+};
+
enum dpio_channel {
DPIO_CH0,
DPIO_CH1
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b477124717e7..f3d5b9eed625 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4730,6 +4730,38 @@ static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
return I915_READ(ICP_SDE_ISR) & ICP_DDI_HOTPLUG(port);
}
+static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *intel_dig_port,
+ bool is_legacy, bool is_typec, bool is_tbt)
+{
+ enum port port = intel_dig_port->base.port;
+ enum tc_port_type old_type = intel_dig_port->tc_type;
+ const char *type_str;
+
+ WARN_ON(is_legacy + is_typec + is_tbt != 1);
+
+ if (is_legacy) {
+ intel_dig_port->tc_type = TC_PORT_LEGACY;
+ type_str = "legacy";
+ } else if (is_typec) {
+ intel_dig_port->tc_type = TC_PORT_TYPEC;
+ type_str = "typec";
+ } else if (is_tbt) {
+ intel_dig_port->tc_type = TC_PORT_TBT;
+ type_str = "tbt";
+ } else {
+ return;
+ }
+
+ /* Types are not supposed to be changed at runtime. */
+ WARN_ON(old_type != TC_PORT_UNKNOWN &&
+ old_type != intel_dig_port->tc_type);
+
+ if (old_type != intel_dig_port->tc_type)
+ DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
+ type_str);
+}
+
static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
struct intel_digital_port *intel_dig_port)
{
@@ -4750,10 +4782,12 @@ static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
if (cpu_isr & tbt_bit)
is_tbt = true;
- WARN_ON(is_legacy + is_typec + is_tbt > 1);
if (!is_legacy && !is_typec && !is_tbt)
return false;
+ icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
+ is_tbt);
+
return true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a54232c270e1..8602f2e17d86 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1169,6 +1169,7 @@ struct intel_digital_port {
bool release_cl2_override;
uint8_t max_lanes;
enum intel_display_power_domain ddi_io_power_domain;
+ enum tc_port_type tc_type;
void (*write_infoframe)(struct drm_encoder *encoder,
const struct intel_crtc_state *crtc_state,
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 19/24] drm/i915/icl: store the port type for TC ports
2018-05-22 0:25 ` [PATCH 19/24] drm/i915/icl: store the port type for TC ports Paulo Zanoni
@ 2018-06-14 19:59 ` Rodrigo Vivi
2018-06-21 0:37 ` Paulo Zanoni
0 siblings, 1 reply; 127+ messages in thread
From: Rodrigo Vivi @ 2018-06-14 19:59 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Mon, May 21, 2018 at 05:25:53PM -0700, Paulo Zanoni wrote:
> The type is detected based on the interrupt ISR bit. Once detected,
> it's not supposed to be changed, so we have some sanity checks for
> that.
>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.h | 7 +++++++
> drivers/gpu/drm/i915/intel_dp.c | 36 +++++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 3 files changed, 43 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index c88185ed7594..fcedc600706b 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -137,6 +137,13 @@ enum tc_port {
> I915_MAX_TC_PORTS
> };
>
> +enum tc_port_type {
> + TC_PORT_UNKNOWN = 0,
> + TC_PORT_TYPEC,
> + TC_PORT_TBT,
> + TC_PORT_LEGACY,
> +};
> +
> enum dpio_channel {
> DPIO_CH0,
> DPIO_CH1
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b477124717e7..f3d5b9eed625 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4730,6 +4730,38 @@ static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
> return I915_READ(ICP_SDE_ISR) & ICP_DDI_HOTPLUG(port);
> }
>
> +static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
> + struct intel_digital_port *intel_dig_port,
> + bool is_legacy, bool is_typec, bool is_tbt)
> +{
> + enum port port = intel_dig_port->base.port;
> + enum tc_port_type old_type = intel_dig_port->tc_type;
> + const char *type_str;
> +
> + WARN_ON(is_legacy + is_typec + is_tbt != 1);
> +
> + if (is_legacy) {
> + intel_dig_port->tc_type = TC_PORT_LEGACY;
> + type_str = "legacy";
> + } else if (is_typec) {
> + intel_dig_port->tc_type = TC_PORT_TYPEC;
> + type_str = "typec";
> + } else if (is_tbt) {
> + intel_dig_port->tc_type = TC_PORT_TBT;
> + type_str = "tbt";
> + } else {
> + return;
> + }
> +
> + /* Types are not supposed to be changed at runtime. */
> + WARN_ON(old_type != TC_PORT_UNKNOWN &&
> + old_type != intel_dig_port->tc_type);
> +
> + if (old_type != intel_dig_port->tc_type)
> + DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
> + type_str);
> +}
> +
> static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
> struct intel_digital_port *intel_dig_port)
> {
> @@ -4750,10 +4782,12 @@ static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
> if (cpu_isr & tbt_bit)
> is_tbt = true;
>
> - WARN_ON(is_legacy + is_typec + is_tbt > 1);
> if (!is_legacy && !is_typec && !is_tbt)
> return false;
>
> + icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
> + is_tbt);
I really don't like the new chain of functions this patch here starts.
for all other platforms the function is_port_connect returns true or false
immediately. For this TC/TBT design this start a new chain that not only
check if it is connected but it also updates the status... and all in a
chain of function calls....
I didn't check the code now actually. I just remember for one rebase
change that I did a while ago and saw these patches. Unfortunately I
had no better idea on when exactly call the current status when I looked.
Probably a totally separated function that is called outside right always
along with is_port_connected
update_tc_port()
is_port_connected()
just to keep is_port_connect as simple as it is on any other platform
and this new meaning of status update in a separated block.
Thanks,
Rodrigo.
> +
> return true;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index a54232c270e1..8602f2e17d86 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1169,6 +1169,7 @@ struct intel_digital_port {
> bool release_cl2_override;
> uint8_t max_lanes;
> enum intel_display_power_domain ddi_io_power_domain;
> + enum tc_port_type tc_type;
>
> void (*write_infoframe)(struct drm_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 19/24] drm/i915/icl: store the port type for TC ports
2018-06-14 19:59 ` Rodrigo Vivi
@ 2018-06-21 0:37 ` Paulo Zanoni
0 siblings, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-06-21 0:37 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
Em Qui, 2018-06-14 às 12:59 -0700, Rodrigo Vivi escreveu:
> On Mon, May 21, 2018 at 05:25:53PM -0700, Paulo Zanoni wrote:
> > The type is detected based on the interrupt ISR bit. Once detected,
> > it's not supposed to be changed, so we have some sanity checks for
> > that.
> >
> > Cc: Animesh Manna <animesh.manna@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.h | 7 +++++++
> > drivers/gpu/drm/i915/intel_dp.c | 36
> > +++++++++++++++++++++++++++++++++++-
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > 3 files changed, 43 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > b/drivers/gpu/drm/i915/intel_display.h
> > index c88185ed7594..fcedc600706b 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -137,6 +137,13 @@ enum tc_port {
> > I915_MAX_TC_PORTS
> > };
> >
> > +enum tc_port_type {
> > + TC_PORT_UNKNOWN = 0,
> > + TC_PORT_TYPEC,
> > + TC_PORT_TBT,
> > + TC_PORT_LEGACY,
> > +};
> > +
> > enum dpio_channel {
> > DPIO_CH0,
> > DPIO_CH1
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index b477124717e7..f3d5b9eed625 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4730,6 +4730,38 @@ static bool icl_combo_port_connected(struct
> > drm_i915_private *dev_priv,
> > return I915_READ(ICP_SDE_ISR) & ICP_DDI_HOTPLUG(port);
> > }
> >
> > +static void icl_update_tc_port_type(struct drm_i915_private
> > *dev_priv,
> > + struct intel_digital_port
> > *intel_dig_port,
> > + bool is_legacy, bool is_typec,
> > bool is_tbt)
> > +{
> > + enum port port = intel_dig_port->base.port;
> > + enum tc_port_type old_type = intel_dig_port->tc_type;
> > + const char *type_str;
> > +
> > + WARN_ON(is_legacy + is_typec + is_tbt != 1);
> > +
> > + if (is_legacy) {
> > + intel_dig_port->tc_type = TC_PORT_LEGACY;
> > + type_str = "legacy";
> > + } else if (is_typec) {
> > + intel_dig_port->tc_type = TC_PORT_TYPEC;
> > + type_str = "typec";
> > + } else if (is_tbt) {
> > + intel_dig_port->tc_type = TC_PORT_TBT;
> > + type_str = "tbt";
> > + } else {
> > + return;
> > + }
> > +
> > + /* Types are not supposed to be changed at runtime. */
> > + WARN_ON(old_type != TC_PORT_UNKNOWN &&
> > + old_type != intel_dig_port->tc_type);
> > +
> > + if (old_type != intel_dig_port->tc_type)
> > + DRM_DEBUG_KMS("Port %c has TC type %s\n",
> > port_name(port),
> > + type_str);
> > +}
> > +
> > static bool icl_tc_port_connected(struct drm_i915_private
> > *dev_priv,
> > struct intel_digital_port
> > *intel_dig_port)
> > {
> > @@ -4750,10 +4782,12 @@ static bool icl_tc_port_connected(struct
> > drm_i915_private *dev_priv,
> > if (cpu_isr & tbt_bit)
> > is_tbt = true;
> >
> > - WARN_ON(is_legacy + is_typec + is_tbt > 1);
> > if (!is_legacy && !is_typec && !is_tbt)
> > return false;
> >
> > + icl_update_tc_port_type(dev_priv, intel_dig_port,
> > is_legacy, is_typec,
> > + is_tbt);
>
> I really don't like the new chain of functions this patch here
> starts.
I don't like it either, but the hardware changed in a way that is
different from every previous platform.
>
> for all other platforms the function is_port_connect returns true or
> false
> immediately. For this TC/TBT design this start a new chain that not
> only
> check if it is connected but it also updates the status... and all in
> a
> chain of function calls....
We have to figure out the port type (in case it's tc) during the
hotplug anyway since that's part of the hotplug sequence, for the
DFLEXDP* dance. If we keep passing it as a local variable and opt to do
later, we'll have to re-read the ISR bits anyway and we'll have to do
it right after. I don't see how that would actually help anything: it
could only increase the risk of de-sync when functions get moved
around.
>
> I didn't check the code now actually. I just remember for one rebase
> change that I did a while ago and saw these patches. Unfortunately I
> had no better idea on when exactly call the current status when I
> looked.
>
> Probably a totally separated function that is called outside right
> always
> along with is_port_connected
>
> update_tc_port()
> is_port_connected()
This would need to be in the inverse order and it would pretty much
just re-read the ISR bits again. Doable, but wouldn't solve the main
problem you complain about: is_connected() would still do a lot more
than just reading the ISR bits, in fact it would look exactly the same
as right now except it wouldn't set dig_port->tc_type.
>
> just to keep is_port_connect as simple as it is on any other platform
> and this new meaning of status update in a separated block.
This is not possible due to the DFLEXDP* dance. I think you're mad at
the DFLEXDP* dance and is unleashing your rage at poor dig_port-
>tc_type.
Please read the rest of the series and tell me what you think should
really be done here. Open review comments like "this is bad but I
haven't read the other patches in order to formulate a proper
suggestion" don't help very much.
Thanks,
Paulo
>
> Thanks,
> Rodrigo.
>
> > +
> > return true;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index a54232c270e1..8602f2e17d86 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1169,6 +1169,7 @@ struct intel_digital_port {
> > bool release_cl2_override;
> > uint8_t max_lanes;
> > enum intel_display_power_domain ddi_io_power_domain;
> > + enum tc_port_type tc_type;
> >
> > void (*write_infoframe)(struct drm_encoder *encoder,
> > const struct intel_crtc_state
> > *crtc_state,
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 20/24] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (18 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 19/24] drm/i915/icl: store the port type for TC ports Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-06-21 22:04 ` Srivatsa, Anusha
2018-05-22 0:25 ` [PATCH 21/24] drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI Paulo Zanoni
` (20 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Implement the DFLEXDPPMS/DFLEXDPCSSS dance for DisplayPort. These
functions need to be called during HPD assert/deassert, but due to how
our driver works it's much simpler if we always call them when
icl_digital_port_connected() is called, which means we won't call them
exactly once per HPD event. This should also cover the connected boot
case, whatever the BIOS does.
We're still missing the HDMI case, which should be implemented in the
next patch.
Also notice that, today, the BSpec pages for the DFLEXDPPMS and
DFLEXDPCSSS registers are wrong, so you should only trust the flows
described by the "Gen11 TypeC Programming" page in our spec.
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 +++++
drivers/gpu/drm/i915/intel_dp.c | 57 ++++++++++++++++++++++++++++++++++++++++-
2 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24308d4435f5..42cbace4c61e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10027,4 +10027,10 @@ enum skl_power_gate {
_ICL_PHY_MISC_B)
#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
+#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
+#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
+
+#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
+#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f3d5b9eed625..f25f871e7c22 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4762,6 +4762,56 @@ static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
type_str);
}
+static bool icl_tc_phy_mode_status_connect(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *dig_port)
+{
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+ u32 val;
+
+ if (dig_port->tc_type != TC_PORT_LEGACY &&
+ dig_port->tc_type != TC_PORT_TYPEC)
+ return true;
+
+ val = I915_READ(PORT_TX_DFLEXDPPMS);
+ if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
+ DRM_ERROR("DP PHY for TC port %d not ready\n", tc_port);
+ return false;
+ }
+
+ /*
+ * This function may be called many times in a row without an HPD event
+ * in between, so try to avoid the write when we can.
+ */
+ val = I915_READ(PORT_TX_DFLEXDPCSSS);
+ if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
+ val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
+ I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
+ }
+
+ return true;
+}
+
+static void icl_tc_phy_mode_status_disconnect(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *dig_port)
+{
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+ u32 val;
+
+ if (dig_port->tc_type != TC_PORT_LEGACY &&
+ dig_port->tc_type != TC_PORT_TYPEC)
+ return;
+
+ /*
+ * This function may be called many times in a row without an HPD event
+ * in between, so try to avoid the write when we can.
+ */
+ val = I915_READ(PORT_TX_DFLEXDPCSSS);
+ if (val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)) {
+ val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
+ I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
+ }
+}
+
static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
struct intel_digital_port *intel_dig_port)
{
@@ -4782,12 +4832,17 @@ static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
if (cpu_isr & tbt_bit)
is_tbt = true;
- if (!is_legacy && !is_typec && !is_tbt)
+ if (!is_legacy && !is_typec && !is_tbt) {
+ icl_tc_phy_mode_status_disconnect(dev_priv, intel_dig_port);
return false;
+ }
icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
is_tbt);
+ if (!icl_tc_phy_mode_status_connect(dev_priv, intel_dig_port))
+ return false;
+
return true;
}
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 20/24] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
2018-05-22 0:25 ` [PATCH 20/24] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP Paulo Zanoni
@ 2018-06-21 22:04 ` Srivatsa, Anusha
2018-07-11 21:28 ` Paulo Zanoni
0 siblings, 1 reply; 127+ messages in thread
From: Srivatsa, Anusha @ 2018-06-21 22:04 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org; +Cc: Zanoni, Paulo R
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Paulo Zanoni
>Sent: Monday, May 21, 2018 5:26 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Zanoni, Paulo R <paulo.r.zanoni@intel.com>
>Subject: [Intel-gfx] [PATCH 20/24] drm/i915/icl: implement the tc/legacy HPD
>{dis, }connect flow for DP
>
>Implement the DFLEXDPPMS/DFLEXDPCSSS dance for DisplayPort. These
>functions need to be called during HPD assert/deassert, but due to how our driver
>works it's much simpler if we always call them when
>icl_digital_port_connected() is called, which means we won't call them exactly
>once per HPD event. This should also cover the connected boot case, whatever
>the BIOS does.
>
>We're still missing the HDMI case, which should be implemented in the next
>patch.
>
>Also notice that, today, the BSpec pages for the DFLEXDPPMS and DFLEXDPCSSS
>registers are wrong, so you should only trust the flows described by the "Gen11
>TypeC Programming" page in our spec.
>
>Cc: Animesh Manna <animesh.manna@intel.com>
>Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 6 +++++ drivers/gpu/drm/i915/intel_dp.c |
>57 ++++++++++++++++++++++++++++++++++++++++-
> 2 files changed, 62 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 24308d4435f5..42cbace4c61e 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -10027,4 +10027,10 @@ enum skl_power_gate {
> _ICL_PHY_MISC_B)
> #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
>
>+#define PORT_TX_DFLEXDPPMS
> _MMIO(0x163890)
>+#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 <<
>(tc_port))
>+
>+#define PORT_TX_DFLEXDPCSSS
> _MMIO(0x163894)
>+#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
>+
> #endif /* _I915_REG_H_ */
>diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>index f3d5b9eed625..f25f871e7c22 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -4762,6 +4762,56 @@ static void icl_update_tc_port_type(struct
>drm_i915_private *dev_priv,
> type_str);
> }
>
>+static bool icl_tc_phy_mode_status_connect(struct drm_i915_private *dev_priv,
>+ struct intel_digital_port *dig_port) {
>+ enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
>+ u32 val;
>+
>+ if (dig_port->tc_type != TC_PORT_LEGACY &&
>+ dig_port->tc_type != TC_PORT_TYPEC)
>+ return true;
Shouldn’t this return false?
>+ val = I915_READ(PORT_TX_DFLEXDPPMS);
>+ if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
>+ DRM_ERROR("DP PHY for TC port %d not ready\n", tc_port);
>+ return false;
>+ }
>+
>+ /*
>+ * This function may be called many times in a row without an HPD event
>+ * in between, so try to avoid the write when we can.
>+ */
>+ val = I915_READ(PORT_TX_DFLEXDPCSSS);
>+ if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
>+ val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
>+ I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
>+ }
>+
>+ return true;
>+}
>+
>+static void icl_tc_phy_mode_status_disconnect(struct drm_i915_private
>*dev_priv,
>+ struct intel_digital_port *dig_port) {
>+ enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
>+ u32 val;
>+
>+ if (dig_port->tc_type != TC_PORT_LEGACY &&
>+ dig_port->tc_type != TC_PORT_TYPEC)
>+ return;
>+
>+ /*
>+ * This function may be called many times in a row without an HPD event
>+ * in between, so try to avoid the write when we can.
>+ */
So, in the sequences to enable, it does tell that enabling suitable aux power domains is optional. But in the disable sequence, disable AUX_PWR is mentioned as a non-optional step.
In which case it has to be before we set DFLEXDPCSSS register to 0.
Is it being addressed in another patch?
The rest of the patch looks good.
Anusha
>+ val = I915_READ(PORT_TX_DFLEXDPCSSS);
>+ if (val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)) {
>+ val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
>+ I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
>+ }
>+}
>+
> static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
> struct intel_digital_port *intel_dig_port) { @@
>-4782,12 +4832,17 @@ static bool icl_tc_port_connected(struct
>drm_i915_private *dev_priv,
> if (cpu_isr & tbt_bit)
> is_tbt = true;
>
>- if (!is_legacy && !is_typec && !is_tbt)
>+ if (!is_legacy && !is_typec && !is_tbt) {
>+ icl_tc_phy_mode_status_disconnect(dev_priv, intel_dig_port);
> return false;
>+ }
>
> icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
> is_tbt);
>
>+ if (!icl_tc_phy_mode_status_connect(dev_priv, intel_dig_port))
>+ return false;
>+
> return true;
> }
>
>--
>2.14.3
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 20/24] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
2018-06-21 22:04 ` Srivatsa, Anusha
@ 2018-07-11 21:28 ` Paulo Zanoni
0 siblings, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-07-11 21:28 UTC (permalink / raw)
To: Srivatsa, Anusha, intel-gfx@lists.freedesktop.org
Em Qui, 2018-06-21 às 15:04 -0700, Srivatsa, Anusha escreveu:
> > -----Original Message-----
> > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On
> > Behalf Of
> > Paulo Zanoni
> > Sent: Monday, May 21, 2018 5:26 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Zanoni, Paulo R <paulo.r.zanoni@intel.com>
> > Subject: [Intel-gfx] [PATCH 20/24] drm/i915/icl: implement the
> > tc/legacy HPD
> > {dis, }connect flow for DP
> >
> > Implement the DFLEXDPPMS/DFLEXDPCSSS dance for DisplayPort. These
> > functions need to be called during HPD assert/deassert, but due to
> > how our driver
> > works it's much simpler if we always call them when
> > icl_digital_port_connected() is called, which means we won't call
> > them exactly
> > once per HPD event. This should also cover the connected boot case,
> > whatever
> > the BIOS does.
> >
> > We're still missing the HDMI case, which should be implemented in
> > the next
> > patch.
> >
> > Also notice that, today, the BSpec pages for the DFLEXDPPMS and
> > DFLEXDPCSSS
> > registers are wrong, so you should only trust the flows described
> > by the "Gen11
> > TypeC Programming" page in our spec.
> >
> > Cc: Animesh Manna <animesh.manna@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 6
> > +++++ drivers/gpu/drm/i915/intel_dp.c |
> > 57 ++++++++++++++++++++++++++++++++++++++++-
> > 2 files changed, 62 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 24308d4435f5..42cbace4c61e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10027,4 +10027,10 @@ enum skl_power_gate {
> > _ICL_PHY_MISC_B)
> > #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
> >
> > +#define PORT_TX_DFLEXDPPMS
> > _MMIO(0x163890)
> > +#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1
> > <<
> > (tc_port))
> > +
> > +#define PORT_TX_DFLEXDPCSSS
> > _MMIO(0x163894)
> > +#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1
> > << (tc_port))
> > +
> > #endif /* _I915_REG_H_ */
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index f3d5b9eed625..f25f871e7c22 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4762,6 +4762,56 @@ static void icl_update_tc_port_type(struct
> > drm_i915_private *dev_priv,
> > type_str);
> > }
> >
> > +static bool icl_tc_phy_mode_status_connect(struct drm_i915_private
> > *dev_priv,
> > + struct
> > intel_digital_port *dig_port) {
> > + enum tc_port tc_port = intel_port_to_tc(dev_priv,
> > dig_port->base.port);
> > + u32 val;
> > +
> > + if (dig_port->tc_type != TC_PORT_LEGACY &&
> > + dig_port->tc_type != TC_PORT_TYPEC)
> > + return true;
>
> Shouldn’t this return false?
Types that don't need to run this sequence can be considered connected,
so we return true.
>
> > + val = I915_READ(PORT_TX_DFLEXDPPMS);
> > + if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
> > + DRM_ERROR("DP PHY for TC port %d not ready\n",
> > tc_port);
> > + return false;
> > + }
> > +
> > + /*
> > + * This function may be called many times in a row without
> > an HPD event
> > + * in between, so try to avoid the write when we can.
> > + */
> > + val = I915_READ(PORT_TX_DFLEXDPCSSS);
> > + if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
> > + val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
> > + I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
> > + }
> > +
> > + return true;
> > +}
> > +
> > +static void icl_tc_phy_mode_status_disconnect(struct
> > drm_i915_private
> > *dev_priv,
> > + struct
> > intel_digital_port *dig_port) {
> > + enum tc_port tc_port = intel_port_to_tc(dev_priv,
> > dig_port->base.port);
> > + u32 val;
> > +
> > + if (dig_port->tc_type != TC_PORT_LEGACY &&
> > + dig_port->tc_type != TC_PORT_TYPEC)
> > + return;
> > +
> > + /*
> > + * This function may be called many times in a row without
> > an HPD event
> > + * in between, so try to avoid the write when we can.
> > + */
>
> So, in the sequences to enable, it does tell that enabling suitable
> aux power domains is optional. But in the disable sequence, disable
> AUX_PWR is mentioned as a non-optional step.
> In which case it has to be before we set DFLEXDPCSSS register to 0.
>
> Is it being addressed in another patch?
It should be disabled here because we're not using the port anymore at
this point.
>
> The rest of the patch looks good.
>
> Anusha
>
> > + val = I915_READ(PORT_TX_DFLEXDPCSSS);
> > + if (val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)) {
> > + val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
> > + I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
> > + }
> > +}
> > +
> > static bool icl_tc_port_connected(struct drm_i915_private
> > *dev_priv,
> > struct intel_digital_port
> > *intel_dig_port) { @@
> > -4782,12 +4832,17 @@ static bool icl_tc_port_connected(struct
> > drm_i915_private *dev_priv,
> > if (cpu_isr & tbt_bit)
> > is_tbt = true;
> >
> > - if (!is_legacy && !is_typec && !is_tbt)
> > + if (!is_legacy && !is_typec && !is_tbt) {
> > + icl_tc_phy_mode_status_disconnect(dev_priv,
> > intel_dig_port);
> > return false;
> > + }
> >
> > icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy,
> > is_typec,
> > is_tbt);
> >
> > + if (!icl_tc_phy_mode_status_connect(dev_priv,
> > intel_dig_port))
> > + return false;
> > +
> > return true;
> > }
> >
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 21/24] drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (19 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 20/24] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-06-26 11:41 ` Mika Kahola
2018-05-22 0:25 ` [PATCH 22/24] drm/i915/icl: Update FIA supported lane count for hpd Paulo Zanoni
` (19 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
Just like DP, HDMI needs to implement these flows. The side effect is
that HDMI is now going to rely on the ISR bits, just like DP.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[Rodrigo: non-trivial rebase.]
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 53ac8bb85218..75f02a0e7d39 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1893,21 +1893,26 @@ intel_hdmi_set_edid(struct drm_connector *connector)
static enum drm_connector_status
intel_hdmi_detect(struct drm_connector *connector, bool force)
{
- enum drm_connector_status status;
+ enum drm_connector_status status = connector_status_disconnected;
struct drm_i915_private *dev_priv = to_i915(connector->dev);
+ struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
+ struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
connector->base.id, connector->name);
intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
+ if (IS_ICELAKE(dev_priv) &&
+ !intel_digital_port_connected(encoder))
+ goto out;
+
intel_hdmi_unset_edid(connector);
if (intel_hdmi_set_edid(connector))
status = connector_status_connected;
- else
- status = connector_status_disconnected;
+out:
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
return status;
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 21/24] drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
2018-05-22 0:25 ` [PATCH 21/24] drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI Paulo Zanoni
@ 2018-06-26 11:41 ` Mika Kahola
0 siblings, 0 replies; 127+ messages in thread
From: Mika Kahola @ 2018-06-26 11:41 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: Rodrigo Vivi
the patch looks fine to me.
On Mon, 2018-05-21 at 17:25 -0700, Paulo Zanoni wrote:
> Just like DP, HDMI needs to implement these flows. The side effect is
> that HDMI is now going to rely on the ISR bits, just like DP.
>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> [Rodrigo: non-trivial rebase.]
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_hdmi.c | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 53ac8bb85218..75f02a0e7d39 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1893,21 +1893,26 @@ intel_hdmi_set_edid(struct drm_connector
> *connector)
> static enum drm_connector_status
> intel_hdmi_detect(struct drm_connector *connector, bool force)
> {
> - enum drm_connector_status status;
> + enum drm_connector_status status =
> connector_status_disconnected;
> struct drm_i915_private *dev_priv = to_i915(connector->dev);
> + struct intel_hdmi *intel_hdmi =
> intel_attached_hdmi(connector);
> + struct intel_encoder *encoder =
> &hdmi_to_dig_port(intel_hdmi)->base;
>
> DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
> connector->base.id, connector->name);
>
> intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
>
> + if (IS_ICELAKE(dev_priv) &&
> + !intel_digital_port_connected(encoder))
> + goto out;
> +
> intel_hdmi_unset_edid(connector);
>
> if (intel_hdmi_set_edid(connector))
> status = connector_status_connected;
> - else
> - status = connector_status_disconnected;
>
> +out:
> intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
>
> return status;
--
Mika Kahola - Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 22/24] drm/i915/icl: Update FIA supported lane count for hpd.
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (20 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 21/24] drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-06-21 22:45 ` Srivatsa, Anusha
2018-05-22 0:25 ` [PATCH 23/24] drm/i915/icl: program MG_DP_MODE Paulo Zanoni
` (18 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Animesh Manna <animesh.manna@intel.com>
In ICL, Flexible IO Adapter (FIA) muxes data and clocks of USB 3.1,
tbt and display controller. In DP alt mode FIA configure the
number of lanes and will be used apart from DPCD read to calculate max
available lanes for DP enablement.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
[Paulo: significant rewrite of the patch.]
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
drivers/gpu/drm/i915/intel_dp.c | 33 ++++++++++++++++++++++++++++++++-
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 42cbace4c61e..2a501e7590bf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10033,4 +10033,9 @@ enum skl_power_gate {
#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
+#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
+#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
+#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
+#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f25f871e7c22..a883a3264e56 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -176,14 +176,45 @@ static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
return intel_dp->common_rates[intel_dp->num_common_rates - 1];
}
+static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+ u32 lane_info;
+
+ if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
+ return 4;
+
+ lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
+ DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
+ DP_LANE_ASSIGNMENT_SHIFT(tc_port);
+
+ switch (lane_info) {
+ default:
+ MISSING_CASE(lane_info);
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ return 1;
+ case 3:
+ case 12:
+ return 2;
+ case 15:
+ return 4;
+ }
+}
+
/* Theoretical max between source and sink */
static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
int source_max = intel_dig_port->max_lanes;
int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
+ int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
- return min(source_max, sink_max);
+ return min3(source_max, sink_max, fia_max);
}
int intel_dp_max_lane_count(struct intel_dp *intel_dp)
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 22/24] drm/i915/icl: Update FIA supported lane count for hpd.
2018-05-22 0:25 ` [PATCH 22/24] drm/i915/icl: Update FIA supported lane count for hpd Paulo Zanoni
@ 2018-06-21 22:45 ` Srivatsa, Anusha
0 siblings, 0 replies; 127+ messages in thread
From: Srivatsa, Anusha @ 2018-06-21 22:45 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org; +Cc: Zanoni, Paulo R
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Paulo Zanoni
>Sent: Monday, May 21, 2018 5:26 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Zanoni, Paulo R <paulo.r.zanoni@intel.com>
>Subject: [Intel-gfx] [PATCH 22/24] drm/i915/icl: Update FIA supported lane count
>for hpd.
>
>From: Animesh Manna <animesh.manna@intel.com>
>
>In ICL, Flexible IO Adapter (FIA) muxes data and clocks of USB 3.1, tbt and display
>controller. In DP alt mode FIA configure the number of lanes and will be used
>apart from DPCD read to calculate max available lanes for DP enablement.
>
>Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>[Paulo: significant rewrite of the patch.]
>Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Looks good.
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_dp.c |
>33 ++++++++++++++++++++++++++++++++-
> 2 files changed, 37 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 42cbace4c61e..2a501e7590bf 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -10033,4 +10033,9 @@ enum skl_power_gate {
> #define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
> #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
>
>+#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
>+#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
>+#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
>+#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
>+
> #endif /* _I915_REG_H_ */
>diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>index f25f871e7c22..a883a3264e56 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -176,14 +176,45 @@ static int intel_dp_max_common_rate(struct intel_dp
>*intel_dp)
> return intel_dp->common_rates[intel_dp->num_common_rates - 1]; }
>
>+static int intel_dp_get_fia_supported_lane_count(struct intel_dp
>+*intel_dp) {
>+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>+ enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
>+ u32 lane_info;
>+
>+ if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
>+ return 4;
>+
>+ lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
>+ DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
>+ DP_LANE_ASSIGNMENT_SHIFT(tc_port);
>+
>+ switch (lane_info) {
>+ default:
>+ MISSING_CASE(lane_info);
>+ case 1:
>+ case 2:
>+ case 4:
>+ case 8:
>+ return 1;
>+ case 3:
>+ case 12:
>+ return 2;
>+ case 15:
>+ return 4;
>+ }
>+}
>+
> /* Theoretical max between source and sink */ static int
>intel_dp_max_common_lane_count(struct intel_dp *intel_dp) {
> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> int source_max = intel_dig_port->max_lanes;
> int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
>+ int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
>
>- return min(source_max, sink_max);
>+ return min3(source_max, sink_max, fia_max);
> }
>
> int intel_dp_max_lane_count(struct intel_dp *intel_dp)
>--
>2.14.3
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 23/24] drm/i915/icl: program MG_DP_MODE
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (21 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 22/24] drm/i915/icl: Update FIA supported lane count for hpd Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-06-19 12:59 ` Maarten Lankhorst
2018-05-22 0:25 ` [PATCH 24/24] drm/i915/icl: toggle PHY clock gating around link training Paulo Zanoni
` (17 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Dhinakaran Pandiyan
Programming this register is part of the Enable Sequence for
DisplayPort on ICL. Do as the spec says.
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
drivers/gpu/drm/i915/intel_dp.c | 66 ++++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 1 +
4 files changed, 84 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2a501e7590bf..2ccae6c3e905 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1943,6 +1943,21 @@ enum i915_power_well_id {
#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
+#define _MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
+#define _MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
+#define _MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
+#define _MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
+#define _MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
+#define _MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
+#define _MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
+#define _MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
+#define MG_DP_MODE(port, ln) \
+ _ICL_MG_PHY_PORT_LN(port, ln, _MG_DP_MODE_LN0_ACU_PORT1, \
+ _MG_DP_MODE_LN0_ACU_PORT2, \
+ _MG_DP_MODE_LN1_ACU_PORT1)
+#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
+#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
+
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
*/
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1d5bfec57c33..c3c29565b863 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2667,6 +2667,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
+ icl_program_mg_dp_mode(intel_dp);
+
if (IS_ICELAKE(dev_priv))
icl_ddi_vswing_sequence(encoder, level, encoder->type);
else if (IS_CANNONLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a883a3264e56..1228d6185f76 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -229,6 +229,72 @@ intel_dp_link_required(int pixel_clock, int bpp)
return DIV_ROUND_UP(pixel_clock * bpp, 8);
}
+void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+ enum port port = intel_dig_port->base.port;
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+ u32 ln0, ln1, lane_info;
+
+ if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
+ return;
+
+ ln0 = I915_READ(MG_DP_MODE(port, 0));
+ ln1 = I915_READ(MG_DP_MODE(port, 1));
+
+ switch (intel_dig_port->tc_type) {
+ case TC_PORT_TYPEC:
+ ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
+ ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
+
+ lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
+ DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
+ DP_LANE_ASSIGNMENT_SHIFT(tc_port);
+
+ switch (lane_info) {
+ case 0x1:
+ case 0x4:
+ break;
+ case 0x2:
+ ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
+ break;
+ case 0x3:
+ ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
+ MG_DP_MODE_CFG_DP_X2_MODE;
+ break;
+ case 0x8:
+ ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
+ break;
+ case 0xC:
+ ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
+ MG_DP_MODE_CFG_DP_X2_MODE;
+ break;
+ case 0xF:
+ ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
+ MG_DP_MODE_CFG_DP_X2_MODE;
+ ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
+ MG_DP_MODE_CFG_DP_X2_MODE;
+ break;
+ default:
+ MISSING_CASE(lane_info);
+ }
+ break;
+
+ case TC_PORT_LEGACY:
+ ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
+ ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
+ break;
+
+ default:
+ MISSING_CASE(intel_dig_port->tc_type);
+ return;
+ }
+
+ I915_WRITE(MG_DP_MODE(port, 0), ln0);
+ I915_WRITE(MG_DP_MODE(port, 1), ln1);
+}
+
int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8602f2e17d86..d04be4c1f30e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1702,6 +1702,7 @@ void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits);
void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits);
+void icl_program_mg_dp_mode(struct intel_dp *intel_dp);
void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
--
2.14.3
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^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 23/24] drm/i915/icl: program MG_DP_MODE
2018-05-22 0:25 ` [PATCH 23/24] drm/i915/icl: program MG_DP_MODE Paulo Zanoni
@ 2018-06-19 12:59 ` Maarten Lankhorst
2018-06-19 13:00 ` Maarten Lankhorst
0 siblings, 1 reply; 127+ messages in thread
From: Maarten Lankhorst @ 2018-06-19 12:59 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: Dhinakaran Pandiyan
Op 22-05-18 om 02:25 schreef Paulo Zanoni:
> Programming this register is part of the Enable Sequence for
> DisplayPort on ICL. Do as the spec says.
>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++
> drivers/gpu/drm/i915/intel_ddi.c | 2 ++
> drivers/gpu/drm/i915/intel_dp.c | 66 ++++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 4 files changed, 84 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2a501e7590bf..2ccae6c3e905 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1943,6 +1943,21 @@ enum i915_power_well_id {
> #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
> #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
>
> +#define _MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
> +#define _MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
> +#define _MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
> +#define _MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
> +#define _MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
> +#define _MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
> +#define _MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
> +#define _MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
> +#define MG_DP_MODE(port, ln) \
> + _ICL_MG_PHY_PORT_LN(port, ln, _MG_DP_MODE_LN0_ACU_PORT1, \
> + _MG_DP_MODE_LN0_ACU_PORT2, \
> + _MG_DP_MODE_LN1_ACU_PORT1)
> +#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
> +#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
> +
> /* The spec defines this only for BXT PHY0, but lets assume that this
> * would exist for PHY1 too if it had a second channel.
> */
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 1d5bfec57c33..c3c29565b863 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2667,6 +2667,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
>
> intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
>
> + icl_program_mg_dp_mode(intel_dp);
> +
> if (IS_ICELAKE(dev_priv))
> icl_ddi_vswing_sequence(encoder, level, encoder->type);
> else if (IS_CANNONLAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a883a3264e56..1228d6185f76 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -229,6 +229,72 @@ intel_dp_link_required(int pixel_clock, int bpp)
> return DIV_ROUND_UP(pixel_clock * bpp, 8);
> }
>
> +void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> + enum port port = intel_dig_port->base.port;
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + u32 ln0, ln1, lane_info;
> +
> + if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
> + return;
> +
> + ln0 = I915_READ(MG_DP_MODE(port, 0));
> + ln1 = I915_READ(MG_DP_MODE(port, 1));
> +
> + switch (intel_dig_port->tc_type) {
> + case TC_PORT_TYPEC:
> + ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
> + ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
> +
> + lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
> + DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
> + DP_LANE_ASSIGNMENT_SHIFT(tc_port);
> +
> + switch (lane_info) {
> + case 0x1:
> + case 0x4:
> + break;
Shouldn't this still be x1 mode?
~Maarten
> + case 0x2:
> + ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
> + break;
> + case 0x3:
> + ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> + MG_DP_MODE_CFG_DP_X2_MODE;
> + break;
> + case 0x8:
> + ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> + break;
> + case 0xC:
> + ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> + MG_DP_MODE_CFG_DP_X2_MODE;
> + break;
> + case 0xF:
> + ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> + MG_DP_MODE_CFG_DP_X2_MODE;
> + ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> + MG_DP_MODE_CFG_DP_X2_MODE;
> + break;
> + default:
> + MISSING_CASE(lane_info);
> + }
> + break;
> +
> + case TC_PORT_LEGACY:
> + ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
> + ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
> + break;
> +
> + default:
> + MISSING_CASE(intel_dig_port->tc_type);
> + return;
> + }
> +
> + I915_WRITE(MG_DP_MODE(port, 0), ln0);
> + I915_WRITE(MG_DP_MODE(port, 1), ln1);
> +}
> +
> int
> intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 8602f2e17d86..d04be4c1f30e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1702,6 +1702,7 @@ void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
> unsigned int frontbuffer_bits);
> void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
> unsigned int frontbuffer_bits);
> +void icl_program_mg_dp_mode(struct intel_dp *intel_dp);
>
> void
> intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
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^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 23/24] drm/i915/icl: program MG_DP_MODE
2018-06-19 12:59 ` Maarten Lankhorst
@ 2018-06-19 13:00 ` Maarten Lankhorst
0 siblings, 0 replies; 127+ messages in thread
From: Maarten Lankhorst @ 2018-06-19 13:00 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: Dhinakaran Pandiyan
Op 19-06-18 om 14:59 schreef Maarten Lankhorst:
> Op 22-05-18 om 02:25 schreef Paulo Zanoni:
>> Programming this register is part of the Enable Sequence for
>> DisplayPort on ICL. Do as the spec says.
>>
>> Cc: Animesh Manna <animesh.manna@intel.com>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++
>> drivers/gpu/drm/i915/intel_ddi.c | 2 ++
>> drivers/gpu/drm/i915/intel_dp.c | 66 ++++++++++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_drv.h | 1 +
>> 4 files changed, 84 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 2a501e7590bf..2ccae6c3e905 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1943,6 +1943,21 @@ enum i915_power_well_id {
>> #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
>> #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
>>
>> +#define _MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
>> +#define _MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
>> +#define _MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
>> +#define _MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
>> +#define _MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
>> +#define _MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
>> +#define _MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
>> +#define _MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
>> +#define MG_DP_MODE(port, ln) \
>> + _ICL_MG_PHY_PORT_LN(port, ln, _MG_DP_MODE_LN0_ACU_PORT1, \
>> + _MG_DP_MODE_LN0_ACU_PORT2, \
>> + _MG_DP_MODE_LN1_ACU_PORT1)
>> +#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
>> +#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
>> +
>> /* The spec defines this only for BXT PHY0, but lets assume that this
>> * would exist for PHY1 too if it had a second channel.
>> */
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 1d5bfec57c33..c3c29565b863 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -2667,6 +2667,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
>>
>> intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
>>
>> + icl_program_mg_dp_mode(intel_dp);
>> +
>> if (IS_ICELAKE(dev_priv))
>> icl_ddi_vswing_sequence(encoder, level, encoder->type);
>> else if (IS_CANNONLAKE(dev_priv))
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index a883a3264e56..1228d6185f76 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -229,6 +229,72 @@ intel_dp_link_required(int pixel_clock, int bpp)
>> return DIV_ROUND_UP(pixel_clock * bpp, 8);
>> }
>>
>> +void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
>> +{
>> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>> + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
>> + enum port port = intel_dig_port->base.port;
>> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>> + u32 ln0, ln1, lane_info;
>> +
>> + if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
>> + return;
>> +
>> + ln0 = I915_READ(MG_DP_MODE(port, 0));
>> + ln1 = I915_READ(MG_DP_MODE(port, 1));
>> +
>> + switch (intel_dig_port->tc_type) {
>> + case TC_PORT_TYPEC:
>> + ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
>> + ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
>> +
>> + lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
>> + DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
>> + DP_LANE_ASSIGNMENT_SHIFT(tc_port);
>> +
>> + switch (lane_info) {
>> + case 0x1:
>> + case 0x4:
>> + break;
> Shouldn't this still be x1 mode?
Ah nm, found the mapping.
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 24/24] drm/i915/icl: toggle PHY clock gating around link training
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (22 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 23/24] drm/i915/icl: program MG_DP_MODE Paulo Zanoni
@ 2018-05-22 0:25 ` Paulo Zanoni
2018-06-19 13:22 ` Maarten Lankhorst
2018-05-22 0:38 ` ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches Patchwork
` (16 subsequent siblings)
40 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-22 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
The Gen11 TypeC PHY DDI Buffer chapter, PHY Clock Gating Programming
section says that PHY clock gating should be disabled before starting
voltage swing programming, then enabled after any link training is
complete.
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 21 +++++++++++++
drivers/gpu/drm/i915/intel_ddi.c | 3 ++
drivers/gpu/drm/i915/intel_dp.c | 66 ++++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
4 files changed, 92 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2ccae6c3e905..9d2c022bc3a1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1957,6 +1957,27 @@ enum i915_power_well_id {
_MG_DP_MODE_LN1_ACU_PORT1)
#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
+#define MG_DP_MODE_CFG_TR2PWR_GATING (1 << 5)
+#define MG_DP_MODE_CFG_TRPWR_GATING (1 << 4)
+#define MG_DP_MODE_CFG_CLNPWR_GATING (1 << 3)
+#define MG_DP_MODE_CFG_DIGPWR_GATING (1 << 2)
+#define MG_DP_MODE_CFG_GAONPWR_GATING (1 << 1)
+
+#define _MG_MISC_SUS0_PORT1 0x168814
+#define _MG_MISC_SUS0_PORT2 0x169814
+#define _MG_MISC_SUS0_PORT3 0x16A814
+#define _MG_MISC_SUS0_PORT4 0x16B814
+#define MG_MISC_SUS0(tc_port) \
+ _MMIO(_PORT(tc_port, _MG_MISC_SUS0_PORT1, _MG_MISC_SUS0_PORT2))
+#define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK (3 << 14)
+#define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x) ((x) << 14)
+#define MG_MISC_SUS0_CFG_TR2PWR_GATING (1 << 12)
+#define MG_MISC_SUS0_CFG_CL2PWR_GATING (1 << 11)
+#define MG_MISC_SUS0_CFG_GAONPWR_GATING (1 << 10)
+#define MG_MISC_SUS0_CFG_TRPWR_GATING (1 << 7)
+#define MG_MISC_SUS0_CFG_CL1PWR_GATING (1 << 6)
+#define MG_MISC_SUS0_CFG_DGPWR_GATING (1 << 5)
+
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c3c29565b863..6617950a28a9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2668,6 +2668,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
icl_program_mg_dp_mode(intel_dp);
+ icl_disable_phy_clock_gating(dig_port);
if (IS_ICELAKE(dev_priv))
icl_ddi_vswing_sequence(encoder, level, encoder->type);
@@ -2684,6 +2685,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
+
+ icl_enable_phy_clock_gating(dig_port);
}
static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1228d6185f76..e898d61b5924 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -295,6 +295,72 @@ void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
I915_WRITE(MG_DP_MODE(port, 1), ln1);
}
+void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ enum port port = dig_port->base.port;
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+ i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
+ u32 val;
+ int i;
+
+ if (tc_port == PORT_TC_NONE)
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
+ val = I915_READ(mg_regs[i]);
+ val |= MG_DP_MODE_CFG_TR2PWR_GATING |
+ MG_DP_MODE_CFG_TRPWR_GATING |
+ MG_DP_MODE_CFG_CLNPWR_GATING |
+ MG_DP_MODE_CFG_DIGPWR_GATING |
+ MG_DP_MODE_CFG_GAONPWR_GATING;
+ I915_WRITE(mg_regs[i], val);
+ }
+
+ val = I915_READ(MG_MISC_SUS0(tc_port));
+ val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
+ MG_MISC_SUS0_CFG_TR2PWR_GATING |
+ MG_MISC_SUS0_CFG_CL2PWR_GATING |
+ MG_MISC_SUS0_CFG_GAONPWR_GATING |
+ MG_MISC_SUS0_CFG_TRPWR_GATING |
+ MG_MISC_SUS0_CFG_CL1PWR_GATING |
+ MG_MISC_SUS0_CFG_DGPWR_GATING;
+ I915_WRITE(MG_MISC_SUS0(tc_port), val);
+}
+
+void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ enum port port = dig_port->base.port;
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+ i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
+ u32 val;
+ int i;
+
+ if (tc_port == PORT_TC_NONE)
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
+ val = I915_READ(mg_regs[i]);
+ val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
+ MG_DP_MODE_CFG_TRPWR_GATING |
+ MG_DP_MODE_CFG_CLNPWR_GATING |
+ MG_DP_MODE_CFG_DIGPWR_GATING |
+ MG_DP_MODE_CFG_GAONPWR_GATING);
+ I915_WRITE(mg_regs[i], val);
+ }
+
+ val = I915_READ(MG_MISC_SUS0(tc_port));
+ val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
+ MG_MISC_SUS0_CFG_TR2PWR_GATING |
+ MG_MISC_SUS0_CFG_CL2PWR_GATING |
+ MG_MISC_SUS0_CFG_GAONPWR_GATING |
+ MG_MISC_SUS0_CFG_TRPWR_GATING |
+ MG_MISC_SUS0_CFG_CL1PWR_GATING |
+ MG_MISC_SUS0_CFG_DGPWR_GATING);
+ I915_WRITE(MG_MISC_SUS0(tc_port), val);
+}
+
int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d04be4c1f30e..8c77e0499b44 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1703,6 +1703,8 @@ void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits);
void icl_program_mg_dp_mode(struct intel_dp *intel_dp);
+void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port);
+void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port);
void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 24/24] drm/i915/icl: toggle PHY clock gating around link training
2018-05-22 0:25 ` [PATCH 24/24] drm/i915/icl: toggle PHY clock gating around link training Paulo Zanoni
@ 2018-06-19 13:22 ` Maarten Lankhorst
0 siblings, 0 replies; 127+ messages in thread
From: Maarten Lankhorst @ 2018-06-19 13:22 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx
Op 22-05-18 om 02:25 schreef Paulo Zanoni:
> The Gen11 TypeC PHY DDI Buffer chapter, PHY Clock Gating Programming
> section says that PHY clock gating should be disabled before starting
> voltage swing programming, then enabled after any link training is
> complete.
>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 21 +++++++++++++
> drivers/gpu/drm/i915/intel_ddi.c | 3 ++
> drivers/gpu/drm/i915/intel_dp.c | 66 ++++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 4 files changed, 92 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2ccae6c3e905..9d2c022bc3a1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1957,6 +1957,27 @@ enum i915_power_well_id {
> _MG_DP_MODE_LN1_ACU_PORT1)
> #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
> #define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
> +#define MG_DP_MODE_CFG_TR2PWR_GATING (1 << 5)
> +#define MG_DP_MODE_CFG_TRPWR_GATING (1 << 4)
> +#define MG_DP_MODE_CFG_CLNPWR_GATING (1 << 3)
> +#define MG_DP_MODE_CFG_DIGPWR_GATING (1 << 2)
> +#define MG_DP_MODE_CFG_GAONPWR_GATING (1 << 1)
> +
> +#define _MG_MISC_SUS0_PORT1 0x168814
> +#define _MG_MISC_SUS0_PORT2 0x169814
> +#define _MG_MISC_SUS0_PORT3 0x16A814
> +#define _MG_MISC_SUS0_PORT4 0x16B814
> +#define MG_MISC_SUS0(tc_port) \
> + _MMIO(_PORT(tc_port, _MG_MISC_SUS0_PORT1, _MG_MISC_SUS0_PORT2))
> +#define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK (3 << 14)
> +#define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x) ((x) << 14)
> +#define MG_MISC_SUS0_CFG_TR2PWR_GATING (1 << 12)
> +#define MG_MISC_SUS0_CFG_CL2PWR_GATING (1 << 11)
> +#define MG_MISC_SUS0_CFG_GAONPWR_GATING (1 << 10)
> +#define MG_MISC_SUS0_CFG_TRPWR_GATING (1 << 7)
> +#define MG_MISC_SUS0_CFG_CL1PWR_GATING (1 << 6)
> +#define MG_MISC_SUS0_CFG_DGPWR_GATING (1 << 5)
> +
>
> /* The spec defines this only for BXT PHY0, but lets assume that this
> * would exist for PHY1 too if it had a second channel.
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index c3c29565b863..6617950a28a9 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2668,6 +2668,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
>
> icl_program_mg_dp_mode(intel_dp);
> + icl_disable_phy_clock_gating(dig_port);
>
> if (IS_ICELAKE(dev_priv))
> icl_ddi_vswing_sequence(encoder, level, encoder->type);
> @@ -2684,6 +2685,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> intel_dp_start_link_train(intel_dp);
> if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> intel_dp_stop_link_train(intel_dp);
> +
> + icl_enable_phy_clock_gating(dig_port);
> }
>
> static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1228d6185f76..e898d61b5924 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -295,6 +295,72 @@ void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
> I915_WRITE(MG_DP_MODE(port, 1), ln1);
> }
>
> +void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> + enum port port = dig_port->base.port;
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
> + u32 val;
> + int i;
> +
> + if (tc_port == PORT_TC_NONE)
> + return;
> +
> + for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> + val = I915_READ(mg_regs[i]);
> + val |= MG_DP_MODE_CFG_TR2PWR_GATING |
> + MG_DP_MODE_CFG_TRPWR_GATING |
> + MG_DP_MODE_CFG_CLNPWR_GATING |
> + MG_DP_MODE_CFG_DIGPWR_GATING |
> + MG_DP_MODE_CFG_GAONPWR_GATING;
> + I915_WRITE(mg_regs[i], val);
> + }
> +
> + val = I915_READ(MG_MISC_SUS0(tc_port));
> + val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
> + MG_MISC_SUS0_CFG_TR2PWR_GATING |
> + MG_MISC_SUS0_CFG_CL2PWR_GATING |
> + MG_MISC_SUS0_CFG_GAONPWR_GATING |
> + MG_MISC_SUS0_CFG_TRPWR_GATING |
> + MG_MISC_SUS0_CFG_CL1PWR_GATING |
> + MG_MISC_SUS0_CFG_DGPWR_GATING;
> + I915_WRITE(MG_MISC_SUS0(tc_port), val);
> +}
> +
> +void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> + enum port port = dig_port->base.port;
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
> + u32 val;
> + int i;
> +
> + if (tc_port == PORT_TC_NONE)
> + return;
> +
> + for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> + val = I915_READ(mg_regs[i]);
> + val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
> + MG_DP_MODE_CFG_TRPWR_GATING |
> + MG_DP_MODE_CFG_CLNPWR_GATING |
> + MG_DP_MODE_CFG_DIGPWR_GATING |
> + MG_DP_MODE_CFG_GAONPWR_GATING);
> + I915_WRITE(mg_regs[i], val);
> + }
> +
> + val = I915_READ(MG_MISC_SUS0(tc_port));
> + val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
> + MG_MISC_SUS0_CFG_TR2PWR_GATING |
> + MG_MISC_SUS0_CFG_CL2PWR_GATING |
> + MG_MISC_SUS0_CFG_GAONPWR_GATING |
> + MG_MISC_SUS0_CFG_TRPWR_GATING |
> + MG_MISC_SUS0_CFG_CL1PWR_GATING |
> + MG_MISC_SUS0_CFG_DGPWR_GATING);
> + I915_WRITE(MG_MISC_SUS0(tc_port), val);
> +}
> +
> int
> intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index d04be4c1f30e..8c77e0499b44 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1703,6 +1703,8 @@ void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
> void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
> unsigned int frontbuffer_bits);
> void icl_program_mg_dp_mode(struct intel_dp *intel_dp);
> +void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port);
> +void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port);
>
> void
> intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (23 preceding siblings ...)
2018-05-22 0:25 ` [PATCH 24/24] drm/i915/icl: toggle PHY clock gating around link training Paulo Zanoni
@ 2018-05-22 0:38 ` Patchwork
2018-05-22 0:45 ` ✗ Fi.CI.SPARSE: " Patchwork
` (15 subsequent siblings)
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-05-22 0:38 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches
URL : https://patchwork.freedesktop.org/series/43546/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2ab358790967 drm/i915/icl: Extend AUX F interrupts to ICL
7f3648f2c0e1 drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
4b03c3e28a4a drm/i915/icl: introduce tc_port
e145ad6bdaf7 drm/i915/icl: Support for TC North Display interrupts
4b11db5d4aee drm/i915/icp: Add Interrupt Support
25d4a67290ae drm/i915/ICL: Add register definition for DFLEXDPMLE
e3cbd1343f5a drm/i915/icl: Add DDI HDMI level selection for ICL
e2f7e7c949f8 drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
f70b5bcd4230 drm/i915/icl: Add Icelake PCH detection
20396ea4a008 drm/i915/icl: add icelake_get_ddi_pll()
ea723cce4da2 drm/i915/icl: Get DDI clock for ICL based on PLLs.
8aeab8ca85b0 drm/i915/icl: Calculate link clock using the new registers
ce32f58b49ab drm/i915/icl: unconditionally init DDI for every port
84be8b3f963c drm/i915/icl: start adding the TBT pll
-:162: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#162: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:137:
};
+#define I915_NUM_PLLS 7
total: 0 errors, 0 warnings, 1 checks, 129 lines checked
eb581c948e8c drm/i915/icl: compute the TBT PLL registers
-:18: CHECK:CAMELCASE: Avoid CamelCase: <icl_tbt_pll_24MHz_values>
#18: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2455:
+static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
-:23: CHECK:CAMELCASE: Avoid CamelCase: <icl_tbt_pll_19_2MHz_values>
#23: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2460:
+static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
total: 0 errors, 0 warnings, 2 checks, 51 lines checked
bb11361a8af0 drm/i915/icl: Handle hotplug interrupts for DP over TBT
2eb44a94c4a2 drm/i915/icl: Add 10-bit support for hdmi
83cac5646aac drm/i915/icl: implement icl_digital_port_connected()
dde729bf09c6 drm/i915/icl: store the port type for TC ports
38f287b089ee drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
cb0454d09ead drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
2732eb911ea5 drm/i915/icl: Update FIA supported lane count for hpd.
6f6990bdd31e drm/i915/icl: program MG_DP_MODE
c9e0a92395b2 drm/i915/icl: toggle PHY clock gating around link training
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* ✗ Fi.CI.SPARSE: warning for More ICL display patches
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (24 preceding siblings ...)
2018-05-22 0:38 ` ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches Patchwork
@ 2018-05-22 0:45 ` Patchwork
2018-05-22 1:00 ` ✓ Fi.CI.BAT: success " Patchwork
` (14 subsequent siblings)
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-05-22 0:45 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches
URL : https://patchwork.freedesktop.org/series/43546/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Extend AUX F interrupts to ICL
Okay!
Commit: drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
Okay!
Commit: drm/i915/icl: introduce tc_port
Okay!
Commit: drm/i915/icl: Support for TC North Display interrupts
Okay!
Commit: drm/i915/icp: Add Interrupt Support
Okay!
Commit: drm/i915/ICL: Add register definition for DFLEXDPMLE
Okay!
Commit: drm/i915/icl: Add DDI HDMI level selection for ICL
Okay!
Commit: drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
Okay!
Commit: drm/i915/icl: Add Icelake PCH detection
Okay!
Commit: drm/i915/icl: add icelake_get_ddi_pll()
Okay!
Commit: drm/i915/icl: Get DDI clock for ICL based on PLLs.
Okay!
Commit: drm/i915/icl: Calculate link clock using the new registers
Okay!
Commit: drm/i915/icl: unconditionally init DDI for every port
Okay!
Commit: drm/i915/icl: start adding the TBT pll
Okay!
Commit: drm/i915/icl: compute the TBT PLL registers
Okay!
Commit: drm/i915/icl: Handle hotplug interrupts for DP over TBT
Okay!
Commit: drm/i915/icl: Add 10-bit support for hdmi
Okay!
Commit: drm/i915/icl: implement icl_digital_port_connected()
Okay!
Commit: drm/i915/icl: store the port type for TC ports
Okay!
Commit: drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
Okay!
Commit: drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
Okay!
Commit: drm/i915/icl: Update FIA supported lane count for hpd.
-O:drivers/gpu/drm/i915/intel_dp.c:186:16: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dp.c:186:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
Commit: drm/i915/icl: program MG_DP_MODE
Okay!
Commit: drm/i915/icl: toggle PHY clock gating around link training
Okay!
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* ✓ Fi.CI.BAT: success for More ICL display patches
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (25 preceding siblings ...)
2018-05-22 0:45 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-05-22 1:00 ` Patchwork
2018-05-22 1:52 ` ✓ Fi.CI.IGT: " Patchwork
` (13 subsequent siblings)
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-05-22 1:00 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches
URL : https://patchwork.freedesktop.org/series/43546/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4213 -> Patchwork_9074 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9074 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9074, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/43546/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9074:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_gttfill@basic:
fi-pnv-d510: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_9074 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927)
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
== Participating hosts (43 -> 39) ==
Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-bsw-cyan fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4213 -> Patchwork_9074
CI_DRM_4213: d7671eea834c4e06f9b86e2248581d23ad98ec73 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4489: d8d5dde407e7f7b17850be71d24a7e679533b03d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9074: c9e0a92395b2122df86175990fef7402892664f3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4489: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit
== Linux commits ==
c9e0a92395b2 drm/i915/icl: toggle PHY clock gating around link training
6f6990bdd31e drm/i915/icl: program MG_DP_MODE
2732eb911ea5 drm/i915/icl: Update FIA supported lane count for hpd.
cb0454d09ead drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
38f287b089ee drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
dde729bf09c6 drm/i915/icl: store the port type for TC ports
83cac5646aac drm/i915/icl: implement icl_digital_port_connected()
2eb44a94c4a2 drm/i915/icl: Add 10-bit support for hdmi
bb11361a8af0 drm/i915/icl: Handle hotplug interrupts for DP over TBT
eb581c948e8c drm/i915/icl: compute the TBT PLL registers
84be8b3f963c drm/i915/icl: start adding the TBT pll
ce32f58b49ab drm/i915/icl: unconditionally init DDI for every port
8aeab8ca85b0 drm/i915/icl: Calculate link clock using the new registers
ea723cce4da2 drm/i915/icl: Get DDI clock for ICL based on PLLs.
20396ea4a008 drm/i915/icl: add icelake_get_ddi_pll()
f70b5bcd4230 drm/i915/icl: Add Icelake PCH detection
e2f7e7c949f8 drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
e3cbd1343f5a drm/i915/icl: Add DDI HDMI level selection for ICL
25d4a67290ae drm/i915/ICL: Add register definition for DFLEXDPMLE
4b11db5d4aee drm/i915/icp: Add Interrupt Support
e145ad6bdaf7 drm/i915/icl: Support for TC North Display interrupts
4b03c3e28a4a drm/i915/icl: introduce tc_port
7f3648f2c0e1 drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
2ab358790967 drm/i915/icl: Extend AUX F interrupts to ICL
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9074/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* ✓ Fi.CI.IGT: success for More ICL display patches
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (26 preceding siblings ...)
2018-05-22 1:00 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-05-22 1:52 ` Patchwork
2018-05-23 22:59 ` ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches (rev2) Patchwork
` (12 subsequent siblings)
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-05-22 1:52 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches
URL : https://patchwork.freedesktop.org/series/43546/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4213_full -> Patchwork_9074_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9074_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9074_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/43546/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9074_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-bsd1:
shard-kbl: SKIP -> PASS
igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions:
shard-snb: PASS -> SKIP
igt@pm_rc6_residency@rc6-accuracy:
shard-kbl: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_9074_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_eio@in-flight-suspend:
shard-kbl: PASS -> INCOMPLETE (fdo#103665)
igt@kms_color@pipe-a-legacy-gamma-reset:
shard-kbl: PASS -> DMESG-WARN (fdo#103313, fdo#103558, fdo#105602) +5
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-kbl: PASS -> FAIL (fdo#104724, fdo#103232, fdo#103191)
igt@kms_flip@2x-dpms-vs-vblank-race:
shard-hsw: PASS -> FAIL (fdo#103060)
igt@kms_flip@dpms-vs-vblank-race-interruptible:
shard-glk: PASS -> FAIL (fdo#103060)
igt@kms_flip_tiling@flip-to-x-tiled:
shard-glk: PASS -> FAIL (fdo#104724)
igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
shard-apl: PASS -> DMESG-WARN (fdo#103558, fdo#105602) +8
igt@kms_pipe_crc_basic@read-crc-pipe-a:
shard-kbl: PASS -> DMESG-WARN (fdo#103313)
igt@kms_rotation_crc@sprite-rotation-270:
shard-kbl: PASS -> DMESG-WARN (fdo#103558, fdo#105602) +14
igt@kms_setmode@basic:
shard-hsw: PASS -> FAIL (fdo#99912)
==== Possible fixes ====
igt@drv_selftest@live_hangcheck:
shard-kbl: DMESG-FAIL (fdo#106560) -> PASS
igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
shard-glk: FAIL (fdo#105703) -> PASS
igt@kms_flip@2x-blocking-wf_vblank:
shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS
igt@kms_flip@2x-flip-vs-expired-vblank:
shard-hsw: FAIL (fdo#102887) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render:
shard-snb: FAIL (fdo#104724, fdo#103167) -> PASS
igt@kms_setmode@basic:
shard-apl: FAIL (fdo#99912) -> PASS
==== Warnings ====
igt@kms_setmode@basic:
shard-kbl: FAIL (fdo#99912) -> DMESG-FAIL (fdo#103558, fdo#99912, fdo#105602)
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (9 -> 9) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4213 -> Patchwork_9074
CI_DRM_4213: d7671eea834c4e06f9b86e2248581d23ad98ec73 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4489: d8d5dde407e7f7b17850be71d24a7e679533b03d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9074: c9e0a92395b2122df86175990fef7402892664f3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4489: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9074/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches (rev2)
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (27 preceding siblings ...)
2018-05-22 1:52 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-05-23 22:59 ` Patchwork
2018-05-23 23:06 ` ✗ Fi.CI.SPARSE: " Patchwork
` (11 subsequent siblings)
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-05-23 22:59 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches (rev2)
URL : https://patchwork.freedesktop.org/series/43546/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
127450a17db7 drm/i915/icl: Extend AUX F interrupts to ICL
531f7327f015 drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
f399dccd8cc6 drm/i915/icl: introduce tc_port
3f0e2981505d drm/i915/icl: Support for TC North Display interrupts
e4ec5bf09dc4 drm/i915/icp: Add Interrupt Support
6cb5cbdd40c5 drm/i915/ICL: Add register definition for DFLEXDPMLE
d33c632e9ea9 drm/i915/icl: Add DDI HDMI level selection for ICL
d58f0e17059b drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
f9905e6229bc drm/i915/icl: Add Icelake PCH detection
1da0c5f49ffc drm/i915/icl: add icelake_get_ddi_pll()
ba91e7a19262 drm/i915/icl: Get DDI clock for ICL based on PLLs.
4a59b2d6c399 drm/i915/icl: Calculate link clock using the new registers
41d365245a0d drm/i915/icl: unconditionally init DDI for every port
e30520c96c42 drm/i915/icl: start adding the TBT pll
-:162: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#162: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:137:
};
+#define I915_NUM_PLLS 7
total: 0 errors, 0 warnings, 1 checks, 129 lines checked
4d717c17a206 drm/i915/icl: compute the TBT PLL registers
-:18: CHECK:CAMELCASE: Avoid CamelCase: <icl_tbt_pll_24MHz_values>
#18: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2455:
+static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
-:23: CHECK:CAMELCASE: Avoid CamelCase: <icl_tbt_pll_19_2MHz_values>
#23: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2460:
+static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
total: 0 errors, 0 warnings, 2 checks, 51 lines checked
839e6e916ef0 drm/i915/icl: Handle hotplug interrupts for DP over TBT
f9457e7eaac0 drm/i915/icl: Add 10-bit support for hdmi
d39f683cc31c drm/i915/icl: implement icl_digital_port_connected()
44c232d87e62 drm/i915/icl: store the port type for TC ports
e9916912b1a7 drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
e737bd4f64f3 drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
cd9cf1051643 drm/i915/icl: Update FIA supported lane count for hpd.
b46919848803 drm/i915/icl: program MG_DP_MODE
c7b5ae16c069 drm/i915/icl: toggle PHY clock gating around link training
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* ✗ Fi.CI.SPARSE: warning for More ICL display patches (rev2)
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (28 preceding siblings ...)
2018-05-23 22:59 ` ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches (rev2) Patchwork
@ 2018-05-23 23:06 ` Patchwork
2018-05-23 23:19 ` ✓ Fi.CI.BAT: success " Patchwork
` (10 subsequent siblings)
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-05-23 23:06 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches (rev2)
URL : https://patchwork.freedesktop.org/series/43546/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Extend AUX F interrupts to ICL
Okay!
Commit: drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
Okay!
Commit: drm/i915/icl: introduce tc_port
Okay!
Commit: drm/i915/icl: Support for TC North Display interrupts
Okay!
Commit: drm/i915/icp: Add Interrupt Support
Okay!
Commit: drm/i915/ICL: Add register definition for DFLEXDPMLE
Okay!
Commit: drm/i915/icl: Add DDI HDMI level selection for ICL
Okay!
Commit: drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
Okay!
Commit: drm/i915/icl: Add Icelake PCH detection
Okay!
Commit: drm/i915/icl: add icelake_get_ddi_pll()
Okay!
Commit: drm/i915/icl: Get DDI clock for ICL based on PLLs.
Okay!
Commit: drm/i915/icl: Calculate link clock using the new registers
Okay!
Commit: drm/i915/icl: unconditionally init DDI for every port
Okay!
Commit: drm/i915/icl: start adding the TBT pll
Okay!
Commit: drm/i915/icl: compute the TBT PLL registers
Okay!
Commit: drm/i915/icl: Handle hotplug interrupts for DP over TBT
Okay!
Commit: drm/i915/icl: Add 10-bit support for hdmi
Okay!
Commit: drm/i915/icl: implement icl_digital_port_connected()
Okay!
Commit: drm/i915/icl: store the port type for TC ports
Okay!
Commit: drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
Okay!
Commit: drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
Okay!
Commit: drm/i915/icl: Update FIA supported lane count for hpd.
-O:drivers/gpu/drm/i915/intel_dp.c:186:16: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dp.c:186:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
Commit: drm/i915/icl: program MG_DP_MODE
Okay!
Commit: drm/i915/icl: toggle PHY clock gating around link training
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* ✓ Fi.CI.BAT: success for More ICL display patches (rev2)
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (29 preceding siblings ...)
2018-05-23 23:06 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-05-23 23:19 ` Patchwork
2018-05-24 0:54 ` ✗ Fi.CI.IGT: failure " Patchwork
` (9 subsequent siblings)
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-05-23 23:19 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches (rev2)
URL : https://patchwork.freedesktop.org/series/43546/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4227 -> Patchwork_9100 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9100 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9100, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/43546/revisions/2/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9100:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_gttfill@basic:
fi-pnv-d510: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_9100 that come from known issues:
=== IGT changes ===
==== Possible fixes ====
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-hsw-4770: FAIL (fdo#100368) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
== Participating hosts (44 -> 38) ==
Missing (6): fi-ilk-m540 fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4227 -> Patchwork_9100
CI_DRM_4227: a8727d3fe03770e4d523468dfbc487dfe01597d3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4495: 71c7a5740913d2618f44bca252669efe8a84f4c9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9100: c7b5ae16c06957a7a21cac7e9272c507dd85eb09 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4495: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Linux commits ==
c7b5ae16c069 drm/i915/icl: toggle PHY clock gating around link training
b46919848803 drm/i915/icl: program MG_DP_MODE
cd9cf1051643 drm/i915/icl: Update FIA supported lane count for hpd.
e737bd4f64f3 drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
e9916912b1a7 drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
44c232d87e62 drm/i915/icl: store the port type for TC ports
d39f683cc31c drm/i915/icl: implement icl_digital_port_connected()
f9457e7eaac0 drm/i915/icl: Add 10-bit support for hdmi
839e6e916ef0 drm/i915/icl: Handle hotplug interrupts for DP over TBT
4d717c17a206 drm/i915/icl: compute the TBT PLL registers
e30520c96c42 drm/i915/icl: start adding the TBT pll
41d365245a0d drm/i915/icl: unconditionally init DDI for every port
4a59b2d6c399 drm/i915/icl: Calculate link clock using the new registers
ba91e7a19262 drm/i915/icl: Get DDI clock for ICL based on PLLs.
1da0c5f49ffc drm/i915/icl: add icelake_get_ddi_pll()
f9905e6229bc drm/i915/icl: Add Icelake PCH detection
d58f0e17059b drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
d33c632e9ea9 drm/i915/icl: Add DDI HDMI level selection for ICL
6cb5cbdd40c5 drm/i915/ICL: Add register definition for DFLEXDPMLE
e4ec5bf09dc4 drm/i915/icp: Add Interrupt Support
3f0e2981505d drm/i915/icl: Support for TC North Display interrupts
f399dccd8cc6 drm/i915/icl: introduce tc_port
531f7327f015 drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
127450a17db7 drm/i915/icl: Extend AUX F interrupts to ICL
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9100/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* ✗ Fi.CI.IGT: failure for More ICL display patches (rev2)
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (30 preceding siblings ...)
2018-05-23 23:19 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-05-24 0:54 ` Patchwork
2018-05-24 23:42 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Paulo Zanoni
` (8 subsequent siblings)
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-05-24 0:54 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches (rev2)
URL : https://patchwork.freedesktop.org/series/43546/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4227_full -> Patchwork_9100_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9100_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9100_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/43546/revisions/2/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9100_full:
=== IGT changes ===
==== Possible regressions ====
igt@drv_selftest@live_gtt:
shard-kbl: PASS -> FAIL
==== Warnings ====
igt@gem_exec_schedule@deep-bsd2:
shard-kbl: PASS -> SKIP
igt@perf_pmu@rc6:
shard-kbl: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_9100_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_hangcheck:
shard-kbl: PASS -> DMESG-FAIL (fdo#106560)
igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
shard-glk: PASS -> FAIL (fdo#106509)
igt@kms_flip@dpms-vs-vblank-race-interruptible:
shard-glk: PASS -> FAIL (fdo#103060)
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-glk: PASS -> FAIL (fdo#105707)
igt@kms_flip_tiling@flip-to-x-tiled:
shard-glk: PASS -> FAIL (fdo#104724)
==== Possible fixes ====
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-kbl: INCOMPLETE (fdo#103665, fdo#106023) -> PASS
igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
shard-glk: FAIL (fdo#105703) -> PASS
igt@kms_flip@2x-plain-flip-fb-recreate:
shard-hsw: FAIL (fdo#100368) -> PASS
igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
shard-hsw: FAIL (fdo#103928) -> PASS
igt@kms_flip@plain-flip-fb-recreate-interruptible:
shard-glk: FAIL (fdo#100368) -> PASS +2
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4227 -> Patchwork_9100
CI_DRM_4227: a8727d3fe03770e4d523468dfbc487dfe01597d3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4495: 71c7a5740913d2618f44bca252669efe8a84f4c9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9100: c7b5ae16c06957a7a21cac7e9272c507dd85eb09 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4495: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9100/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (31 preceding siblings ...)
2018-05-24 0:54 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-05-24 23:42 ` Paulo Zanoni
2018-05-24 23:42 ` [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake Paulo Zanoni
` (6 more replies)
2018-05-24 23:59 ` ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches (rev7) Patchwork
` (7 subsequent siblings)
40 siblings, 7 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-24 23:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Mahesh Kumar <mahesh1.kumar@intel.com>
ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12
mapped to tc ports[1-4].
This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO
pin mapping table.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/intel_i2c.c | 12 ++++++------
3 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 452356a4af07..e48b717769b2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3015,6 +3015,10 @@ enum i915_power_well_id {
#define GPIOF _MMIO(0x5024)
#define GPIOG _MMIO(0x5028)
#define GPIOH _MMIO(0x502c)
+#define GPIOJ _MMIO(0x5034)
+#define GPIOK _MMIO(0x5038)
+#define GPIOL _MMIO(0x503C)
+#define GPIOM _MMIO(0x5040)
# define GPIO_CLOCK_DIR_MASK (1 << 0)
# define GPIO_CLOCK_DIR_IN (0 << 1)
# define GPIO_CLOCK_DIR_OUT (1 << 1)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 75f02a0e7d39..3db2459c79b1 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2276,7 +2276,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_CNP(dev_priv))
ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
- else if (IS_ICELAKE(dev_priv))
+ else if (HAS_PCH_ICP(dev_priv))
ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
else
ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index e6875509bcd9..b91e418028cb 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -77,12 +77,12 @@ static const struct gmbus_pin gmbus_pins_cnp[] = {
};
static const struct gmbus_pin gmbus_pins_icp[] = {
- [GMBUS_PIN_1_BXT] = { "dpa", GPIOA },
- [GMBUS_PIN_2_BXT] = { "dpb", GPIOB },
- [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOC },
- [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOD },
- [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOE },
- [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOF },
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+ [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
+ [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
+ [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
};
/* pin is expected to be valid */
--
2.14.3
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^ permalink raw reply related [flat|nested] 127+ messages in thread* [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake
2018-05-24 23:42 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Paulo Zanoni
@ 2018-05-24 23:42 ` Paulo Zanoni
2018-05-25 18:32 ` James Ausmus
2018-06-14 19:23 ` Rodrigo Vivi
2018-05-24 23:42 ` [PATCH 27/24] drm/i915/dp: Add support for HBR3 and TPS4 during link training Paulo Zanoni
` (5 subsequent siblings)
6 siblings, 2 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-24 23:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Manasi Navare <manasi.d.navare@intel.com>
For ICL, on Combo PHY the allowed max rates are:
- HBR3 8.1 eDP (DDIA)
- HBR2 5.4 DisplayPort (DDIB)
and for MG PHY/TC DDI Ports allowed DP rates are:
- HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
- DP on legacy connector - DDIC/D/E/F)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5109023abe28..3ee8e74cf2b8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
return 810000;
}
+static int icl_max_source_rate(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum port port = dig_port->base.port;
+
+ /* On Combo PHY port A max speed is HBR3 for all Vccio voltages
+ * and on Combo PHY Port B the maximum supported is HBR2.
+ */
+ if (port == PORT_B)
+ return 540000;
+
+ return 810000;
+}
+
static void
intel_dp_set_source_rates(struct intel_dp *intel_dp)
{
@@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
/* This should only be done once */
WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
- if (IS_CANNONLAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 10) {
source_rates = cnl_rates;
size = ARRAY_SIZE(cnl_rates);
- max_rate = cnl_max_source_rate(intel_dp);
+ if (IS_ICELAKE(dev_priv))
+ max_rate = icl_max_source_rate(intel_dp);
+ else
+ max_rate = cnl_max_source_rate(intel_dp);
} else if (IS_GEN9_LP(dev_priv)) {
source_rates = bxt_rates;
size = ARRAY_SIZE(bxt_rates);
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake
2018-05-24 23:42 ` [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake Paulo Zanoni
@ 2018-05-25 18:32 ` James Ausmus
2018-06-01 23:43 ` Paulo Zanoni
2018-06-14 19:23 ` Rodrigo Vivi
1 sibling, 1 reply; 127+ messages in thread
From: James Ausmus @ 2018-05-25 18:32 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Rodrigo Vivi
On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> From: Manasi Navare <manasi.d.navare@intel.com>
>
> For ICL, on Combo PHY the allowed max rates are:
> - HBR3 8.1 eDP (DDIA)
> - HBR2 5.4 DisplayPort (DDIB)
> and for MG PHY/TC DDI Ports allowed DP rates are:
> - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> - DP on legacy connector - DDIC/D/E/F)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5109023abe28..3ee8e74cf2b8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
> return 810000;
> }
>
> +static int icl_max_source_rate(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum port port = dig_port->base.port;
> +
> + /* On Combo PHY port A max speed is HBR3 for all Vccio voltages
> + * and on Combo PHY Port B the maximum supported is HBR2.
> + */
> + if (port == PORT_B)
> + return 540000;
> +
> + return 810000;
> +}
> +
> static void
> intel_dp_set_source_rates(struct intel_dp *intel_dp)
> {
> @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> /* This should only be done once */
> WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
>
> - if (IS_CANNONLAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 10) {
> source_rates = cnl_rates;
> size = ARRAY_SIZE(cnl_rates);
> - max_rate = cnl_max_source_rate(intel_dp);
> + if (IS_ICELAKE(dev_priv))
> + max_rate = icl_max_source_rate(intel_dp);
> + else
> + max_rate = cnl_max_source_rate(intel_dp);
> } else if (IS_GEN9_LP(dev_priv)) {
> source_rates = bxt_rates;
> size = ARRAY_SIZE(bxt_rates);
> --
> 2.14.3
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake
2018-05-25 18:32 ` James Ausmus
@ 2018-06-01 23:43 ` Paulo Zanoni
2018-06-14 19:24 ` Rodrigo Vivi
0 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-06-01 23:43 UTC (permalink / raw)
To: James Ausmus; +Cc: intel-gfx, Rodrigo Vivi
Em Sex, 2018-05-25 às 11:32 -0700, James Ausmus escreveu:
> On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > From: Manasi Navare <manasi.d.navare@intel.com>
> >
> > For ICL, on Combo PHY the allowed max rates are:
> > - HBR3 8.1 eDP (DDIA)
> > - HBR2 5.4 DisplayPort (DDIB)
> > and for MG PHY/TC DDI Ports allowed DP rates are:
> > - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> > - DP on legacy connector - DDIC/D/E/F)
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: James Ausmus <james.ausmus@intel.com>
>
> Reviewed-by: James Ausmus <james.ausmus@intel.com>
>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
> > 1 file changed, 19 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 5109023abe28..3ee8e74cf2b8 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp
> > *intel_dp)
> > return 810000;
> > }
> >
> > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > +{
> > + struct intel_digital_port *dig_port =
> > dp_to_dig_port(intel_dp);
> > + enum port port = dig_port->base.port;
> > +
> > + /* On Combo PHY port A max speed is HBR3 for all Vccio
> > voltages
> > + * and on Combo PHY Port B the maximum supported is HBR2.
> > + */
> > + if (port == PORT_B)
> > + return 540000;
> > +
> > + return 810000;
> > +}
> > +
> > static void
> > intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > {
> > @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp
> > *intel_dp)
> > /* This should only be done once */
> > WARN_ON(intel_dp->source_rates || intel_dp-
> > >num_source_rates);
> >
> > - if (IS_CANNONLAKE(dev_priv)) {
> > + if (INTEL_GEN(dev_priv) >= 10) {
> > source_rates = cnl_rates;
> > size = ARRAY_SIZE(cnl_rates);
> > - max_rate = cnl_max_source_rate(intel_dp);
> > + if (IS_ICELAKE(dev_priv))
> > + max_rate = icl_max_source_rate(intel_dp);
> > + else
> > + max_rate = cnl_max_source_rate(intel_dp);
Bikeshed: changing this to "if (IS_CANNONLAKE())" would help ensuring
any possible future platform would be using the ICL table instead of
the CNL one.
> > } else if (IS_GEN9_LP(dev_priv)) {
> > source_rates = bxt_rates;
> > size = ARRAY_SIZE(bxt_rates);
> > --
> > 2.14.3
> >
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake
2018-06-01 23:43 ` Paulo Zanoni
@ 2018-06-14 19:24 ` Rodrigo Vivi
2018-06-15 0:45 ` Manasi Navare
0 siblings, 1 reply; 127+ messages in thread
From: Rodrigo Vivi @ 2018-06-14 19:24 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Fri, Jun 01, 2018 at 04:43:26PM -0700, Paulo Zanoni wrote:
> Em Sex, 2018-05-25 às 11:32 -0700, James Ausmus escreveu:
> > On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > > From: Manasi Navare <manasi.d.navare@intel.com>
> > >
> > > For ICL, on Combo PHY the allowed max rates are:
> > > - HBR3 8.1 eDP (DDIA)
> > > - HBR2 5.4 DisplayPort (DDIB)
> > > and for MG PHY/TC DDI Ports allowed DP rates are:
> > > - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> > > - DP on legacy connector - DDIC/D/E/F)
> > >
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > Cc: James Ausmus <james.ausmus@intel.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > Signed-off-by: James Ausmus <james.ausmus@intel.com>
> >
> > Reviewed-by: James Ausmus <james.ausmus@intel.com>
> >
> > > ---
> > > drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
> > > 1 file changed, 19 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 5109023abe28..3ee8e74cf2b8 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp
> > > *intel_dp)
> > > return 810000;
> > > }
> > >
> > > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > > +{
> > > + struct intel_digital_port *dig_port =
> > > dp_to_dig_port(intel_dp);
> > > + enum port port = dig_port->base.port;
> > > +
> > > + /* On Combo PHY port A max speed is HBR3 for all Vccio
> > > voltages
> > > + * and on Combo PHY Port B the maximum supported is HBR2.
> > > + */
> > > + if (port == PORT_B)
> > > + return 540000;
> > > +
> > > + return 810000;
> > > +}
> > > +
> > > static void
> > > intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > > {
> > > @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp
> > > *intel_dp)
> > > /* This should only be done once */
> > > WARN_ON(intel_dp->source_rates || intel_dp-
> > > >num_source_rates);
> > >
> > > - if (IS_CANNONLAKE(dev_priv)) {
> > > + if (INTEL_GEN(dev_priv) >= 10) {
> > > source_rates = cnl_rates;
> > > size = ARRAY_SIZE(cnl_rates);
> > > - max_rate = cnl_max_source_rate(intel_dp);
> > > + if (IS_ICELAKE(dev_priv))
> > > + max_rate = icl_max_source_rate(intel_dp);
> > > + else
> > > + max_rate = cnl_max_source_rate(intel_dp);
>
> Bikeshed: changing this to "if (IS_CANNONLAKE())" would help ensuring
> any possible future platform would be using the ICL table instead of
> the CNL one.
I agree... but I'd prefer s/IS_ICELAKE/gen >= 11
>
>
> > > } else if (IS_GEN9_LP(dev_priv)) {
> > > source_rates = bxt_rates;
> > > size = ARRAY_SIZE(bxt_rates);
> > > --
> > > 2.14.3
> > >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake
2018-06-14 19:24 ` Rodrigo Vivi
@ 2018-06-15 0:45 ` Manasi Navare
2018-06-15 5:20 ` Rodrigo Vivi
0 siblings, 1 reply; 127+ messages in thread
From: Manasi Navare @ 2018-06-15 0:45 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Paulo Zanoni
On Thu, Jun 14, 2018 at 12:24:32PM -0700, Rodrigo Vivi wrote:
> On Fri, Jun 01, 2018 at 04:43:26PM -0700, Paulo Zanoni wrote:
> > Em Sex, 2018-05-25 às 11:32 -0700, James Ausmus escreveu:
> > > On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > > > From: Manasi Navare <manasi.d.navare@intel.com>
> > > >
> > > > For ICL, on Combo PHY the allowed max rates are:
> > > > - HBR3 8.1 eDP (DDIA)
> > > > - HBR2 5.4 DisplayPort (DDIB)
> > > > and for MG PHY/TC DDI Ports allowed DP rates are:
> > > > - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> > > > - DP on legacy connector - DDIC/D/E/F)
> > > >
> > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > > Cc: James Ausmus <james.ausmus@intel.com>
> > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > > Signed-off-by: James Ausmus <james.ausmus@intel.com>
> > >
> > > Reviewed-by: James Ausmus <james.ausmus@intel.com>
> > >
> > > > ---
> > > > drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
> > > > 1 file changed, 19 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > index 5109023abe28..3ee8e74cf2b8 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp
> > > > *intel_dp)
> > > > return 810000;
> > > > }
> > > >
> > > > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > > > +{
> > > > + struct intel_digital_port *dig_port =
> > > > dp_to_dig_port(intel_dp);
> > > > + enum port port = dig_port->base.port;
> > > > +
> > > > + /* On Combo PHY port A max speed is HBR3 for all Vccio
> > > > voltages
> > > > + * and on Combo PHY Port B the maximum supported is HBR2.
> > > > + */
> > > > + if (port == PORT_B)
> > > > + return 540000;
> > > > +
> > > > + return 810000;
> > > > +}
> > > > +
> > > > static void
> > > > intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > > > {
> > > > @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp
> > > > *intel_dp)
> > > > /* This should only be done once */
> > > > WARN_ON(intel_dp->source_rates || intel_dp-
> > > > >num_source_rates);
> > > >
> > > > - if (IS_CANNONLAKE(dev_priv)) {
> > > > + if (INTEL_GEN(dev_priv) >= 10) {
> > > > source_rates = cnl_rates;
> > > > size = ARRAY_SIZE(cnl_rates);
> > > > - max_rate = cnl_max_source_rate(intel_dp);
> > > > + if (IS_ICELAKE(dev_priv))
> > > > + max_rate = icl_max_source_rate(intel_dp);
> > > > + else
> > > > + max_rate = cnl_max_source_rate(intel_dp);
> >
> > Bikeshed: changing this to "if (IS_CANNONLAKE())" would help ensuring
> > any possible future platform would be using the ICL table instead of
> > the CNL one.
>
> I agree... but I'd prefer s/IS_ICELAKE/gen >= 11
Ok, so remove IS_CANNONLAKE and only have the code for Gen >=11 right?
So remove the cnl_max_source_rate also?
Regards
Manasi
>
> >
> >
> > > > } else if (IS_GEN9_LP(dev_priv)) {
> > > > source_rates = bxt_rates;
> > > > size = ARRAY_SIZE(bxt_rates);
> > > > --
> > > > 2.14.3
> > > >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake
2018-06-15 0:45 ` Manasi Navare
@ 2018-06-15 5:20 ` Rodrigo Vivi
0 siblings, 0 replies; 127+ messages in thread
From: Rodrigo Vivi @ 2018-06-15 5:20 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx, Paulo Zanoni
On Thu, Jun 14, 2018 at 05:45:03PM -0700, Manasi Navare wrote:
> On Thu, Jun 14, 2018 at 12:24:32PM -0700, Rodrigo Vivi wrote:
> > On Fri, Jun 01, 2018 at 04:43:26PM -0700, Paulo Zanoni wrote:
> > > Em Sex, 2018-05-25 às 11:32 -0700, James Ausmus escreveu:
> > > > On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > > > > From: Manasi Navare <manasi.d.navare@intel.com>
> > > > >
> > > > > For ICL, on Combo PHY the allowed max rates are:
> > > > > - HBR3 8.1 eDP (DDIA)
> > > > > - HBR2 5.4 DisplayPort (DDIB)
> > > > > and for MG PHY/TC DDI Ports allowed DP rates are:
> > > > > - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> > > > > - DP on legacy connector - DDIC/D/E/F)
> > > > >
> > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > > > Cc: James Ausmus <james.ausmus@intel.com>
> > > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > > > Signed-off-by: James Ausmus <james.ausmus@intel.com>
> > > >
> > > > Reviewed-by: James Ausmus <james.ausmus@intel.com>
> > > >
> > > > > ---
> > > > > drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
> > > > > 1 file changed, 19 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > > index 5109023abe28..3ee8e74cf2b8 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > > @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp
> > > > > *intel_dp)
> > > > > return 810000;
> > > > > }
> > > > >
> > > > > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > > > > +{
> > > > > + struct intel_digital_port *dig_port =
> > > > > dp_to_dig_port(intel_dp);
> > > > > + enum port port = dig_port->base.port;
> > > > > +
> > > > > + /* On Combo PHY port A max speed is HBR3 for all Vccio
> > > > > voltages
> > > > > + * and on Combo PHY Port B the maximum supported is HBR2.
> > > > > + */
> > > > > + if (port == PORT_B)
> > > > > + return 540000;
> > > > > +
> > > > > + return 810000;
> > > > > +}
> > > > > +
> > > > > static void
> > > > > intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > > > > {
> > > > > @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp
> > > > > *intel_dp)
> > > > > /* This should only be done once */
> > > > > WARN_ON(intel_dp->source_rates || intel_dp-
> > > > > >num_source_rates);
> > > > >
> > > > > - if (IS_CANNONLAKE(dev_priv)) {
> > > > > + if (INTEL_GEN(dev_priv) >= 10) {
> > > > > source_rates = cnl_rates;
> > > > > size = ARRAY_SIZE(cnl_rates);
> > > > > - max_rate = cnl_max_source_rate(intel_dp);
> > > > > + if (IS_ICELAKE(dev_priv))
> > > > > + max_rate = icl_max_source_rate(intel_dp);
> > > > > + else
> > > > > + max_rate = cnl_max_source_rate(intel_dp);
> > >
> > > Bikeshed: changing this to "if (IS_CANNONLAKE())" would help ensuring
> > > any possible future platform would be using the ICL table instead of
> > > the CNL one.
> >
> > I agree... but I'd prefer s/IS_ICELAKE/gen >= 11
>
> Ok, so remove IS_CANNONLAKE and only have the code for Gen >=11 right?
> So remove the cnl_max_source_rate also?
No no, the rest of the patch is okay and should stay...
only instead of IS_ICELAKE you use gen >= 11
>
> Regards
> Manasi
>
> >
> > >
> > >
> > > > > } else if (IS_GEN9_LP(dev_priv)) {
> > > > > source_rates = bxt_rates;
> > > > > size = ARRAY_SIZE(bxt_rates);
> > > > > --
> > > > > 2.14.3
> > > > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake
2018-05-24 23:42 ` [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake Paulo Zanoni
2018-05-25 18:32 ` James Ausmus
@ 2018-06-14 19:23 ` Rodrigo Vivi
2018-06-19 20:39 ` Manasi Navare
1 sibling, 1 reply; 127+ messages in thread
From: Rodrigo Vivi @ 2018-06-14 19:23 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> From: Manasi Navare <manasi.d.navare@intel.com>
>
> For ICL, on Combo PHY the allowed max rates are:
> - HBR3 8.1 eDP (DDIA)
> - HBR2 5.4 DisplayPort (DDIB)
> and for MG PHY/TC DDI Ports allowed DP rates are:
> - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> - DP on legacy connector - DDIC/D/E/F)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5109023abe28..3ee8e74cf2b8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
> return 810000;
> }
>
> +static int icl_max_source_rate(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum port port = dig_port->base.port;
> +
> + /* On Combo PHY port A max speed is HBR3 for all Vccio voltages
> + * and on Combo PHY Port B the maximum supported is HBR2.
> + */
> + if (port == PORT_B)
A more generic way here would be COMBO and !eDP
> + return 540000;
> +
> + return 810000;
> +}
> +
> static void
> intel_dp_set_source_rates(struct intel_dp *intel_dp)
> {
> @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> /* This should only be done once */
> WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
>
> - if (IS_CANNONLAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 10) {
> source_rates = cnl_rates;
> size = ARRAY_SIZE(cnl_rates);
> - max_rate = cnl_max_source_rate(intel_dp);
> + if (IS_ICELAKE(dev_priv))
and gen >= 11
but changes can be in follow-up work, so
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> + max_rate = icl_max_source_rate(intel_dp);
> + else
> + max_rate = cnl_max_source_rate(intel_dp);
> } else if (IS_GEN9_LP(dev_priv)) {
> source_rates = bxt_rates;
> size = ARRAY_SIZE(bxt_rates);
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake
2018-06-14 19:23 ` Rodrigo Vivi
@ 2018-06-19 20:39 ` Manasi Navare
0 siblings, 0 replies; 127+ messages in thread
From: Manasi Navare @ 2018-06-19 20:39 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Paulo Zanoni
On Thu, Jun 14, 2018 at 12:23:36PM -0700, Rodrigo Vivi wrote:
> On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > From: Manasi Navare <manasi.d.navare@intel.com>
> >
> > For ICL, on Combo PHY the allowed max rates are:
> > - HBR3 8.1 eDP (DDIA)
> > - HBR2 5.4 DisplayPort (DDIB)
> > and for MG PHY/TC DDI Ports allowed DP rates are:
> > - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> > - DP on legacy connector - DDIC/D/E/F)
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: James Ausmus <james.ausmus@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
> > 1 file changed, 19 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 5109023abe28..3ee8e74cf2b8 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
> > return 810000;
> > }
> >
> > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > +{
> > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > + enum port port = dig_port->base.port;
> > +
> > + /* On Combo PHY port A max speed is HBR3 for all Vccio voltages
> > + * and on Combo PHY Port B the maximum supported is HBR2.
> > + */
> > + if (port == PORT_B)
>
> A more generic way here would be COMBO and !eDP
Yes I can use the function intel_is_port_combophy() but I dont see that merged yet
Will have to wait to spin this patch in that case.
>
> > + return 540000;
> > +
> > + return 810000;
> > +}
> > +
> > static void
> > intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > {
> > @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > /* This should only be done once */
> > WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
> >
> > - if (IS_CANNONLAKE(dev_priv)) {
> > + if (INTEL_GEN(dev_priv) >= 10) {
> > source_rates = cnl_rates;
> > size = ARRAY_SIZE(cnl_rates);
> > - max_rate = cnl_max_source_rate(intel_dp);
> > + if (IS_ICELAKE(dev_priv))
>
> and gen >= 11
>
> but changes can be in follow-up work, so
Yes will change that to use >= 11
Manasi
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> > + max_rate = icl_max_source_rate(intel_dp);
> > + else
> > + max_rate = cnl_max_source_rate(intel_dp);
> > } else if (IS_GEN9_LP(dev_priv)) {
> > source_rates = bxt_rates;
> > size = ARRAY_SIZE(bxt_rates);
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 27/24] drm/i915/dp: Add support for HBR3 and TPS4 during link training
2018-05-24 23:42 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Paulo Zanoni
2018-05-24 23:42 ` [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake Paulo Zanoni
@ 2018-05-24 23:42 ` Paulo Zanoni
2018-05-25 18:41 ` James Ausmus
2018-05-24 23:42 ` [PATCH 28/24] drm/i915/icl: implement DVFS for ICL Paulo Zanoni
` (4 subsequent siblings)
6 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-24 23:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Manasi Navare <manasi.d.navare@intel.com>
DP spec 1.4 supports training pattern set 4 (TPS4) for HBR3 link
rate. This will be used in link training's channel equalization
phase if supported by both source and sink.
This patch adds the helpers to check if HBR3 is supported and uses
TPS4 in training pattern selection during link training.
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 17 +++++++++---
drivers/gpu/drm/i915/intel_dp_link_training.c | 39 +++++++++++++++++++--------
drivers/gpu/drm/i915/intel_drv.h | 1 +
4 files changed, 44 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e48b717769b2..ae7070c0806d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8791,6 +8791,7 @@ enum skl_power_gate {
#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
+#define DP_TP_CTL_LINK_TRAIN_PAT4 (5<<8)
#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3ee8e74cf2b8..bcc3f330b301 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1721,6 +1721,13 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
return max_rate >= 540000;
}
+bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
+{
+ int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
+
+ return max_rate >= 810000;
+}
+
static void
intel_dp_set_clock(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
@@ -3046,10 +3053,11 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
enum port port = intel_dig_port->base.port;
+ uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
- if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
+ if (dp_train_pat & train_pat_mask)
DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
- dp_train_pat & DP_TRAINING_PATTERN_MASK);
+ dp_train_pat & train_pat_mask);
if (HAS_DDI(dev_priv)) {
uint32_t temp = I915_READ(DP_TP_CTL(port));
@@ -3060,7 +3068,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
- switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
+ switch (dp_train_pat & train_pat_mask) {
case DP_TRAINING_PATTERN_DISABLE:
temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
@@ -3074,6 +3082,9 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
case DP_TRAINING_PATTERN_3:
temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
break;
+ case DP_TRAINING_PATTERN_4:
+ temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
+ break;
}
I915_WRITE(DP_TP_CTL(port), temp);
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 3fcaa98b9055..4da6e33c7fa1 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -219,14 +219,30 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
}
/*
- * Pick training pattern for channel equalization. Training Pattern 3 for HBR2
+ * Pick training pattern for channel equalization. Training pattern 4 for HBR3
+ * or for 1.4 devices that support it, training Pattern 3 for HBR2
* or 1.2 devices that support it, Training Pattern 2 otherwise.
*/
static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
{
- u32 training_pattern = DP_TRAINING_PATTERN_2;
- bool source_tps3, sink_tps3;
+ bool source_tps3, sink_tps3, source_tps4, sink_tps4;
+ /*
+ * Intel platforms that support HBR3 also support TPS4. It is mandatory
+ * for all downstream devices that support HBR3. There are no known eDP
+ * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
+ * specification.
+ */
+ source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
+ sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
+ if (source_tps4 && sink_tps4) {
+ return DP_TRAINING_PATTERN_4;
+ } else if (intel_dp->link_rate == 810000) {
+ if (!source_tps4)
+ DRM_DEBUG_KMS("8.1 Gbps link rate without source HBR3/TPS4 support\n");
+ if (!sink_tps4)
+ DRM_DEBUG_KMS("8.1 Gbps link rate without sink TPS4 support\n");
+ }
/*
* Intel platforms that support HBR2 also support TPS3. TPS3 support is
* also mandatory for downstream devices that support HBR2. However, not
@@ -234,17 +250,16 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
*/
source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
-
if (source_tps3 && sink_tps3) {
- training_pattern = DP_TRAINING_PATTERN_3;
- } else if (intel_dp->link_rate == 540000) {
+ return DP_TRAINING_PATTERN_3;
+ } else if (intel_dp->link_rate >= 540000) {
if (!source_tps3)
- DRM_DEBUG_KMS("5.4 Gbps link rate without source HBR2/TPS3 support\n");
+ DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
if (!sink_tps3)
- DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
+ DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
}
- return training_pattern;
+ return DP_TRAINING_PATTERN_2;
}
static bool
@@ -256,11 +271,13 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
bool channel_eq = false;
training_pattern = intel_dp_training_pattern(intel_dp);
+ /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
+ if (training_pattern != DP_TRAINING_PATTERN_4)
+ training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
/* channel equalization */
if (!intel_dp_set_link_train(intel_dp,
- training_pattern |
- DP_LINK_SCRAMBLING_DISABLE)) {
+ training_pattern)) {
DRM_ERROR("failed to start channel equalization\n");
return false;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e3c2419301b4..c97a7ab3a2b1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1718,6 +1718,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
uint8_t *link_bw, uint8_t *rate_select);
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
+bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
bool
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
--
2.14.3
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 27/24] drm/i915/dp: Add support for HBR3 and TPS4 during link training
2018-05-24 23:42 ` [PATCH 27/24] drm/i915/dp: Add support for HBR3 and TPS4 during link training Paulo Zanoni
@ 2018-05-25 18:41 ` James Ausmus
0 siblings, 0 replies; 127+ messages in thread
From: James Ausmus @ 2018-05-25 18:41 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Rodrigo Vivi
On Thu, May 24, 2018 at 04:42:38PM -0700, Paulo Zanoni wrote:
> From: Manasi Navare <manasi.d.navare@intel.com>
>
> DP spec 1.4 supports training pattern set 4 (TPS4) for HBR3 link
> rate. This will be used in link training's channel equalization
> phase if supported by both source and sink.
> This patch adds the helpers to check if HBR3 is supported and uses
> TPS4 in training pattern selection during link training.
>
> Cc: James Ausmus <james.ausmus@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 17 +++++++++---
> drivers/gpu/drm/i915/intel_dp_link_training.c | 39 +++++++++++++++++++--------
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 4 files changed, 44 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e48b717769b2..ae7070c0806d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8791,6 +8791,7 @@ enum skl_power_gate {
> #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
> #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
> #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
> +#define DP_TP_CTL_LINK_TRAIN_PAT4 (5<<8)
> #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
> #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
> #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3ee8e74cf2b8..bcc3f330b301 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1721,6 +1721,13 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
> return max_rate >= 540000;
> }
>
> +bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
> +{
> + int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
> +
> + return max_rate >= 810000;
> +}
> +
> static void
> intel_dp_set_clock(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> @@ -3046,10 +3053,11 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> enum port port = intel_dig_port->base.port;
> + uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
>
> - if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
> + if (dp_train_pat & train_pat_mask)
> DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
> - dp_train_pat & DP_TRAINING_PATTERN_MASK);
> + dp_train_pat & train_pat_mask);
>
> if (HAS_DDI(dev_priv)) {
> uint32_t temp = I915_READ(DP_TP_CTL(port));
> @@ -3060,7 +3068,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
>
> temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> - switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> + switch (dp_train_pat & train_pat_mask) {
> case DP_TRAINING_PATTERN_DISABLE:
> temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
>
> @@ -3074,6 +3082,9 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> case DP_TRAINING_PATTERN_3:
> temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
> break;
> + case DP_TRAINING_PATTERN_4:
> + temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
> + break;
> }
> I915_WRITE(DP_TP_CTL(port), temp);
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 3fcaa98b9055..4da6e33c7fa1 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -219,14 +219,30 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
> }
>
> /*
> - * Pick training pattern for channel equalization. Training Pattern 3 for HBR2
> + * Pick training pattern for channel equalization. Training pattern 4 for HBR3
> + * or for 1.4 devices that support it, training Pattern 3 for HBR2
> * or 1.2 devices that support it, Training Pattern 2 otherwise.
> */
> static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
> {
> - u32 training_pattern = DP_TRAINING_PATTERN_2;
> - bool source_tps3, sink_tps3;
> + bool source_tps3, sink_tps3, source_tps4, sink_tps4;
>
> + /*
> + * Intel platforms that support HBR3 also support TPS4. It is mandatory
> + * for all downstream devices that support HBR3. There are no known eDP
> + * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
> + * specification.
> + */
> + source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
> + sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
> + if (source_tps4 && sink_tps4) {
> + return DP_TRAINING_PATTERN_4;
> + } else if (intel_dp->link_rate == 810000) {
> + if (!source_tps4)
> + DRM_DEBUG_KMS("8.1 Gbps link rate without source HBR3/TPS4 support\n");
> + if (!sink_tps4)
> + DRM_DEBUG_KMS("8.1 Gbps link rate without sink TPS4 support\n");
> + }
> /*
> * Intel platforms that support HBR2 also support TPS3. TPS3 support is
> * also mandatory for downstream devices that support HBR2. However, not
> @@ -234,17 +250,16 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
> */
> source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
> sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
> -
> if (source_tps3 && sink_tps3) {
> - training_pattern = DP_TRAINING_PATTERN_3;
> - } else if (intel_dp->link_rate == 540000) {
> + return DP_TRAINING_PATTERN_3;
> + } else if (intel_dp->link_rate >= 540000) {
> if (!source_tps3)
> - DRM_DEBUG_KMS("5.4 Gbps link rate without source HBR2/TPS3 support\n");
> + DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
> if (!sink_tps3)
> - DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
> + DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
> }
>
> - return training_pattern;
> + return DP_TRAINING_PATTERN_2;
> }
>
> static bool
> @@ -256,11 +271,13 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
> bool channel_eq = false;
>
> training_pattern = intel_dp_training_pattern(intel_dp);
> + /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
> + if (training_pattern != DP_TRAINING_PATTERN_4)
> + training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
>
> /* channel equalization */
> if (!intel_dp_set_link_train(intel_dp,
> - training_pattern |
> - DP_LINK_SCRAMBLING_DISABLE)) {
> + training_pattern)) {
> DRM_ERROR("failed to start channel equalization\n");
> return false;
> }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index e3c2419301b4..c97a7ab3a2b1 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1718,6 +1718,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
> void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> uint8_t *link_bw, uint8_t *rate_select);
> bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
> +bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
> bool
> intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
>
> --
> 2.14.3
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 28/24] drm/i915/icl: implement DVFS for ICL
2018-05-24 23:42 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Paulo Zanoni
2018-05-24 23:42 ` [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake Paulo Zanoni
2018-05-24 23:42 ` [PATCH 27/24] drm/i915/dp: Add support for HBR3 and TPS4 during link training Paulo Zanoni
@ 2018-05-24 23:42 ` Paulo Zanoni
2018-06-14 19:47 ` Rodrigo Vivi
2018-05-24 23:42 ` [PATCH 29/24] drm/i915/icl: DP_AUX_E is valid on ICL+ Paulo Zanoni
` (3 subsequent siblings)
6 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-24 23:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
ICL DVFS is almost the same as CNL, except for the CDCLK/DDICLK
table. Implement it just like CNL does.
References: commit 48469eced282 ("drm/i915: Use cdclk_state->voltage
on CNL")
References: commit 53e9bf5e8159 ("drm/i915: Adjust system agent
voltage on CNL if required by DDI ports")
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 46 +++++++++++++++++++++++++++++++++++---
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
2 files changed, 45 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 704ddb4d3ca7..642f1e542a62 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1861,11 +1861,35 @@ static void icl_set_cdclk(struct drm_i915_private *dev_priv,
skl_cdclk_decimal(cdclk));
mutex_lock(&dev_priv->pcu_lock);
- /* TODO: add proper DVFS support. */
- sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 2);
+ sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ cdclk_state->voltage_level);
mutex_unlock(&dev_priv->pcu_lock);
intel_update_cdclk(dev_priv);
+
+ /*
+ * Can't read out the voltage level :(
+ * Let's just assume everything is as expected.
+ */
+ dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
+}
+
+static u8 icl_calc_voltage_level(int cdclk)
+{
+ switch (cdclk) {
+ case 50000:
+ case 307200:
+ case 312000:
+ return 0;
+ case 556800:
+ case 552000:
+ return 1;
+ default:
+ MISSING_CASE(cdclk);
+ case 652800:
+ case 648000:
+ return 2;
+ }
}
static void icl_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1899,7 +1923,7 @@ static void icl_get_cdclk(struct drm_i915_private *dev_priv,
*/
cdclk_state->vco = 0;
cdclk_state->cdclk = cdclk_state->bypass;
- return;
+ goto out;
}
cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
@@ -1908,6 +1932,14 @@ static void icl_get_cdclk(struct drm_i915_private *dev_priv,
WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
cdclk_state->cdclk = cdclk_state->vco / 2;
+
+out:
+ /*
+ * Can't read this out :( Let's assume it's
+ * at least what the CDCLK frequency requires.
+ */
+ cdclk_state->voltage_level =
+ icl_calc_voltage_level(cdclk_state->cdclk);
}
/**
@@ -1950,6 +1982,8 @@ void icl_init_cdclk(struct drm_i915_private *dev_priv)
sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
sanitized_state.cdclk);
+ sanitized_state.voltage_level =
+ icl_calc_voltage_level(sanitized_state.cdclk);
icl_set_cdclk(dev_priv, &sanitized_state);
}
@@ -1967,6 +2001,7 @@ void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
cdclk_state.cdclk = cdclk_state.bypass;
cdclk_state.vco = 0;
+ cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
icl_set_cdclk(dev_priv, &cdclk_state);
}
@@ -2470,6 +2505,9 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
intel_state->cdclk.logical.vco = vco;
intel_state->cdclk.logical.cdclk = cdclk;
+ intel_state->cdclk.logical.voltage_level =
+ max(icl_calc_voltage_level(cdclk),
+ cnl_compute_min_voltage_level(intel_state));
if (!intel_state->active_crtcs) {
cdclk = icl_calc_cdclk(0, ref);
@@ -2477,6 +2515,8 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
intel_state->cdclk.actual.vco = vco;
intel_state->cdclk.actual.cdclk = cdclk;
+ intel_state->cdclk.actual.voltage_level =
+ icl_calc_voltage_level(cdclk);
} else {
intel_state->cdclk.actual = intel_state->cdclk.logical;
}
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 610c2d7d499c..6cdcbf9bf098 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3073,6 +3073,8 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
{
if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
crtc_state->min_voltage_level = 2;
+ else if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
+ crtc_state->min_voltage_level = 1;
}
void intel_ddi_get_config(struct intel_encoder *encoder,
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 28/24] drm/i915/icl: implement DVFS for ICL
2018-05-24 23:42 ` [PATCH 28/24] drm/i915/icl: implement DVFS for ICL Paulo Zanoni
@ 2018-06-14 19:47 ` Rodrigo Vivi
0 siblings, 0 replies; 127+ messages in thread
From: Rodrigo Vivi @ 2018-06-14 19:47 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Thu, May 24, 2018 at 04:42:39PM -0700, Paulo Zanoni wrote:
> ICL DVFS is almost the same as CNL, except for the CDCLK/DDICLK
> table. Implement it just like CNL does.
>
> References: commit 48469eced282 ("drm/i915: Use cdclk_state->voltage
> on CNL")
> References: commit 53e9bf5e8159 ("drm/i915: Adjust system agent
> voltage on CNL if required by DDI ports")
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 46 +++++++++++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/intel_ddi.c | 2 ++
> 2 files changed, 45 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 704ddb4d3ca7..642f1e542a62 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1861,11 +1861,35 @@ static void icl_set_cdclk(struct drm_i915_private *dev_priv,
> skl_cdclk_decimal(cdclk));
>
> mutex_lock(&dev_priv->pcu_lock);
> - /* TODO: add proper DVFS support. */
> - sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 2);
> + sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> + cdclk_state->voltage_level);
> mutex_unlock(&dev_priv->pcu_lock);
>
> intel_update_cdclk(dev_priv);
> +
> + /*
> + * Can't read out the voltage level :(
> + * Let's just assume everything is as expected.
> + */
> + dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
> +}
> +
> +static u8 icl_calc_voltage_level(int cdclk)
> +{
> + switch (cdclk) {
> + case 50000:
> + case 307200:
> + case 312000:
> + return 0;
> + case 556800:
> + case 552000:
> + return 1;
> + default:
> + MISSING_CASE(cdclk);
> + case 652800:
> + case 648000:
> + return 2;
> + }
> }
>
> static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> @@ -1899,7 +1923,7 @@ static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> */
> cdclk_state->vco = 0;
> cdclk_state->cdclk = cdclk_state->bypass;
> - return;
> + goto out;
> }
>
> cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
> @@ -1908,6 +1932,14 @@ static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
>
> cdclk_state->cdclk = cdclk_state->vco / 2;
> +
> +out:
> + /*
> + * Can't read this out :( Let's assume it's
> + * at least what the CDCLK frequency requires.
> + */
> + cdclk_state->voltage_level =
> + icl_calc_voltage_level(cdclk_state->cdclk);
> }
>
> /**
> @@ -1950,6 +1982,8 @@ void icl_init_cdclk(struct drm_i915_private *dev_priv)
> sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
> sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
> sanitized_state.cdclk);
> + sanitized_state.voltage_level =
> + icl_calc_voltage_level(sanitized_state.cdclk);
>
> icl_set_cdclk(dev_priv, &sanitized_state);
> }
> @@ -1967,6 +2001,7 @@ void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> cdclk_state.cdclk = cdclk_state.bypass;
> cdclk_state.vco = 0;
> + cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
>
> icl_set_cdclk(dev_priv, &cdclk_state);
> }
> @@ -2470,6 +2505,9 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
>
> intel_state->cdclk.logical.vco = vco;
> intel_state->cdclk.logical.cdclk = cdclk;
> + intel_state->cdclk.logical.voltage_level =
> + max(icl_calc_voltage_level(cdclk),
> + cnl_compute_min_voltage_level(intel_state));
>
> if (!intel_state->active_crtcs) {
> cdclk = icl_calc_cdclk(0, ref);
> @@ -2477,6 +2515,8 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
>
> intel_state->cdclk.actual.vco = vco;
> intel_state->cdclk.actual.cdclk = cdclk;
> + intel_state->cdclk.actual.voltage_level =
> + icl_calc_voltage_level(cdclk);
> } else {
> intel_state->cdclk.actual = intel_state->cdclk.logical;
> }
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 610c2d7d499c..6cdcbf9bf098 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3073,6 +3073,8 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
> {
> if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
> crtc_state->min_voltage_level = 2;
> + else if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
> + crtc_state->min_voltage_level = 1;
> }
>
> void intel_ddi_get_config(struct intel_encoder *encoder,
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 29/24] drm/i915/icl: DP_AUX_E is valid on ICL+
2018-05-24 23:42 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Paulo Zanoni
` (2 preceding siblings ...)
2018-05-24 23:42 ` [PATCH 28/24] drm/i915/icl: implement DVFS for ICL Paulo Zanoni
@ 2018-05-24 23:42 ` Paulo Zanoni
2018-05-25 0:12 ` Paulo Zanoni
2018-05-24 23:42 ` [PATCH 30/24] drm/i915/icl: update VBT's child_device_config flags2 field Paulo Zanoni
` (2 subsequent siblings)
6 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-24 23:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi, Paulo Zanoni
From: James Ausmus <james.ausmus@intel.com>
Add support for DP_AUX_E. Here we also introduce the bits for the AUX
power well E, however ICL power well support is still not enabled yet,
so the power well is not used.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
drivers/gpu/drm/i915/intel_display.h | 3 ++-
drivers/gpu/drm/i915/intel_dp.c | 7 +++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
6 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b86ed6401120..a85329f053dc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1005,6 +1005,7 @@ enum modeset_restore {
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30
+#define DP_AUX_E 0x50
#define DP_AUX_F 0x60
#define DDC_PIN_B 0x05
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9f1b01ca4ed1..672bfaf2052a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2783,6 +2783,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
+ if (INTEL_GEN(dev_priv) >= 11)
+ tmp_mask |= ICL_AUX_CHANNEL_E;
+
if (IS_CNL_WITH_PORT_F(dev_priv) ||
INTEL_GEN(dev_priv) >= 11)
tmp_mask |= CNL_AUX_CHANNEL_F;
@@ -4168,6 +4171,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
}
+ if (INTEL_GEN(dev_priv) >= 11)
+ de_port_masked |= ICL_AUX_CHANNEL_E;
+
if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11)
de_port_masked |= CNL_AUX_CHANNEL_F;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ae7070c0806d..ba5285348534 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5342,6 +5342,13 @@ enum {
#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
+#define _DPE_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64410)
+#define _DPE_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64414)
+#define _DPE_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64418)
+#define _DPE_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6441c)
+#define _DPE_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64420)
+#define _DPE_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64424)
+
#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
@@ -7040,6 +7047,7 @@ enum {
#define GEN8_DE_PORT_IMR _MMIO(0x44444)
#define GEN8_DE_PORT_IIR _MMIO(0x44448)
#define GEN8_DE_PORT_IER _MMIO(0x4444c)
+#define ICL_AUX_CHANNEL_E (1 << 29)
#define CNL_AUX_CHANNEL_F (1 << 28)
#define GEN9_AUX_CHANNEL_D (1 << 27)
#define GEN9_AUX_CHANNEL_C (1 << 26)
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index fcedc600706b..653d85f8a374 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -162,7 +162,7 @@ enum aux_ch {
AUX_CH_B,
AUX_CH_C,
AUX_CH_D,
- _AUX_CH_E, /* does not exist */
+ AUX_CH_E, /* ICL+ */
AUX_CH_F,
};
@@ -203,6 +203,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
+ POWER_DOMAIN_AUX_E,
POWER_DOMAIN_AUX_F,
POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_GMBUS,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bcc3f330b301..588a5de3a8ee 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1527,6 +1527,9 @@ static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
case DP_AUX_D:
aux_ch = AUX_CH_D;
break;
+ case DP_AUX_E:
+ aux_ch = AUX_CH_E;
+ break;
case DP_AUX_F:
aux_ch = AUX_CH_F;
break;
@@ -1554,6 +1557,8 @@ intel_aux_power_domain(struct intel_dp *intel_dp)
return POWER_DOMAIN_AUX_C;
case AUX_CH_D:
return POWER_DOMAIN_AUX_D;
+ case AUX_CH_E:
+ return POWER_DOMAIN_AUX_E;
case AUX_CH_F:
return POWER_DOMAIN_AUX_F;
default:
@@ -1640,6 +1645,7 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
case AUX_CH_B:
case AUX_CH_C:
case AUX_CH_D:
+ case AUX_CH_E:
case AUX_CH_F:
return DP_AUX_CH_CTL(aux_ch);
default:
@@ -1658,6 +1664,7 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
case AUX_CH_B:
case AUX_CH_C:
case AUX_CH_D:
+ case AUX_CH_E:
case AUX_CH_F:
return DP_AUX_CH_DATA(aux_ch, index);
default:
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 53a6eaa9671a..0e4a631afc7d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -128,6 +128,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_C";
case POWER_DOMAIN_AUX_D:
return "AUX_D";
+ case POWER_DOMAIN_AUX_E:
+ return "AUX E";
case POWER_DOMAIN_AUX_F:
return "AUX_F";
case POWER_DOMAIN_AUX_IO_A:
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 29/24] drm/i915/icl: DP_AUX_E is valid on ICL+
2018-05-24 23:42 ` [PATCH 29/24] drm/i915/icl: DP_AUX_E is valid on ICL+ Paulo Zanoni
@ 2018-05-25 0:12 ` Paulo Zanoni
2018-06-11 23:01 ` Paulo Zanoni
0 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-25 0:12 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi, Dhinakaran Pandiyan
Em Qui, 2018-05-24 às 16:42 -0700, Paulo Zanoni escreveu:
> From: James Ausmus <james.ausmus@intel.com>
>
> Add support for DP_AUX_E. Here we also introduce the bits for the AUX
> power well E, however ICL power well support is still not enabled
> yet,
> so the power well is not used.
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> drivers/gpu/drm/i915/intel_display.h | 3 ++-
> drivers/gpu/drm/i915/intel_dp.c | 7 +++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
> 6 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index b86ed6401120..a85329f053dc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1005,6 +1005,7 @@ enum modeset_restore {
> #define DP_AUX_B 0x10
> #define DP_AUX_C 0x20
> #define DP_AUX_D 0x30
> +#define DP_AUX_E 0x50
> #define DP_AUX_F 0x60
>
> #define DDC_PIN_B 0x05
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 9f1b01ca4ed1..672bfaf2052a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2783,6 +2783,9 @@ gen8_de_irq_handler(struct drm_i915_private
> *dev_priv, u32 master_ctl)
> GEN9_AUX_CHANNEL_C |
> GEN9_AUX_CHANNEL_D;
>
> + if (INTEL_GEN(dev_priv) >= 11)
> + tmp_mask |= ICL_AUX_CHANNEL_E;
> +
> if (IS_CNL_WITH_PORT_F(dev_priv) ||
> INTEL_GEN(dev_priv) >= 11)
> tmp_mask |= CNL_AUX_CHANNEL_F;
> @@ -4168,6 +4171,9 @@ static void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
> de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> }
>
> + if (INTEL_GEN(dev_priv) >= 11)
> + de_port_masked |= ICL_AUX_CHANNEL_E;
> +
> if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >=
> 11)
> de_port_masked |= CNL_AUX_CHANNEL_F;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index ae7070c0806d..ba5285348534 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5342,6 +5342,13 @@ enum {
> #define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset
> + 0x64320)
> #define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset
> + 0x64324)
>
> +#define _DPE_AUX_CH_CTL (dev_priv-
> >info.display_mmio_offset + 0x64410)
> +#define _DPE_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset
> + 0x64414)
> +#define _DPE_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset
> + 0x64418)
> +#define _DPE_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset
> + 0x6441c)
> +#define _DPE_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset
> + 0x64420)
> +#define _DPE_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset
> + 0x64424)
> +
> #define _DPF_AUX_CH_CTL (dev_priv-
> >info.display_mmio_offset + 0x64510)
> #define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset
> + 0x64514)
> #define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset
> + 0x64518)
> @@ -7040,6 +7047,7 @@ enum {
> #define GEN8_DE_PORT_IMR _MMIO(0x44444)
> #define GEN8_DE_PORT_IIR _MMIO(0x44448)
> #define GEN8_DE_PORT_IER _MMIO(0x4444c)
> +#define ICL_AUX_CHANNEL_E (1 << 29)
> #define CNL_AUX_CHANNEL_F (1 << 28)
> #define GEN9_AUX_CHANNEL_D (1 << 27)
> #define GEN9_AUX_CHANNEL_C (1 << 26)
> diff --git a/drivers/gpu/drm/i915/intel_display.h
> b/drivers/gpu/drm/i915/intel_display.h
> index fcedc600706b..653d85f8a374 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -162,7 +162,7 @@ enum aux_ch {
> AUX_CH_B,
> AUX_CH_C,
> AUX_CH_D,
> - _AUX_CH_E, /* does not exist */
> + AUX_CH_E, /* ICL+ */
> AUX_CH_F,
> };
>
> @@ -203,6 +203,7 @@ enum intel_display_power_domain {
> POWER_DOMAIN_AUX_B,
> POWER_DOMAIN_AUX_C,
> POWER_DOMAIN_AUX_D,
> + POWER_DOMAIN_AUX_E,
> POWER_DOMAIN_AUX_F,
> POWER_DOMAIN_AUX_IO_A,
> POWER_DOMAIN_GMBUS,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index bcc3f330b301..588a5de3a8ee 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1527,6 +1527,9 @@ static enum aux_ch intel_aux_ch(struct intel_dp
> *intel_dp)
> case DP_AUX_D:
> aux_ch = AUX_CH_D;
> break;
> + case DP_AUX_E:
> + aux_ch = AUX_CH_E;
> + break;
> case DP_AUX_F:
> aux_ch = AUX_CH_F;
> break;
> @@ -1554,6 +1557,8 @@ intel_aux_power_domain(struct intel_dp
> *intel_dp)
> return POWER_DOMAIN_AUX_C;
> case AUX_CH_D:
> return POWER_DOMAIN_AUX_D;
> + case AUX_CH_E:
> + return POWER_DOMAIN_AUX_E;
> case AUX_CH_F:
> return POWER_DOMAIN_AUX_F;
> default:
> @@ -1640,6 +1645,7 @@ static i915_reg_t skl_aux_ctl_reg(struct
> intel_dp *intel_dp)
> case AUX_CH_B:
> case AUX_CH_C:
> case AUX_CH_D:
> + case AUX_CH_E:
> case AUX_CH_F:
> return DP_AUX_CH_CTL(aux_ch);
> default:
> @@ -1658,6 +1664,7 @@ static i915_reg_t skl_aux_data_reg(struct
> intel_dp *intel_dp, int index)
> case AUX_CH_B:
> case AUX_CH_C:
> case AUX_CH_D:
> + case AUX_CH_E:
> case AUX_CH_F:
> return DP_AUX_CH_DATA(aux_ch, index);
> default:
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 53a6eaa9671a..0e4a631afc7d 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -128,6 +128,8 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> return "AUX_C";
> case POWER_DOMAIN_AUX_D:
> return "AUX_D";
> + case POWER_DOMAIN_AUX_E:
> + return "AUX E";
This should be "AUX_E" instead of "AUX E" and I'm 100% sure it's an
error I introduced myself to the patch.
> case POWER_DOMAIN_AUX_F:
> return "AUX_F";
> case POWER_DOMAIN_AUX_IO_A:
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 29/24] drm/i915/icl: DP_AUX_E is valid on ICL+
2018-05-25 0:12 ` Paulo Zanoni
@ 2018-06-11 23:01 ` Paulo Zanoni
0 siblings, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-06-11 23:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
Em Qui, 2018-05-24 às 17:12 -0700, Paulo Zanoni escreveu:
> Em Qui, 2018-05-24 às 16:42 -0700, Paulo Zanoni escreveu:
> > From: James Ausmus <james.ausmus@intel.com>
> >
> > Add support for DP_AUX_E. Here we also introduce the bits for the
> > AUX
> > power well E, however ICL power well support is still not enabled
> > yet,
> > so the power well is not used.
> >
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: James Ausmus <james.ausmus@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
> > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> > drivers/gpu/drm/i915/intel_display.h | 3 ++-
> > drivers/gpu/drm/i915/intel_dp.c | 7 +++++++
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
> > 6 files changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index b86ed6401120..a85329f053dc 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1005,6 +1005,7 @@ enum modeset_restore {
> > #define DP_AUX_B 0x10
> > #define DP_AUX_C 0x20
> > #define DP_AUX_D 0x30
> > +#define DP_AUX_E 0x50
> > #define DP_AUX_F 0x60
> >
> > #define DDC_PIN_B 0x05
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 9f1b01ca4ed1..672bfaf2052a 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2783,6 +2783,9 @@ gen8_de_irq_handler(struct drm_i915_private
> > *dev_priv, u32 master_ctl)
> > GEN9_AUX_CHANNEL_C |
> > GEN9_AUX_CHANNEL_D;
> >
> > + if (INTEL_GEN(dev_priv) >= 11)
> > + tmp_mask |= ICL_AUX_CHANNEL_E;
> > +
> > if (IS_CNL_WITH_PORT_F(dev_priv) ||
> > INTEL_GEN(dev_priv) >= 11)
> > tmp_mask |= CNL_AUX_CHANNEL_F;
> > @@ -4168,6 +4171,9 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> > }
> >
> > + if (INTEL_GEN(dev_priv) >= 11)
> > + de_port_masked |= ICL_AUX_CHANNEL_E;
> > +
> > if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >=
> > 11)
> > de_port_masked |= CNL_AUX_CHANNEL_F;
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index ae7070c0806d..ba5285348534 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5342,6 +5342,13 @@ enum {
> > #define _DPD_AUX_CH_DATA4 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64320)
> > #define _DPD_AUX_CH_DATA5 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64324)
> >
> > +#define _DPE_AUX_CH_CTL (dev_priv-
> > > info.display_mmio_offset + 0x64410)
> >
> > +#define _DPE_AUX_CH_DATA1 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64414)
> > +#define _DPE_AUX_CH_DATA2 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64418)
> > +#define _DPE_AUX_CH_DATA3 (dev_priv-
> > >info.display_mmio_offset
> > + 0x6441c)
> > +#define _DPE_AUX_CH_DATA4 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64420)
> > +#define _DPE_AUX_CH_DATA5 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64424)
> > +
> > #define _DPF_AUX_CH_CTL (dev_priv-
> > > info.display_mmio_offset + 0x64510)
> >
> > #define _DPF_AUX_CH_DATA1 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64514)
> > #define _DPF_AUX_CH_DATA2 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64518)
> > @@ -7040,6 +7047,7 @@ enum {
> > #define GEN8_DE_PORT_IMR _MMIO(0x44444)
> > #define GEN8_DE_PORT_IIR _MMIO(0x44448)
> > #define GEN8_DE_PORT_IER _MMIO(0x4444c)
> > +#define ICL_AUX_CHANNEL_E (1 << 29)
> > #define CNL_AUX_CHANNEL_F (1 << 28)
> > #define GEN9_AUX_CHANNEL_D (1 << 27)
> > #define GEN9_AUX_CHANNEL_C (1 << 26)
> > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > b/drivers/gpu/drm/i915/intel_display.h
> > index fcedc600706b..653d85f8a374 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -162,7 +162,7 @@ enum aux_ch {
> > AUX_CH_B,
> > AUX_CH_C,
> > AUX_CH_D,
> > - _AUX_CH_E, /* does not exist */
> > + AUX_CH_E, /* ICL+ */
> > AUX_CH_F,
> > };
> >
> > @@ -203,6 +203,7 @@ enum intel_display_power_domain {
> > POWER_DOMAIN_AUX_B,
> > POWER_DOMAIN_AUX_C,
> > POWER_DOMAIN_AUX_D,
> > + POWER_DOMAIN_AUX_E,
> > POWER_DOMAIN_AUX_F,
> > POWER_DOMAIN_AUX_IO_A,
> > POWER_DOMAIN_GMBUS,
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index bcc3f330b301..588a5de3a8ee 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1527,6 +1527,9 @@ static enum aux_ch intel_aux_ch(struct
> > intel_dp
> > *intel_dp)
> > case DP_AUX_D:
> > aux_ch = AUX_CH_D;
> > break;
> > + case DP_AUX_E:
> > + aux_ch = AUX_CH_E;
> > + break;
> > case DP_AUX_F:
> > aux_ch = AUX_CH_F;
> > break;
> > @@ -1554,6 +1557,8 @@ intel_aux_power_domain(struct intel_dp
> > *intel_dp)
> > return POWER_DOMAIN_AUX_C;
> > case AUX_CH_D:
> > return POWER_DOMAIN_AUX_D;
> > + case AUX_CH_E:
> > + return POWER_DOMAIN_AUX_E;
> > case AUX_CH_F:
> > return POWER_DOMAIN_AUX_F;
> > default:
> > @@ -1640,6 +1645,7 @@ static i915_reg_t skl_aux_ctl_reg(struct
> > intel_dp *intel_dp)
> > case AUX_CH_B:
> > case AUX_CH_C:
> > case AUX_CH_D:
> > + case AUX_CH_E:
> > case AUX_CH_F:
> > return DP_AUX_CH_CTL(aux_ch);
> > default:
> > @@ -1658,6 +1664,7 @@ static i915_reg_t skl_aux_data_reg(struct
> > intel_dp *intel_dp, int index)
> > case AUX_CH_B:
> > case AUX_CH_C:
> > case AUX_CH_D:
> > + case AUX_CH_E:
> > case AUX_CH_F:
> > return DP_AUX_CH_DATA(aux_ch, index);
> > default:
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 53a6eaa9671a..0e4a631afc7d 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -128,6 +128,8 @@ intel_display_power_domain_str(enum
> > intel_display_power_domain domain)
> > return "AUX_C";
> > case POWER_DOMAIN_AUX_D:
> > return "AUX_D";
> > + case POWER_DOMAIN_AUX_E:
> > + return "AUX E";
>
> This should be "AUX_E" instead of "AUX E" and I'm 100% sure it's an
> error I introduced myself to the patch.
Just to clarify: this was a rebase issue due to changing the patch
order when sending upstream. The POWER_DOMAIN bits were part of the
patch that implements power wells for ICL, which we didn't submit yet.
I finally got to actually review this patch, so with that fixed:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> > case POWER_DOMAIN_AUX_F:
> > return "AUX_F";
> > case POWER_DOMAIN_AUX_IO_A:
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH 30/24] drm/i915/icl: update VBT's child_device_config flags2 field
2018-05-24 23:42 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Paulo Zanoni
` (3 preceding siblings ...)
2018-05-24 23:42 ` [PATCH 29/24] drm/i915/icl: DP_AUX_E is valid on ICL+ Paulo Zanoni
@ 2018-05-24 23:42 ` Paulo Zanoni
2018-06-14 19:33 ` Rodrigo Vivi
2018-05-25 0:36 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Lucas De Marchi
2018-06-14 19:07 ` Rodrigo Vivi
6 siblings, 1 reply; 127+ messages in thread
From: Paulo Zanoni @ 2018-05-24 23:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Some bits from the flags2 field are going to be used in the next
patches, so replace the whole-byte definition with the actual bits and
document their versions.
This patch is based on a patch by Animesh Manna.
Cc: Animesh Manna <animesh.manna@intel.com>
Credits-to: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_vbt_defs.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index 7c798c18600e..4dc907e47262 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -420,7 +420,9 @@ struct child_device_config {
u16 extended_type;
u8 dvo_function;
u8 dp_usb_type_c:1; /* 195 */
- u8 flags2_reserved:7; /* 195 */
+ u8 tbt:1; /* 209 */
+ u8 flags2_reserved:2; /* 195 */
+ u8 dp_port_trace_length:4; /* 209 */
u8 dp_gpio_index; /* 195 */
u16 dp_gpio_pin_num; /* 195 */
u8 dp_iboost_level:4; /* 196 */
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 30/24] drm/i915/icl: update VBT's child_device_config flags2 field
2018-05-24 23:42 ` [PATCH 30/24] drm/i915/icl: update VBT's child_device_config flags2 field Paulo Zanoni
@ 2018-06-14 19:33 ` Rodrigo Vivi
0 siblings, 0 replies; 127+ messages in thread
From: Rodrigo Vivi @ 2018-06-14 19:33 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Thu, May 24, 2018 at 04:42:41PM -0700, Paulo Zanoni wrote:
> Some bits from the flags2 field are going to be used in the next
> patches, so replace the whole-byte definition with the actual bits and
> document their versions.
>
> This patch is based on a patch by Animesh Manna.
>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Credits-to: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_vbt_defs.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
> index 7c798c18600e..4dc907e47262 100644
> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> @@ -420,7 +420,9 @@ struct child_device_config {
> u16 extended_type;
> u8 dvo_function;
> u8 dp_usb_type_c:1; /* 195 */
> - u8 flags2_reserved:7; /* 195 */
> + u8 tbt:1; /* 209 */
> + u8 flags2_reserved:2; /* 195 */
> + u8 dp_port_trace_length:4; /* 209 */
The reversal order always confuses me :P
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> u8 dp_gpio_index; /* 195 */
> u16 dp_gpio_pin_num; /* 195 */
> u8 dp_iboost_level:4; /* 196 */
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping
2018-05-24 23:42 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Paulo Zanoni
` (4 preceding siblings ...)
2018-05-24 23:42 ` [PATCH 30/24] drm/i915/icl: update VBT's child_device_config flags2 field Paulo Zanoni
@ 2018-05-25 0:36 ` Lucas De Marchi
2018-05-25 16:24 ` Ville Syrjälä
2018-06-14 19:28 ` Rodrigo Vivi
2018-06-14 19:07 ` Rodrigo Vivi
6 siblings, 2 replies; 127+ messages in thread
From: Lucas De Marchi @ 2018-05-25 0:36 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Lucas De Marchi
On Thu, May 24, 2018 at 04:42:36PM -0700, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12
> mapped to tc ports[1-4].
> This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO
> pin mapping table.
>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> drivers/gpu/drm/i915/intel_i2c.c | 12 ++++++------
> 3 files changed, 11 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 452356a4af07..e48b717769b2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3015,6 +3015,10 @@ enum i915_power_well_id {
> #define GPIOF _MMIO(0x5024)
> #define GPIOG _MMIO(0x5028)
> #define GPIOH _MMIO(0x502c)
> +#define GPIOJ _MMIO(0x5034)
> +#define GPIOK _MMIO(0x5038)
> +#define GPIOL _MMIO(0x503C)
> +#define GPIOM _MMIO(0x5040)
I was reviewing again this and I think again I was puzzled why the spec
has them as 0xc5034, ...
Probably same conclusion as I had when I first reviewed this. Maybe it
would be nice to add a comment to PCH_GPIO* saying PCH_GPIOA is used
only for calculation the gpio base and remove the rest. I can send this
is a separate patch, what do you think?
-------8<-------
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6953419881c4..40b9aa57078b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7442,12 +7442,8 @@ enum {
#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
+/* Used just for calculating the gpio base for PCH */
#define PCH_GPIOA _MMIO(0xc5010)
-#define PCH_GPIOB _MMIO(0xc5014)
-#define PCH_GPIOC _MMIO(0xc5018)
-#define PCH_GPIOD _MMIO(0xc501c)
-#define PCH_GPIOE _MMIO(0xc5020)
-#define PCH_GPIOF _MMIO(0xc5024)
#define PCH_GMBUS0 _MMIO(0xc5100)
#define PCH_GMBUS1 _MMIO(0xc5104)
-------8<-------
Other than that,
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> # define GPIO_CLOCK_DIR_MASK (1 << 0)
> # define GPIO_CLOCK_DIR_IN (0 << 1)
> # define GPIO_CLOCK_DIR_OUT (1 << 1)
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 75f02a0e7d39..3db2459c79b1 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -2276,7 +2276,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
> ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
> else if (HAS_PCH_CNP(dev_priv))
> ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
> - else if (IS_ICELAKE(dev_priv))
> + else if (HAS_PCH_ICP(dev_priv))
> ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
> else
> ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index e6875509bcd9..b91e418028cb 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -77,12 +77,12 @@ static const struct gmbus_pin gmbus_pins_cnp[] = {
> };
>
> static const struct gmbus_pin gmbus_pins_icp[] = {
> - [GMBUS_PIN_1_BXT] = { "dpa", GPIOA },
> - [GMBUS_PIN_2_BXT] = { "dpb", GPIOB },
> - [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOC },
> - [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOD },
> - [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOE },
> - [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOF },
> + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> };
>
> /* pin is expected to be valid */
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 127+ messages in thread* Re: [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping
2018-05-25 0:36 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Lucas De Marchi
@ 2018-05-25 16:24 ` Ville Syrjälä
2018-05-25 16:26 ` Lucas De Marchi
2018-06-14 19:28 ` Rodrigo Vivi
1 sibling, 1 reply; 127+ messages in thread
From: Ville Syrjälä @ 2018-05-25 16:24 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Lucas De Marchi, Paulo Zanoni
On Thu, May 24, 2018 at 05:36:37PM -0700, Lucas De Marchi wrote:
> On Thu, May 24, 2018 at 04:42:36PM -0700, Paulo Zanoni wrote:
> > From: Mahesh Kumar <mahesh1.kumar@intel.com>
> >
> > ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12
> > mapped to tc ports[1-4].
> > This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO
> > pin mapping table.
> >
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> > drivers/gpu/drm/i915/intel_i2c.c | 12 ++++++------
> > 3 files changed, 11 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 452356a4af07..e48b717769b2 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3015,6 +3015,10 @@ enum i915_power_well_id {
> > #define GPIOF _MMIO(0x5024)
> > #define GPIOG _MMIO(0x5028)
> > #define GPIOH _MMIO(0x502c)
> > +#define GPIOJ _MMIO(0x5034)
> > +#define GPIOK _MMIO(0x5038)
> > +#define GPIOL _MMIO(0x503C)
> > +#define GPIOM _MMIO(0x5040)
>
> I was reviewing again this and I think again I was puzzled why the spec
> has them as 0xc5034, ...
>
> Probably same conclusion as I had when I first reviewed this. Maybe it
> would be nice to add a comment to PCH_GPIO* saying PCH_GPIOA is used
> only for calculation the gpio base and remove the rest. I can send this
> is a separate patch, what do you think?
>
> -------8<-------
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6953419881c4..40b9aa57078b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7442,12 +7442,8 @@ enum {
> #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
> #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
>
> +/* Used just for calculating the gpio base for PCH */
> #define PCH_GPIOA _MMIO(0xc5010)
> -#define PCH_GPIOB _MMIO(0xc5014)
> -#define PCH_GPIOC _MMIO(0xc5018)
> -#define PCH_GPIOD _MMIO(0xc501c)
> -#define PCH_GPIOE _MMIO(0xc5020)
> -#define PCH_GPIOF _MMIO(0xc5024)
Maybe just have
#define PCH_GPIO_BASE ...
and throw out the PCH_GPIO/GMBUS defines entirely?
>
> #define PCH_GMBUS0 _MMIO(0xc5100)
> #define PCH_GMBUS1 _MMIO(0xc5104)
> -------8<-------
>
>
> Other than that,
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> > # define GPIO_CLOCK_DIR_MASK (1 << 0)
> > # define GPIO_CLOCK_DIR_IN (0 << 1)
> > # define GPIO_CLOCK_DIR_OUT (1 << 1)
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index 75f02a0e7d39..3db2459c79b1 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -2276,7 +2276,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
> > ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
> > else if (HAS_PCH_CNP(dev_priv))
> > ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
> > - else if (IS_ICELAKE(dev_priv))
> > + else if (HAS_PCH_ICP(dev_priv))
> > ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
> > else
> > ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
> > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> > index e6875509bcd9..b91e418028cb 100644
> > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > @@ -77,12 +77,12 @@ static const struct gmbus_pin gmbus_pins_cnp[] = {
> > };
> >
> > static const struct gmbus_pin gmbus_pins_icp[] = {
> > - [GMBUS_PIN_1_BXT] = { "dpa", GPIOA },
> > - [GMBUS_PIN_2_BXT] = { "dpb", GPIOB },
> > - [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOC },
> > - [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOD },
> > - [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOE },
> > - [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOF },
> > + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> > + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> > + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> > + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> > + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> > + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> > };
> >
> > /* pin is expected to be valid */
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping
2018-05-25 16:24 ` Ville Syrjälä
@ 2018-05-25 16:26 ` Lucas De Marchi
0 siblings, 0 replies; 127+ messages in thread
From: Lucas De Marchi @ 2018-05-25 16:26 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Paulo Zanoni
On Fri, May 25, 2018 at 07:24:07PM +0300, Ville Syrjälä wrote:
> On Thu, May 24, 2018 at 05:36:37PM -0700, Lucas De Marchi wrote:
> > On Thu, May 24, 2018 at 04:42:36PM -0700, Paulo Zanoni wrote:
> > > From: Mahesh Kumar <mahesh1.kumar@intel.com>
> > >
> > > ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12
> > > mapped to tc ports[1-4].
> > > This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO
> > > pin mapping table.
> > >
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > > drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> > > drivers/gpu/drm/i915/intel_i2c.c | 12 ++++++------
> > > 3 files changed, 11 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 452356a4af07..e48b717769b2 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -3015,6 +3015,10 @@ enum i915_power_well_id {
> > > #define GPIOF _MMIO(0x5024)
> > > #define GPIOG _MMIO(0x5028)
> > > #define GPIOH _MMIO(0x502c)
> > > +#define GPIOJ _MMIO(0x5034)
> > > +#define GPIOK _MMIO(0x5038)
> > > +#define GPIOL _MMIO(0x503C)
> > > +#define GPIOM _MMIO(0x5040)
> >
> > I was reviewing again this and I think again I was puzzled why the spec
> > has them as 0xc5034, ...
> >
> > Probably same conclusion as I had when I first reviewed this. Maybe it
> > would be nice to add a comment to PCH_GPIO* saying PCH_GPIOA is used
> > only for calculation the gpio base and remove the rest. I can send this
> > is a separate patch, what do you think?
> >
> > -------8<-------
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 6953419881c4..40b9aa57078b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7442,12 +7442,8 @@ enum {
> > #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
> > #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
> >
> > +/* Used just for calculating the gpio base for PCH */
> > #define PCH_GPIOA _MMIO(0xc5010)
> > -#define PCH_GPIOB _MMIO(0xc5014)
> > -#define PCH_GPIOC _MMIO(0xc5018)
> > -#define PCH_GPIOD _MMIO(0xc501c)
> > -#define PCH_GPIOE _MMIO(0xc5020)
> > -#define PCH_GPIOF _MMIO(0xc5024)
>
> Maybe just have
>
> #define PCH_GPIO_BASE ...
>
> and throw out the PCH_GPIO/GMBUS defines entirely?
Yeah just thought about this after sending the email. I will spin a
patch with that.
thanks
Lucas De Marchi
>
> >
> > #define PCH_GMBUS0 _MMIO(0xc5100)
> > #define PCH_GMBUS1 _MMIO(0xc5104)
> > -------8<-------
> >
> >
> > Other than that,
> >
> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >
> > > # define GPIO_CLOCK_DIR_MASK (1 << 0)
> > > # define GPIO_CLOCK_DIR_IN (0 << 1)
> > > # define GPIO_CLOCK_DIR_OUT (1 << 1)
> > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > > index 75f02a0e7d39..3db2459c79b1 100644
> > > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > > @@ -2276,7 +2276,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
> > > ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
> > > else if (HAS_PCH_CNP(dev_priv))
> > > ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
> > > - else if (IS_ICELAKE(dev_priv))
> > > + else if (HAS_PCH_ICP(dev_priv))
> > > ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
> > > else
> > > ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
> > > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> > > index e6875509bcd9..b91e418028cb 100644
> > > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > > @@ -77,12 +77,12 @@ static const struct gmbus_pin gmbus_pins_cnp[] = {
> > > };
> > >
> > > static const struct gmbus_pin gmbus_pins_icp[] = {
> > > - [GMBUS_PIN_1_BXT] = { "dpa", GPIOA },
> > > - [GMBUS_PIN_2_BXT] = { "dpb", GPIOB },
> > > - [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOC },
> > > - [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOD },
> > > - [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOE },
> > > - [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOF },
> > > + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> > > + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> > > + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> > > + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> > > + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> > > + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> > > };
> > >
> > > /* pin is expected to be valid */
> > > --
> > > 2.14.3
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping
2018-05-25 0:36 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Lucas De Marchi
2018-05-25 16:24 ` Ville Syrjälä
@ 2018-06-14 19:28 ` Rodrigo Vivi
1 sibling, 0 replies; 127+ messages in thread
From: Rodrigo Vivi @ 2018-06-14 19:28 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Lucas De Marchi, Paulo Zanoni
On Thu, May 24, 2018 at 05:36:37PM -0700, Lucas De Marchi wrote:
> On Thu, May 24, 2018 at 04:42:36PM -0700, Paulo Zanoni wrote:
> > From: Mahesh Kumar <mahesh1.kumar@intel.com>
> >
> > ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12
> > mapped to tc ports[1-4].
> > This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO
> > pin mapping table.
> >
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> > drivers/gpu/drm/i915/intel_i2c.c | 12 ++++++------
> > 3 files changed, 11 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 452356a4af07..e48b717769b2 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3015,6 +3015,10 @@ enum i915_power_well_id {
> > #define GPIOF _MMIO(0x5024)
> > #define GPIOG _MMIO(0x5028)
> > #define GPIOH _MMIO(0x502c)
> > +#define GPIOJ _MMIO(0x5034)
> > +#define GPIOK _MMIO(0x5038)
> > +#define GPIOL _MMIO(0x503C)
> > +#define GPIOM _MMIO(0x5040)
>
> I was reviewing again this and I think again I was puzzled why the spec
> has them as 0xc5034, ...
>
> Probably same conclusion as I had when I first reviewed this. Maybe it
> would be nice to add a comment to PCH_GPIO* saying PCH_GPIOA is used
> only for calculation the gpio base and remove the rest. I can send this
> is a separate patch, what do you think?
yeap... 0xC0000 is magically summed on the gmbus reg access...
I spent a while in the past deciphering this...
It would be good to have registers and offset mapping to spec
to avoid more future readers
>
> -------8<-------
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6953419881c4..40b9aa57078b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7442,12 +7442,8 @@ enum {
> #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
> #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
>
> +/* Used just for calculating the gpio base for PCH */
> #define PCH_GPIOA _MMIO(0xc5010)
> -#define PCH_GPIOB _MMIO(0xc5014)
> -#define PCH_GPIOC _MMIO(0xc5018)
> -#define PCH_GPIOD _MMIO(0xc501c)
> -#define PCH_GPIOE _MMIO(0xc5020)
> -#define PCH_GPIOF _MMIO(0xc5024)
>
> #define PCH_GMBUS0 _MMIO(0xc5100)
> #define PCH_GMBUS1 _MMIO(0xc5104)
> -------8<-------
>
>
> Other than that,
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> > # define GPIO_CLOCK_DIR_MASK (1 << 0)
> > # define GPIO_CLOCK_DIR_IN (0 << 1)
> > # define GPIO_CLOCK_DIR_OUT (1 << 1)
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index 75f02a0e7d39..3db2459c79b1 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -2276,7 +2276,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
> > ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
> > else if (HAS_PCH_CNP(dev_priv))
> > ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
> > - else if (IS_ICELAKE(dev_priv))
> > + else if (HAS_PCH_ICP(dev_priv))
> > ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
> > else
> > ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
> > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> > index e6875509bcd9..b91e418028cb 100644
> > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > @@ -77,12 +77,12 @@ static const struct gmbus_pin gmbus_pins_cnp[] = {
> > };
> >
> > static const struct gmbus_pin gmbus_pins_icp[] = {
> > - [GMBUS_PIN_1_BXT] = { "dpa", GPIOA },
> > - [GMBUS_PIN_2_BXT] = { "dpb", GPIOB },
> > - [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOC },
> > - [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOD },
> > - [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOE },
> > - [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOF },
> > + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> > + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> > + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> > + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> > + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> > + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> > };
> >
> > /* pin is expected to be valid */
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping
2018-05-24 23:42 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Paulo Zanoni
` (5 preceding siblings ...)
2018-05-25 0:36 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Lucas De Marchi
@ 2018-06-14 19:07 ` Rodrigo Vivi
2018-06-14 20:43 ` Paulo Zanoni
6 siblings, 1 reply; 127+ messages in thread
From: Rodrigo Vivi @ 2018-06-14 19:07 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Lucas De Marchi
On Thu, May 24, 2018 at 04:42:36PM -0700, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12
> mapped to tc ports[1-4].
> This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO
> pin mapping table.
>
Fixes:?
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> drivers/gpu/drm/i915/intel_i2c.c | 12 ++++++------
> 3 files changed, 11 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 452356a4af07..e48b717769b2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3015,6 +3015,10 @@ enum i915_power_well_id {
> #define GPIOF _MMIO(0x5024)
> #define GPIOG _MMIO(0x5028)
> #define GPIOH _MMIO(0x502c)
> +#define GPIOJ _MMIO(0x5034)
I believe we could start using the real register name
instead the generic letter++, in order
to help all future readers to find it easily on spec.
like s/GPIOJ/GPIO_CTL_9 and etc...
The offset value already magically adds the 0xC0000
so offset as it is here doesn't help...
also leter J means nothing...
Anyways this might be on this patch or separated one
or just ignored, so:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> +#define GPIOK _MMIO(0x5038)
> +#define GPIOL _MMIO(0x503C)
> +#define GPIOM _MMIO(0x5040)
> # define GPIO_CLOCK_DIR_MASK (1 << 0)
> # define GPIO_CLOCK_DIR_IN (0 << 1)
> # define GPIO_CLOCK_DIR_OUT (1 << 1)
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 75f02a0e7d39..3db2459c79b1 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -2276,7 +2276,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
> ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
> else if (HAS_PCH_CNP(dev_priv))
> ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
> - else if (IS_ICELAKE(dev_priv))
> + else if (HAS_PCH_ICP(dev_priv))
> ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
> else
> ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index e6875509bcd9..b91e418028cb 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -77,12 +77,12 @@ static const struct gmbus_pin gmbus_pins_cnp[] = {
> };
>
> static const struct gmbus_pin gmbus_pins_icp[] = {
> - [GMBUS_PIN_1_BXT] = { "dpa", GPIOA },
> - [GMBUS_PIN_2_BXT] = { "dpb", GPIOB },
> - [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOC },
> - [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOD },
> - [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOE },
> - [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOF },
> + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> };
>
> /* pin is expected to be valid */
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping
2018-06-14 19:07 ` Rodrigo Vivi
@ 2018-06-14 20:43 ` Paulo Zanoni
0 siblings, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-06-14 20:43 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Lucas De Marchi
Em Qui, 2018-06-14 às 12:07 -0700, Rodrigo Vivi escreveu:
> On Thu, May 24, 2018 at 04:42:36PM -0700, Paulo Zanoni wrote:
> > From: Mahesh Kumar <mahesh1.kumar@intel.com>
> >
> > ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins
> > 9/10/11/12
> > mapped to tc ports[1-4].
> > This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them
> > in GPIO
> > pin mapping table.
> >
>
> Fixes:?
No since it's alpha_support.
>
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> > drivers/gpu/drm/i915/intel_i2c.c | 12 ++++++------
> > 3 files changed, 11 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 452356a4af07..e48b717769b2 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3015,6 +3015,10 @@ enum i915_power_well_id {
> > #define GPIOF _MMIO(0x5024)
> > #define GPIOG _MMIO(0x5028)
> > #define GPIOH _MMIO(0x502c)
> > +#define GPIOJ _MMIO(0x5034)
>
> I believe we could start using the real register name
> instead the generic letter++, in order
> to help all future readers to find it easily on spec.
>
> like s/GPIOJ/GPIO_CTL_9 and etc...
>
> The offset value already magically adds the 0xC0000
> so offset as it is here doesn't help...
> also leter J means nothing...
>
> Anyways this might be on this patch or separated one
> or just ignored, so:
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This is already merged, but thanks anyway.
>
> > +#define GPIOK _MMIO(0x5038)
> > +#define GPIOL _MMIO(0x503C)
> > +#define GPIOM _MMIO(0x5040)
>
>
> > # define GPIO_CLOCK_DIR_MASK (1 << 0)
> > # define GPIO_CLOCK_DIR_IN (0 << 1)
> > # define GPIO_CLOCK_DIR_OUT (1 << 1)
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > b/drivers/gpu/drm/i915/intel_hdmi.c
> > index 75f02a0e7d39..3db2459c79b1 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -2276,7 +2276,7 @@ static u8 intel_hdmi_ddc_pin(struct
> > drm_i915_private *dev_priv,
> > ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
> > else if (HAS_PCH_CNP(dev_priv))
> > ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
> > - else if (IS_ICELAKE(dev_priv))
> > + else if (HAS_PCH_ICP(dev_priv))
> > ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
> > else
> > ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
> > diff --git a/drivers/gpu/drm/i915/intel_i2c.c
> > b/drivers/gpu/drm/i915/intel_i2c.c
> > index e6875509bcd9..b91e418028cb 100644
> > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > @@ -77,12 +77,12 @@ static const struct gmbus_pin gmbus_pins_cnp[]
> > = {
> > };
> >
> > static const struct gmbus_pin gmbus_pins_icp[] = {
> > - [GMBUS_PIN_1_BXT] = { "dpa", GPIOA },
> > - [GMBUS_PIN_2_BXT] = { "dpb", GPIOB },
> > - [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOC },
> > - [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOD },
> > - [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOE },
> > - [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOF },
> > + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> > + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> > + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> > + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> > + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> > + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> > };
> >
> > /* pin is expected to be valid */
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches (rev7)
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (32 preceding siblings ...)
2018-05-24 23:42 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Paulo Zanoni
@ 2018-05-24 23:59 ` Patchwork
2018-05-25 0:06 ` ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-05-24 23:59 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches (rev7)
URL : https://patchwork.freedesktop.org/series/43546/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d9841751b963 drm/i915/icl: Extend AUX F interrupts to ICL
7913b8e944f7 drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
8b1806b8b1e1 drm/i915/icl: introduce tc_port
dbbc1dcd8f1d drm/i915/icl: Support for TC North Display interrupts
bb897d8be18f drm/i915/icp: Add Interrupt Support
23bec0ea27e5 drm/i915/ICL: Add register definition for DFLEXDPMLE
0aa9dd7d6752 drm/i915/icl: Add DDI HDMI level selection for ICL
0452d69471d2 drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
ff4263dd5056 drm/i915/icl: Add Icelake PCH detection
914247ff4516 drm/i915/icl: add icelake_get_ddi_pll()
7aacef71bf5a drm/i915/icl: Get DDI clock for ICL based on PLLs.
ea5e8efbb415 drm/i915/icl: Calculate link clock using the new registers
87436cc87084 drm/i915/icl: unconditionally init DDI for every port
089d3d15c278 drm/i915/icl: start adding the TBT pll
-:162: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#162: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:137:
};
+#define I915_NUM_PLLS 7
total: 0 errors, 0 warnings, 1 checks, 129 lines checked
3292e78e766b drm/i915/icl: compute the TBT PLL registers
-:18: CHECK:CAMELCASE: Avoid CamelCase: <icl_tbt_pll_24MHz_values>
#18: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2455:
+static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
-:23: CHECK:CAMELCASE: Avoid CamelCase: <icl_tbt_pll_19_2MHz_values>
#23: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2460:
+static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
total: 0 errors, 0 warnings, 2 checks, 51 lines checked
91188c6ba486 drm/i915/icl: Handle hotplug interrupts for DP over TBT
c7b5b502d19d drm/i915/icl: Add 10-bit support for hdmi
8a7fe1b43d10 drm/i915/icl: implement icl_digital_port_connected()
6463e56dbfc4 drm/i915/icl: store the port type for TC ports
8e31a26476b9 drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
e86c6a8b3512 drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
30221f17596f drm/i915/icl: Update FIA supported lane count for hpd.
76747abf5771 drm/i915/icl: program MG_DP_MODE
2a7fade59ca8 drm/i915/icl: toggle PHY clock gating around link training
0e9dc804376b drm/i915/icl: update VBT's child_device_config flags2 field
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* ✗ Fi.CI.SPARSE: warning for More ICL display patches (rev7)
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (33 preceding siblings ...)
2018-05-24 23:59 ` ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches (rev7) Patchwork
@ 2018-05-25 0:06 ` Patchwork
2018-05-25 0:14 ` ✗ Fi.CI.BAT: failure " Patchwork
` (5 subsequent siblings)
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-05-25 0:06 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches (rev7)
URL : https://patchwork.freedesktop.org/series/43546/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Extend AUX F interrupts to ICL
Okay!
Commit: drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
Okay!
Commit: drm/i915/icl: introduce tc_port
Okay!
Commit: drm/i915/icl: Support for TC North Display interrupts
Okay!
Commit: drm/i915/icp: Add Interrupt Support
Okay!
Commit: drm/i915/ICL: Add register definition for DFLEXDPMLE
Okay!
Commit: drm/i915/icl: Add DDI HDMI level selection for ICL
Okay!
Commit: drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
Okay!
Commit: drm/i915/icl: Add Icelake PCH detection
Okay!
Commit: drm/i915/icl: add icelake_get_ddi_pll()
Okay!
Commit: drm/i915/icl: Get DDI clock for ICL based on PLLs.
Okay!
Commit: drm/i915/icl: Calculate link clock using the new registers
Okay!
Commit: drm/i915/icl: unconditionally init DDI for every port
Okay!
Commit: drm/i915/icl: start adding the TBT pll
Okay!
Commit: drm/i915/icl: compute the TBT PLL registers
Okay!
Commit: drm/i915/icl: Handle hotplug interrupts for DP over TBT
Okay!
Commit: drm/i915/icl: Add 10-bit support for hdmi
Okay!
Commit: drm/i915/icl: implement icl_digital_port_connected()
Okay!
Commit: drm/i915/icl: store the port type for TC ports
Okay!
Commit: drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
Okay!
Commit: drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
Okay!
Commit: drm/i915/icl: Update FIA supported lane count for hpd.
-O:drivers/gpu/drm/i915/intel_dp.c:186:16: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dp.c:186:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
Commit: drm/i915/icl: program MG_DP_MODE
Okay!
Commit: drm/i915/icl: toggle PHY clock gating around link training
Okay!
Commit: drm/i915/icl: update VBT's child_device_config flags2 field
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* ✗ Fi.CI.BAT: failure for More ICL display patches (rev7)
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (34 preceding siblings ...)
2018-05-25 0:06 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-05-25 0:14 ` Patchwork
2018-05-25 0:49 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev8) Patchwork
` (4 subsequent siblings)
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-05-25 0:14 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches (rev7)
URL : https://patchwork.freedesktop.org/series/43546/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4234 -> Patchwork_9111 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9111 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9111, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/43546/revisions/7/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9111:
=== IGT changes ===
==== Possible regressions ====
igt@drv_module_reload@basic-reload-inject:
fi-ilk-650: PASS -> DMESG-WARN
== Known issues ==
Here are the changes found in Patchwork_9111 that come from known issues:
=== IGT changes ===
==== Possible fixes ====
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
== Participating hosts (44 -> 39) ==
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4234 -> Patchwork_9111
CI_DRM_4234: 399e4206d849c5667d8553911e0035c53cd9c24e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9111: 0e9dc804376bf800ffdb84a2ffde54c720c9f295 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0e9dc804376b drm/i915/icl: update VBT's child_device_config flags2 field
2a7fade59ca8 drm/i915/icl: toggle PHY clock gating around link training
76747abf5771 drm/i915/icl: program MG_DP_MODE
30221f17596f drm/i915/icl: Update FIA supported lane count for hpd.
e86c6a8b3512 drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
8e31a26476b9 drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
6463e56dbfc4 drm/i915/icl: store the port type for TC ports
8a7fe1b43d10 drm/i915/icl: implement icl_digital_port_connected()
c7b5b502d19d drm/i915/icl: Add 10-bit support for hdmi
91188c6ba486 drm/i915/icl: Handle hotplug interrupts for DP over TBT
3292e78e766b drm/i915/icl: compute the TBT PLL registers
089d3d15c278 drm/i915/icl: start adding the TBT pll
87436cc87084 drm/i915/icl: unconditionally init DDI for every port
ea5e8efbb415 drm/i915/icl: Calculate link clock using the new registers
7aacef71bf5a drm/i915/icl: Get DDI clock for ICL based on PLLs.
914247ff4516 drm/i915/icl: add icelake_get_ddi_pll()
ff4263dd5056 drm/i915/icl: Add Icelake PCH detection
0452d69471d2 drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
0aa9dd7d6752 drm/i915/icl: Add DDI HDMI level selection for ICL
23bec0ea27e5 drm/i915/ICL: Add register definition for DFLEXDPMLE
bb897d8be18f drm/i915/icp: Add Interrupt Support
dbbc1dcd8f1d drm/i915/icl: Support for TC North Display interrupts
8b1806b8b1e1 drm/i915/icl: introduce tc_port
7913b8e944f7 drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
d9841751b963 drm/i915/icl: Extend AUX F interrupts to ICL
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9111/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* ✗ Fi.CI.BAT: failure for More ICL display patches (rev8)
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (35 preceding siblings ...)
2018-05-25 0:14 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2018-05-25 0:49 ` Patchwork
2018-05-25 20:11 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev11) Patchwork
` (3 subsequent siblings)
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-05-25 0:49 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches (rev8)
URL : https://patchwork.freedesktop.org/series/43546/
State : failure
== Summary ==
Applying: drm/i915/icl: Extend AUX F interrupts to ICL
Applying: drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
Applying: drm/i915/icl: introduce tc_port
Applying: drm/i915/icl: Support for TC North Display interrupts
Applying: drm/i915/icp: Add Interrupt Support
Applying: drm/i915/ICL: Add register definition for DFLEXDPMLE
Applying: drm/i915/icl: Add DDI HDMI level selection for ICL
Applying: drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
Applying: drm/i915/icl: Add Icelake PCH detection
Applying: drm/i915/icl: add icelake_get_ddi_pll()
Applying: drm/i915/icl: Get DDI clock for ICL based on PLLs.
Applying: drm/i915/icl: Calculate link clock using the new registers
Applying: drm/i915/icl: unconditionally init DDI for every port
Applying: drm/i915/icl: start adding the TBT pll
Applying: drm/i915/icl: compute the TBT PLL registers
Applying: drm/i915/icl: Handle hotplug interrupts for DP over TBT
Applying: drm/i915/icl: Add 10-bit support for hdmi
Applying: drm/i915/icl: implement icl_digital_port_connected()
Applying: drm/i915/icl: store the port type for TC ports
Applying: drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
Applying: drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
Applying: drm/i915/icl: Update FIA supported lane count for hpd.
Applying: drm/i915/icl: program MG_DP_MODE
Applying: drm/i915/icl: toggle PHY clock gating around link training
Applying: drm/i915/icl: fix gmbus gpio pin mapping
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_reg.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_reg.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_reg.h
Patch failed at 0025 drm/i915/icl: fix gmbus gpio pin mapping
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 127+ messages in thread* ✗ Fi.CI.BAT: failure for More ICL display patches (rev11)
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (36 preceding siblings ...)
2018-05-25 0:49 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev8) Patchwork
@ 2018-05-25 20:11 ` Patchwork
2018-06-01 23:22 ` [PATCH 00/24] More ICL display patches Paulo Zanoni
` (2 subsequent siblings)
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-05-25 20:11 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches (rev11)
URL : https://patchwork.freedesktop.org/series/43546/
State : failure
== Summary ==
Applying: drm/i915/icl: Extend AUX F interrupts to ICL
Applying: drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
Applying: drm/i915/icl: introduce tc_port
Applying: drm/i915/icl: Support for TC North Display interrupts
Applying: drm/i915/icp: Add Interrupt Support
Applying: drm/i915/icl: Add register definition for DFLEXDPMLE
Applying: drm/i915/icl: Add DDI HDMI level selection for ICL
Applying: drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
Applying: drm/i915/icl: Add Icelake PCH detection
Applying: drm/i915/icl: add icelake_get_ddi_pll()
Applying: drm/i915/icl: Get DDI clock for ICL based on PLLs.
Applying: drm/i915/icl: Calculate link clock using the new registers
Applying: drm/i915/icl: unconditionally init DDI for every port
Applying: drm/i915/icl: start adding the TBT pll
Applying: drm/i915/icl: compute the TBT PLL registers
Applying: drm/i915/icl: Handle hotplug interrupts for DP over TBT
Applying: drm/i915/icl: Add 10-bit support for hdmi
Applying: drm/i915/icl: implement icl_digital_port_connected()
Applying: drm/i915/icl: store the port type for TC ports
Applying: drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
Applying: drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
Applying: drm/i915/icl: Update FIA supported lane count for hpd.
Applying: drm/i915/icl: program MG_DP_MODE
Applying: drm/i915/icl: toggle PHY clock gating around link training
Applying: drm/i915/icl: fix gmbus gpio pin mapping
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_reg.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_reg.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_reg.h
Patch failed at 0025 drm/i915/icl: fix gmbus gpio pin mapping
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
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^ permalink raw reply [flat|nested] 127+ messages in thread* Re: [PATCH 00/24] More ICL display patches
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (37 preceding siblings ...)
2018-05-25 20:11 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev11) Patchwork
@ 2018-06-01 23:22 ` Paulo Zanoni
2018-06-13 21:49 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev12) Patchwork
2018-06-14 20:20 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev13) Patchwork
40 siblings, 0 replies; 127+ messages in thread
From: Paulo Zanoni @ 2018-06-01 23:22 UTC (permalink / raw)
To: intel-gfx
Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> Hi
>
> This series contains some more ICL patches that haven't seen the
> mailing list yet. While I'll definitely help re-review the patches
> not
> authored by me, please help me with the ones I can't review.
I just applied 7 patches of this series. They were all part of v1 and
got proper testing by CI.
I messed the threading while submitting patches 25-30 so now CI doesn't
know what to do. Looks like we'll have to submit the full series in a
single thread again for it to be happy. I'll wait a little more before
doing that.
Thanks everybody for the help,
Paulo
>
> Thanks,
> Paulo
>
> Animesh Manna (1):
> drm/i915/icl: Update FIA supported lane count for hpd.
>
> Anusha Srivatsa (2):
> drm/i915/icp: Add Interrupt Support
> drm/i915/icl: Add Icelake PCH detection
>
> Arkadiusz Hiler (1):
> drm/i915/icl: Calculate link clock using the new registers
>
> Dhinakaran Pandiyan (4):
> drm/i915/icl: Extend AUX F interrupts to ICL
> drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
> drm/i915/icl: Support for TC North Display interrupts
> drm/i915/icl: Handle hotplug interrupts for DP over TBT
>
> Manasi Navare (3):
> drm/i915/ICL: Add register definition for DFLEXDPMLE
> drm/i915/icl: Add DDI HDMI level selection for ICL
> drm/i915/icl: Get DDI clock for ICL based on PLLs.
>
> Paulo Zanoni (11):
> drm/i915/icl: introduce tc_port
> drm/i915/icl: add icelake_get_ddi_pll()
> drm/i915/icl: unconditionally init DDI for every port
> drm/i915/icl: start adding the TBT pll
> drm/i915/icl: compute the TBT PLL registers
> drm/i915/icl: implement icl_digital_port_connected()
> drm/i915/icl: store the port type for TC ports
> drm/i915/icl: implement the tc/legacy HPD {dis,}connect flow for DP
> drm/i915/icl: implement the legacy HPD {dis,}connect flow for HDMI
> drm/i915/icl: program MG_DP_MODE
> drm/i915/icl: toggle PHY clock gating around link training
>
> Sripada, Radhakrishna (2):
> drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
> drm/i915/icl: Add 10-bit support for hdmi
>
> drivers/gpu/drm/i915/i915_drv.c | 2 +
> drivers/gpu/drm/i915/i915_irq.c | 295
> +++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 142 ++++++++++++++++
> drivers/gpu/drm/i915/intel_bios.c | 35 +++-
> drivers/gpu/drm/i915/intel_ddi.c | 65 ++++++-
> drivers/gpu/drm/i915/intel_display.c | 67 +++++++-
> drivers/gpu/drm/i915/intel_display.h | 18 ++
> drivers/gpu/drm/i915/intel_dp.c | 311
> +++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 111 +++++++++++-
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 16 +-
> drivers/gpu/drm/i915/intel_drv.h | 7 +
> drivers/gpu/drm/i915/intel_hdmi.c | 75 +++++---
> drivers/gpu/drm/i915/intel_vbt_defs.h | 6 +
> 13 files changed, 1098 insertions(+), 52 deletions(-)
>
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^ permalink raw reply [flat|nested] 127+ messages in thread* ✗ Fi.CI.BAT: failure for More ICL display patches (rev12)
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (38 preceding siblings ...)
2018-06-01 23:22 ` [PATCH 00/24] More ICL display patches Paulo Zanoni
@ 2018-06-13 21:49 ` Patchwork
2018-06-14 20:20 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev13) Patchwork
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-06-13 21:49 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches (rev12)
URL : https://patchwork.freedesktop.org/series/43546/
State : failure
== Summary ==
Applying: drm/i915/icl: Extend AUX F interrupts to ICL
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_irq.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_irq.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_irq.c
error: Failed to merge in the changes.
Patch failed at 0001 drm/i915/icl: Extend AUX F interrupts to ICL
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
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^ permalink raw reply [flat|nested] 127+ messages in thread* ✗ Fi.CI.BAT: failure for More ICL display patches (rev13)
2018-05-22 0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
` (39 preceding siblings ...)
2018-06-13 21:49 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev12) Patchwork
@ 2018-06-14 20:20 ` Patchwork
40 siblings, 0 replies; 127+ messages in thread
From: Patchwork @ 2018-06-14 20:20 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: More ICL display patches (rev13)
URL : https://patchwork.freedesktop.org/series/43546/
State : failure
== Summary ==
Applying: drm/i915/icl: Extend AUX F interrupts to ICL
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_irq.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_irq.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_irq.c
error: Failed to merge in the changes.
Patch failed at 0001 drm/i915/icl: Extend AUX F interrupts to ICL
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 127+ messages in thread