From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: Re: [PATCH] drm/i915: Fix CHICKEN_TRANS register offset
Date: Wed, 27 Jun 2018 21:54:57 -0700 [thread overview]
Message-ID: <20180628045457.GG9765@intel.com> (raw)
In-Reply-To: <20180627231401.14880-1-jose.souza@intel.com>
On Wed, Jun 27, 2018 at 04:14:01PM -0700, José Roberto de Souza wrote:
> This registers offsets is not sequential for transcoder D and EDP so
> for EDP transcoder it was writing to 0x420d0 that do not map to
> any register in spec.
>
> CHICKEN_TRANS is used in PSR2 and intel_enable_ddi_hdmi() to apply
> WA #1143 but I'm not aware of any open issue cause by this offset
> error.
>
> Spec: 7524
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 14 +++++++++++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c30cfcd90754..098a4cb71310 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7256,9 +7256,17 @@ enum {
> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>
> -#define CHICKEN_TRANS_A 0x420c0
> -#define CHICKEN_TRANS_B 0x420c4
> -#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> +#define _CHICKEN_TRANS_A 0x420c0
> +#define _CHICKEN_TRANS_B 0x420c4
> +#define _CHICKEN_TRANS_C 0x420c8
> +#define _CHICKEN_TRANS_D 0x420d8
note that enum transcoder has no TRANSCODER_D...
TRANSCODER_EDP = 3
so:
>>> hex(0x420c0+3*4)
'0x420cc'
> +#define _CHICKEN_TRANS_EDP 0x420cc
> +#define CHICKEN_TRANS(trans) _MMIO(_PICK(trans, \
> + _CHICKEN_TRANS_A, \
> + _CHICKEN_TRANS_B, \
> + _CHICKEN_TRANS_C, \
> + _CHICKEN_TRANS_D, \
> + _CHICKEN_TRANS_EDP))
> #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
> #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
> --
> 2.18.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2018-06-28 4:55 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-27 23:14 [PATCH] drm/i915: Fix CHICKEN_TRANS register offset José Roberto de Souza
2018-06-27 23:42 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-06-28 4:54 ` Rodrigo Vivi [this message]
2018-06-28 5:53 ` ✓ Fi.CI.IGT: " Patchwork
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