* [PATCH i-g-t] igt/gem_tiled_partial_pwrite_pread: Check for known swizzling
@ 2018-06-15 12:47 Chris Wilson
0 siblings, 0 replies; 3+ messages in thread
From: Chris Wilson @ 2018-06-15 12:47 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
As we want to compare a templated tiling pattern against the target_bo,
we need to know that the swizzling is compatible. Or else the two
tiling pattern may differ due to underlying page address that we cannot
know, and so the test may sporadically fail.
References: https://bugs.freedesktop.org/show_bug.cgi?id=102575
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_tiled_partial_pwrite_pread.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/tests/gem_tiled_partial_pwrite_pread.c b/tests/gem_tiled_partial_pwrite_pread.c
index fe573c37c..83c57c07d 100644
--- a/tests/gem_tiled_partial_pwrite_pread.c
+++ b/tests/gem_tiled_partial_pwrite_pread.c
@@ -249,6 +249,24 @@ static void test_partial_read_writes(void)
}
}
+static bool known_swizzling(uint32_t handle)
+{
+ struct drm_i915_gem_get_tiling2 {
+ uint32_t handle;
+ uint32_t tiling_mode;
+ uint32_t swizzle_mode;
+ uint32_t phys_swizzle_mode;
+ } arg = {
+ .handle = handle,
+ };
+#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
+
+ if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg))
+ return false;
+
+ return arg.phys_swizzle_mode == arg.swizzle_mode;
+}
+
igt_main
{
uint32_t tiling_mode = I915_TILING_X;
@@ -271,6 +289,12 @@ igt_main
&tiling_mode, &scratch_pitch, 0);
igt_assert(tiling_mode == I915_TILING_X);
igt_assert(scratch_pitch == 4096);
+
+ /*
+ * As we want to compare our template tiled pattern against
+ * the target bo, we need consistent swizzling on both.
+ */
+ igt_require(known_swizzling(scratch_bo->handle));
staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
BO_SIZE/4096, 4,
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH i-g-t] igt/gem_tiled_partial_pwrite_pread: Check for known swizzling
@ 2018-07-05 19:26 Chris Wilson
2018-07-06 9:00 ` [igt-dev] " Tvrtko Ursulin
0 siblings, 1 reply; 3+ messages in thread
From: Chris Wilson @ 2018-07-05 19:26 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
As we want to compare a templated tiling pattern against the target_bo,
we need to know that the swizzling is compatible. Or else the two
tiling pattern may differ due to underlying page address that we cannot
know, and so the test may sporadically fail.
References: https://bugs.freedesktop.org/show_bug.cgi?id=102575
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
tests/gem_tiled_partial_pwrite_pread.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/tests/gem_tiled_partial_pwrite_pread.c b/tests/gem_tiled_partial_pwrite_pread.c
index 39779dbed..0b4972e37 100644
--- a/tests/gem_tiled_partial_pwrite_pread.c
+++ b/tests/gem_tiled_partial_pwrite_pread.c
@@ -249,6 +249,18 @@ static void test_partial_read_writes(void)
}
}
+static bool known_swizzling(uint32_t handle)
+{
+ struct drm_i915_gem_get_tiling arg = {
+ .handle = handle,
+ };
+
+ if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING, &arg))
+ return false;
+
+ return arg.phys_swizzle_mode == arg.swizzle_mode;
+}
+
igt_main
{
uint32_t tiling_mode = I915_TILING_X;
@@ -272,6 +284,12 @@ igt_main
&tiling_mode, &scratch_pitch, 0);
igt_assert(tiling_mode == I915_TILING_X);
igt_assert(scratch_pitch == 4096);
+
+ /*
+ * As we want to compare our template tiled pattern against
+ * the target bo, we need consistent swizzling on both.
+ */
+ igt_require(known_swizzling(scratch_bo->handle));
staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
BO_SIZE/4096, 4,
--
2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] igt/gem_tiled_partial_pwrite_pread: Check for known swizzling
2018-07-05 19:26 [PATCH i-g-t] igt/gem_tiled_partial_pwrite_pread: Check for known swizzling Chris Wilson
@ 2018-07-06 9:00 ` Tvrtko Ursulin
0 siblings, 0 replies; 3+ messages in thread
From: Tvrtko Ursulin @ 2018-07-06 9:00 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev
On 05/07/2018 20:26, Chris Wilson wrote:
> As we want to compare a templated tiling pattern against the target_bo,
> we need to know that the swizzling is compatible. Or else the two
> tiling pattern may differ due to underlying page address that we cannot
> know, and so the test may sporadically fail.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=102575
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> tests/gem_tiled_partial_pwrite_pread.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/tests/gem_tiled_partial_pwrite_pread.c b/tests/gem_tiled_partial_pwrite_pread.c
> index 39779dbed..0b4972e37 100644
> --- a/tests/gem_tiled_partial_pwrite_pread.c
> +++ b/tests/gem_tiled_partial_pwrite_pread.c
> @@ -249,6 +249,18 @@ static void test_partial_read_writes(void)
> }
> }
>
> +static bool known_swizzling(uint32_t handle)
> +{
> + struct drm_i915_gem_get_tiling arg = {
> + .handle = handle,
> + };
> +
> + if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING, &arg))
> + return false;
> +
> + return arg.phys_swizzle_mode == arg.swizzle_mode;
> +}
> +
> igt_main
> {
> uint32_t tiling_mode = I915_TILING_X;
> @@ -272,6 +284,12 @@ igt_main
> &tiling_mode, &scratch_pitch, 0);
> igt_assert(tiling_mode == I915_TILING_X);
> igt_assert(scratch_pitch == 4096);
> +
> + /*
> + * As we want to compare our template tiled pattern against
> + * the target bo, we need consistent swizzling on both.
> + */
> + igt_require(known_swizzling(scratch_bo->handle));
> staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
> tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
> BO_SIZE/4096, 4,
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2018-07-06 9:00 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-07-05 19:26 [PATCH i-g-t] igt/gem_tiled_partial_pwrite_pread: Check for known swizzling Chris Wilson
2018-07-06 9:00 ` [igt-dev] " Tvrtko Ursulin
-- strict thread matches above, loose matches on Subject: below --
2018-06-15 12:47 Chris Wilson
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).