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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Cc: matthew.auld@intel.com
Subject: [PATCH] drm/i915: Flush the WCB following a WC write
Date: Fri,  6 Jul 2018 12:54:02 +0100	[thread overview]
Message-ID: <20180706115402.18547-1-chris@chris-wilson.co.uk> (raw)

If we have just completed a WC write, we must ensure that the WCB (Write
Combining Buffer) is flushed out to main memory before we can expect to
see the results. This is especially important when mixing WC with GTT as
the physical paths are different and cachelines are not naturally flushed.

Testcase: igt/drv_selftests/live_coherency #gdg
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0c0a1a959d0b..be63e8bbb6d2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -837,6 +837,10 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
 		}
 		break;
 
+	case I915_GEM_DOMAIN_WC:
+		wmb();
+		break;
+
 	case I915_GEM_DOMAIN_CPU:
 		i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
 		break;
-- 
2.18.0

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             reply	other threads:[~2018-07-06 11:54 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-06 11:54 Chris Wilson [this message]
2018-07-06 12:07 ` [PATCH] drm/i915: Flush the WCB following a WC write Matthew Auld
2018-07-06 12:32 ` Tvrtko Ursulin
2018-07-06 12:44 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-07-06 13:00 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-06 16:52 ` [PATCH] " Rodrigo Vivi
2018-07-07  5:20 ` ✗ Fi.CI.IGT: failure for " Patchwork

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