From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Chauhan, Madhav" <madhav.chauhan@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✓ Fi.CI.IGT: success for ICELAKE DSI DRIVER (rev4)
Date: Fri, 06 Jul 2018 22:22:46 -0000 [thread overview]
Message-ID: <20180706222246.22154.47849@emeril.freedesktop.org> (raw)
In-Reply-To: <1530798591-2077-1-git-send-email-madhav.chauhan@intel.com>
== Series Details ==
Series: ICELAKE DSI DRIVER (rev4)
URL : https://patchwork.freedesktop.org/series/44823/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4441_full -> Patchwork_9561_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9561_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9561_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9561_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-bsd2:
shard-kbl: PASS -> SKIP +1
igt@gem_mocs_settings@mocs-rc6-vebox:
shard-kbl: SKIP -> PASS +3
igt@kms_chv_cursor_fail@pipe-b-64x64-right-edge:
shard-snb: PASS -> SKIP +4
== Known issues ==
Here are the changes found in Patchwork_9561_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@plain-flip-ts-check-interruptible:
shard-glk: PASS -> FAIL (fdo#100368)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
shard-snb: PASS -> DMESG-WARN (fdo#102365)
igt@kms_setmode@basic:
shard-apl: PASS -> FAIL (fdo#99912)
igt@perf@blocking:
shard-hsw: PASS -> FAIL (fdo#102252)
==== Possible fixes ====
igt@kms_flip_tiling@flip-to-y-tiled:
shard-glk: FAIL -> PASS
==== Warnings ====
igt@drv_selftest@live_gtt:
shard-kbl: INCOMPLETE (fdo#107127, fdo#103665) -> FAIL (fdo#105347, fdo#107127)
shard-glk: INCOMPLETE (fdo#107127, fdo#103359, k.org#198133) -> FAIL (fdo#105347, fdo#107127)
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
fdo#107127 https://bugs.freedesktop.org/show_bug.cgi?id=107127
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4441 -> Patchwork_9561
CI_DRM_4441: 3fe30c1d16d414ebf8c3ca95af28add100b7975e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4539: 8b3cc74c6911e9b2835fe6e160f84bae463a70ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9561: fb68c08ac6fa9e5975c8fb6b074db0ad65bde5d8 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9561/shards.html
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Intel-gfx mailing list
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prev parent reply other threads:[~2018-07-06 22:22 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-05 13:49 [PATCH v4 00/20] ICELAKE DSI DRIVER Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 01/20] drm/i915/icl: Define register for DSI PLL Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 02/20] drm/i915/icl: Program DSI Escape clock Divider Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 03/20] drm/i915/icl: Define DSI mode ctl register Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 04/20] drm/i915/icl: Enable DSI IO power Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 05/20] drm/i915/icl: Define PORT_CL_DW_10 register Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 06/20] drm/i915/icl: Power down unused DSI lanes Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 07/20] drm/i915/icl: Define AUX lane registers for Port A/B Madhav Chauhan
2018-07-06 9:16 ` Jani Nikula
2018-07-05 13:49 ` [PATCH v4 08/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 09/20] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 10/20] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 11/20] drm/i915/icl: Define T_INIT_MASTER registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 12/20] drm/i915/icl: Program " Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 13/20] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 14/20] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 15/20] drm/i915/icl: Define TA_TIMING_PARAM registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 16/20] drm/i915/icl: Program " Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 17/20] drm/i915/icl: Get DSI transcoder for a given port Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 18/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 19/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 20/20] drm/i915/icl: Configure DSI transcoders Madhav Chauhan
2018-07-05 14:58 ` ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev4) Patchwork
2018-07-05 15:05 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-05 15:20 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-07-05 20:30 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-06 8:10 ` Patchwork
2018-07-06 8:14 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-07-06 22:22 ` Patchwork [this message]
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