* [v3] drm/i915/dsc: Add missing _MMIO() from PPS registers
@ 2018-07-20 21:42 Anusha Srivatsa
2018-07-20 22:40 ` ✓ Fi.CI.BAT: success for drm/i915/dsc: Add missing _MMIO() from PPS registers (rev3) Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Anusha Srivatsa @ 2018-07-20 21:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigi Vivi
This patch fixes the commit -
<2efbb2f099fb> ("i915/dp/dsc: Add DSC PPS register definitions"),
which did not have _MMIO() for DSCA and DSCC.
v2: Fix typos. (manasi)
v3: Change the commit message (Rodrigo)
Cc: Rodrigi Vivi <rodrigo.vivi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 76 ++++++++++++++++++++---------------------
1 file changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8af945d..7394605 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10349,8 +10349,8 @@ enum skl_power_gate {
#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
/* Icelake Display Stream Compression Registers */
-#define DSCA_PICTURE_PARAMETER_SET_0 0x6B200
-#define DSCC_PICTURE_PARAMETER_SET_0 0x6BA00
+#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
+#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
@@ -10370,8 +10370,8 @@ enum skl_power_gate {
#define DSC_VER_MIN_SHIFT 4
#define DSC_VER_MAJ (0x1 << 0)
-#define DSCA_PICTURE_PARAMETER_SET_1 0x6B204
-#define DSCC_PICTURE_PARAMETER_SET_1 0x6BA04
+#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
+#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
@@ -10384,8 +10384,8 @@ enum skl_power_gate {
_ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
#define DSC_BPP(bpp) ((bpp) << 0)
-#define DSCA_PICTURE_PARAMETER_SET_2 0x6B208
-#define DSCC_PICTURE_PARAMETER_SET_2 0x6BA08
+#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
+#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
@@ -10399,8 +10399,8 @@ enum skl_power_gate {
#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
-#define DSCA_PICTURE_PARAMETER_SET_3 0x6B20C
-#define DSCC_PICTURE_PARAMETER_SET_3 0x6BA0C
+#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
+#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
@@ -10414,8 +10414,8 @@ enum skl_power_gate {
#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
-#define DSCA_PICTURE_PARAMETER_SET_4 0x6B210
-#define DSCC_PICTURE_PARAMETER_SET_4 0x6BA10
+#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
+#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
@@ -10429,8 +10429,8 @@ enum skl_power_gate {
#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
-#define DSCA_PICTURE_PARAMETER_SET_5 0x6B214
-#define DSCC_PICTURE_PARAMETER_SET_5 0x6BA14
+#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
+#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
@@ -10441,11 +10441,11 @@ enum skl_power_gate {
#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
_ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
-#define DSC_SCALE_DEC_INTINT(scale_dec) ((scale_dec) << 16)
+#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
-#define DSCA_PICTURE_PARAMETER_SET_6 0x6B218
-#define DSCC_PICTURE_PARAMETER_SET_6 0x6BA18
+#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
+#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
@@ -10456,13 +10456,13 @@ enum skl_power_gate {
#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
-#define DSC_FLATNESS_MAX_QP(max_qp) (qp << 24)
-#define DSC_FLATNESS_MIN_QP(min_qp) (qp << 16)
+#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
+#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
-#define DSCA_PICTURE_PARAMETER_SET_7 0x6B21C
-#define DSCC_PICTURE_PARAMETER_SET_7 0x6BA1C
+#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
+#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
@@ -10476,8 +10476,8 @@ enum skl_power_gate {
#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
-#define DSCA_PICTURE_PARAMETER_SET_8 0x6B220
-#define DSCC_PICTURE_PARAMETER_SET_8 0x6BA20
+#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
+#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
@@ -10491,8 +10491,8 @@ enum skl_power_gate {
#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
-#define DSCA_PICTURE_PARAMETER_SET_9 0x6B224
-#define DSCC_PICTURE_PARAMETER_SET_9 0x6BA24
+#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
+#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
@@ -10506,8 +10506,8 @@ enum skl_power_gate {
#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
-#define DSCA_PICTURE_PARAMETER_SET_10 0x6B228
-#define DSCC_PICTURE_PARAMETER_SET_10 0x6BA28
+#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
+#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
@@ -10523,8 +10523,8 @@ enum skl_power_gate {
#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
-#define DSCA_PICTURE_PARAMETER_SET_11 0x6B22C
-#define DSCC_PICTURE_PARAMETER_SET_11 0x6BA2C
+#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
+#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
@@ -10536,8 +10536,8 @@ enum skl_power_gate {
_ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
-#define DSCA_PICTURE_PARAMETER_SET_12 0x6B260
-#define DSCC_PICTURE_PARAMETER_SET_12 0x6BA60
+#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
+#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
@@ -10549,8 +10549,8 @@ enum skl_power_gate {
_ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
-#define DSCA_PICTURE_PARAMETER_SET_13 0x6B264
-#define DSCC_PICTURE_PARAMETER_SET_13 0x6BA64
+#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
+#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
@@ -10562,8 +10562,8 @@ enum skl_power_gate {
_ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
-#define DSCA_PICTURE_PARAMETER_SET_14 0x6B268
-#define DSCC_PICTURE_PARAMETER_SET_14 0x6BA68
+#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
+#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
@@ -10575,8 +10575,8 @@ enum skl_power_gate {
_ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
-#define DSCA_PICTURE_PARAMETER_SET_15 0x6B26C
-#define DSCC_PICTURE_PARAMETER_SET_15 0x6BA6C
+#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
+#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
@@ -10588,8 +10588,8 @@ enum skl_power_gate {
_ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
-#define DSCA_PICTURE_PARAMETER_SET_16 0x6B270
-#define DSCC_PICTURE_PARAMETER_SET_16 0x6BA70
+#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
+#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
@@ -10601,7 +10601,7 @@ enum skl_power_gate {
_ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
-#define DSC_SLICE_CHUNK_SIZE(slice_chunk_aize) (slice_chunk_size << 0)
+#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
/* Icelake Rate Control Buffer Threshold Registers */
#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/dsc: Add missing _MMIO() from PPS registers (rev3)
2018-07-20 21:42 [v3] drm/i915/dsc: Add missing _MMIO() from PPS registers Anusha Srivatsa
@ 2018-07-20 22:40 ` Patchwork
2018-07-20 22:59 ` [v3] drm/i915/dsc: Add missing _MMIO() from PPS registers Rodrigo Vivi
2018-07-21 19:08 ` ✓ Fi.CI.IGT: success for drm/i915/dsc: Add missing _MMIO() from PPS registers (rev3) Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2018-07-20 22:40 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsc: Add missing _MMIO() from PPS registers (rev3)
URL : https://patchwork.freedesktop.org/series/46979/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4521 -> Patchwork_9741 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/46979/revisions/3/mbox/
== Known issues ==
Here are the changes found in Patchwork_9741 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_hangcheck:
fi-kbl-7560u: PASS -> DMESG-FAIL (fdo#106947, fdo#106560)
igt@drv_selftest@live_workarounds:
{fi-cfl-8109u}: PASS -> DMESG-FAIL (fdo#107292)
igt@gem_exec_suspend@basic-s4-devices:
fi-kbl-7500u: PASS -> DMESG-WARN (fdo#105128, fdo#107139)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: NOTRUN -> INCOMPLETE (fdo#103713)
==== Possible fixes ====
igt@debugfs_test@read_all_entries:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: FAIL (fdo#104008) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
== Participating hosts (47 -> 42) ==
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4521 -> Patchwork_9741
CI_DRM_4521: a4ebbd84c682fd30edbde6ac0e48d150d4c5c066 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4570: 65cdccdc7bcbb791d791aeeeecb784a382110a3c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9741: 2d67170971143977f59b4852f29c888fcb3b0d18 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2d6717097114 drm/i915/dsc: Add missing _MMIO() from PPS registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9741/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [v3] drm/i915/dsc: Add missing _MMIO() from PPS registers
2018-07-20 21:42 [v3] drm/i915/dsc: Add missing _MMIO() from PPS registers Anusha Srivatsa
2018-07-20 22:40 ` ✓ Fi.CI.BAT: success for drm/i915/dsc: Add missing _MMIO() from PPS registers (rev3) Patchwork
@ 2018-07-20 22:59 ` Rodrigo Vivi
2018-07-20 23:00 ` Srivatsa, Anusha
2018-07-21 19:08 ` ✓ Fi.CI.IGT: success for drm/i915/dsc: Add missing _MMIO() from PPS registers (rev3) Patchwork
2 siblings, 1 reply; 5+ messages in thread
From: Rodrigo Vivi @ 2018-07-20 22:59 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Fri, Jul 20, 2018 at 02:42:42PM -0700, Anusha Srivatsa wrote:
> This patch fixes the commit -
> <2efbb2f099fb> ("i915/dp/dsc: Add DSC PPS register definitions"),
> which did not have _MMIO() for DSCA and DSCC.
>
> v2: Fix typos. (manasi)
>
> v3: Change the commit message (Rodrigo)
>
> Cc: Rodrigi Vivi <rodrigo.vivi@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
pushed to dinq, thanks
> ---
> drivers/gpu/drm/i915/i915_reg.h | 76 ++++++++++++++++++++---------------------
> 1 file changed, 38 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8af945d..7394605 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10349,8 +10349,8 @@ enum skl_power_gate {
> #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
>
> /* Icelake Display Stream Compression Registers */
> -#define DSCA_PICTURE_PARAMETER_SET_0 0x6B200
> -#define DSCC_PICTURE_PARAMETER_SET_0 0x6BA00
> +#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
> +#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
> @@ -10370,8 +10370,8 @@ enum skl_power_gate {
> #define DSC_VER_MIN_SHIFT 4
> #define DSC_VER_MAJ (0x1 << 0)
>
> -#define DSCA_PICTURE_PARAMETER_SET_1 0x6B204
> -#define DSCC_PICTURE_PARAMETER_SET_1 0x6BA04
> +#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
> +#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
> @@ -10384,8 +10384,8 @@ enum skl_power_gate {
> _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
> #define DSC_BPP(bpp) ((bpp) << 0)
>
> -#define DSCA_PICTURE_PARAMETER_SET_2 0x6B208
> -#define DSCC_PICTURE_PARAMETER_SET_2 0x6BA08
> +#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
> +#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
> @@ -10399,8 +10399,8 @@ enum skl_power_gate {
> #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
> #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
>
> -#define DSCA_PICTURE_PARAMETER_SET_3 0x6B20C
> -#define DSCC_PICTURE_PARAMETER_SET_3 0x6BA0C
> +#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
> +#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
> @@ -10414,8 +10414,8 @@ enum skl_power_gate {
> #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
> #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
>
> -#define DSCA_PICTURE_PARAMETER_SET_4 0x6B210
> -#define DSCC_PICTURE_PARAMETER_SET_4 0x6BA10
> +#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
> +#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
> @@ -10429,8 +10429,8 @@ enum skl_power_gate {
> #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
> #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
>
> -#define DSCA_PICTURE_PARAMETER_SET_5 0x6B214
> -#define DSCC_PICTURE_PARAMETER_SET_5 0x6BA14
> +#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
> +#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
> @@ -10441,11 +10441,11 @@ enum skl_power_gate {
> #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
> _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
> -#define DSC_SCALE_DEC_INTINT(scale_dec) ((scale_dec) << 16)
> +#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
> #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
>
> -#define DSCA_PICTURE_PARAMETER_SET_6 0x6B218
> -#define DSCC_PICTURE_PARAMETER_SET_6 0x6BA18
> +#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
> +#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
> @@ -10456,13 +10456,13 @@ enum skl_power_gate {
> #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
> _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
> -#define DSC_FLATNESS_MAX_QP(max_qp) (qp << 24)
> -#define DSC_FLATNESS_MIN_QP(min_qp) (qp << 16)
> +#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
> +#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
> #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
> #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
>
> -#define DSCA_PICTURE_PARAMETER_SET_7 0x6B21C
> -#define DSCC_PICTURE_PARAMETER_SET_7 0x6BA1C
> +#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
> +#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
> @@ -10476,8 +10476,8 @@ enum skl_power_gate {
> #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
> #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
>
> -#define DSCA_PICTURE_PARAMETER_SET_8 0x6B220
> -#define DSCC_PICTURE_PARAMETER_SET_8 0x6BA20
> +#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
> +#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
> @@ -10491,8 +10491,8 @@ enum skl_power_gate {
> #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
> #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
>
> -#define DSCA_PICTURE_PARAMETER_SET_9 0x6B224
> -#define DSCC_PICTURE_PARAMETER_SET_9 0x6BA24
> +#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
> +#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
> @@ -10506,8 +10506,8 @@ enum skl_power_gate {
> #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
> #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
>
> -#define DSCA_PICTURE_PARAMETER_SET_10 0x6B228
> -#define DSCC_PICTURE_PARAMETER_SET_10 0x6BA28
> +#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
> +#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
> @@ -10523,8 +10523,8 @@ enum skl_power_gate {
> #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
> #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
>
> -#define DSCA_PICTURE_PARAMETER_SET_11 0x6B22C
> -#define DSCC_PICTURE_PARAMETER_SET_11 0x6BA2C
> +#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
> +#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
> @@ -10536,8 +10536,8 @@ enum skl_power_gate {
> _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
> _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
>
> -#define DSCA_PICTURE_PARAMETER_SET_12 0x6B260
> -#define DSCC_PICTURE_PARAMETER_SET_12 0x6BA60
> +#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
> +#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
> @@ -10549,8 +10549,8 @@ enum skl_power_gate {
> _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
> _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
>
> -#define DSCA_PICTURE_PARAMETER_SET_13 0x6B264
> -#define DSCC_PICTURE_PARAMETER_SET_13 0x6BA64
> +#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
> +#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
> @@ -10562,8 +10562,8 @@ enum skl_power_gate {
> _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
> _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
>
> -#define DSCA_PICTURE_PARAMETER_SET_14 0x6B268
> -#define DSCC_PICTURE_PARAMETER_SET_14 0x6BA68
> +#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
> +#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
> @@ -10575,8 +10575,8 @@ enum skl_power_gate {
> _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
> _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
>
> -#define DSCA_PICTURE_PARAMETER_SET_15 0x6B26C
> -#define DSCC_PICTURE_PARAMETER_SET_15 0x6BA6C
> +#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
> +#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
> @@ -10588,8 +10588,8 @@ enum skl_power_gate {
> _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
> _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
>
> -#define DSCA_PICTURE_PARAMETER_SET_16 0x6B270
> -#define DSCC_PICTURE_PARAMETER_SET_16 0x6BA70
> +#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
> +#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
> #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
> #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
> @@ -10601,7 +10601,7 @@ enum skl_power_gate {
> _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
> _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
> #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
> -#define DSC_SLICE_CHUNK_SIZE(slice_chunk_aize) (slice_chunk_size << 0)
> +#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
>
> /* Icelake Rate Control Buffer Threshold Registers */
> #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
> --
> 2.7.4
>
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [v3] drm/i915/dsc: Add missing _MMIO() from PPS registers
2018-07-20 22:59 ` [v3] drm/i915/dsc: Add missing _MMIO() from PPS registers Rodrigo Vivi
@ 2018-07-20 23:00 ` Srivatsa, Anusha
0 siblings, 0 replies; 5+ messages in thread
From: Srivatsa, Anusha @ 2018-07-20 23:00 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx@lists.freedesktop.org
>-----Original Message-----
>From: Vivi, Rodrigo
>Sent: Friday, July 20, 2018 3:59 PM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Navare, Manasi D
><manasi.d.navare@intel.com>
>Subject: Re: [v3] drm/i915/dsc: Add missing _MMIO() from PPS registers
>
>On Fri, Jul 20, 2018 at 02:42:42PM -0700, Anusha Srivatsa wrote:
>> This patch fixes the commit -
>> <2efbb2f099fb> ("i915/dp/dsc: Add DSC PPS register definitions"),
>> which did not have _MMIO() for DSCA and DSCC.
>>
>> v2: Fix typos. (manasi)
>>
>> v3: Change the commit message (Rodrigo)
>>
>> Cc: Rodrigi Vivi <rodrigo.vivi@intel.com>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>
>pushed to dinq, thanks
Thanks you very much!
Anusha
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 76
>> ++++++++++++++++++++---------------------
>> 1 file changed, 38 insertions(+), 38 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 8af945d..7394605 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -10349,8 +10349,8 @@ enum skl_power_gate {
>> #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
>>
>> /* Icelake Display Stream Compression Registers */
>> -#define DSCA_PICTURE_PARAMETER_SET_0 0x6B200
>> -#define DSCC_PICTURE_PARAMETER_SET_0 0x6BA00
>> +#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
>> +#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
>> @@ -10370,8 +10370,8 @@ enum skl_power_gate {
>> #define DSC_VER_MIN_SHIFT 4
>> #define DSC_VER_MAJ (0x1 << 0)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_1 0x6B204
>> -#define DSCC_PICTURE_PARAMETER_SET_1 0x6BA04
>> +#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
>> +#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
>> @@ -10384,8 +10384,8 @@ enum skl_power_gate {
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
>> #define DSC_BPP(bpp) ((bpp) << 0)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_2 0x6B208
>> -#define DSCC_PICTURE_PARAMETER_SET_2 0x6BA08
>> +#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
>> +#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
>> @@ -10399,8 +10399,8 @@ enum skl_power_gate {
>> #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
>> #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_3 0x6B20C
>> -#define DSCC_PICTURE_PARAMETER_SET_3 0x6BA0C
>> +#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
>> +#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
>> @@ -10414,8 +10414,8 @@ enum skl_power_gate {
>> #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
>> #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_4 0x6B210
>> -#define DSCC_PICTURE_PARAMETER_SET_4 0x6BA10
>> +#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
>> +#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
>> @@ -10429,8 +10429,8 @@ enum skl_power_gate {
>> #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
>> #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_5 0x6B214
>> -#define DSCC_PICTURE_PARAMETER_SET_5 0x6BA14
>> +#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
>> +#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
>> @@ -10441,11 +10441,11 @@ enum skl_power_gate {
>> #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) -
>PIPE_B, \
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
>> -#define DSC_SCALE_DEC_INTINT(scale_dec) ((scale_dec) << 16)
>> +#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
>> #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_6 0x6B218
>> -#define DSCC_PICTURE_PARAMETER_SET_6 0x6BA18
>> +#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
>> +#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
>> @@ -10456,13 +10456,13 @@ enum skl_power_gate {
>> #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) -
>PIPE_B, \
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
>> -#define DSC_FLATNESS_MAX_QP(max_qp) (qp << 24)
>> -#define DSC_FLATNESS_MIN_QP(min_qp) (qp << 16)
>> +#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
>> +#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
>> #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
>> #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_7 0x6B21C
>> -#define DSCC_PICTURE_PARAMETER_SET_7 0x6BA1C
>> +#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
>> +#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
>> @@ -10476,8 +10476,8 @@ enum skl_power_gate {
>> #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
>> #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_8 0x6B220
>> -#define DSCC_PICTURE_PARAMETER_SET_8 0x6BA20
>> +#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
>> +#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
>> @@ -10491,8 +10491,8 @@ enum skl_power_gate {
>> #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
>> #define DSC_FINAL_OFFSET(final_offset) ((final_offset)
><< 0)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_9 0x6B224
>> -#define DSCC_PICTURE_PARAMETER_SET_9 0x6BA24
>> +#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
>> +#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
>> @@ -10506,8 +10506,8 @@ enum skl_power_gate {
>> #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
>> #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_10 0x6B228
>> -#define DSCC_PICTURE_PARAMETER_SET_10 0x6BA28
>> +#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
>> +#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
>> @@ -10523,8 +10523,8 @@ enum skl_power_gate {
>> #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
>> #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_11 0x6B22C
>> -#define DSCC_PICTURE_PARAMETER_SET_11 0x6BA2C
>> +#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
>> +#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
>> @@ -10536,8 +10536,8 @@ enum skl_power_gate {
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_12 0x6B260
>> -#define DSCC_PICTURE_PARAMETER_SET_12 0x6BA60
>> +#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
>> +#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
>> @@ -10549,8 +10549,8 @@ enum skl_power_gate {
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_13 0x6B264
>> -#define DSCC_PICTURE_PARAMETER_SET_13 0x6BA64
>> +#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
>> +#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
>> @@ -10562,8 +10562,8 @@ enum skl_power_gate {
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_14 0x6B268
>> -#define DSCC_PICTURE_PARAMETER_SET_14 0x6BA68
>> +#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
>> +#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
>> @@ -10575,8 +10575,8 @@ enum skl_power_gate {
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_15 0x6B26C
>> -#define DSCC_PICTURE_PARAMETER_SET_15 0x6BA6C
>> +#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
>> +#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
>> @@ -10588,8 +10588,8 @@ enum skl_power_gate {
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
>>
>> -#define DSCA_PICTURE_PARAMETER_SET_16 0x6B270
>> -#define DSCC_PICTURE_PARAMETER_SET_16 0x6BA70
>> +#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
>> +#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
>> #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
>> #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
>> @@ -10601,7 +10601,7 @@ enum skl_power_gate {
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
>>
>_ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
>> #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
>> -#define DSC_SLICE_CHUNK_SIZE(slice_chunk_aize)
> (slice_chunk_size << 0)
>> +#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size)
> ((slice_chunk_size) << 0)
>>
>> /* Icelake Rate Control Buffer Threshold Registers */
>> #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
>> --
>> 2.7.4
>>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/dsc: Add missing _MMIO() from PPS registers (rev3)
2018-07-20 21:42 [v3] drm/i915/dsc: Add missing _MMIO() from PPS registers Anusha Srivatsa
2018-07-20 22:40 ` ✓ Fi.CI.BAT: success for drm/i915/dsc: Add missing _MMIO() from PPS registers (rev3) Patchwork
2018-07-20 22:59 ` [v3] drm/i915/dsc: Add missing _MMIO() from PPS registers Rodrigo Vivi
@ 2018-07-21 19:08 ` Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2018-07-21 19:08 UTC (permalink / raw)
To: Srivatsa, Anusha; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsc: Add missing _MMIO() from PPS registers (rev3)
URL : https://patchwork.freedesktop.org/series/46979/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4521_full -> Patchwork_9741_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9741_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9741_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9741_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-bsd2:
shard-kbl: SKIP -> PASS +1
igt@gem_exec_schedule@deep-vebox:
shard-kbl: PASS -> SKIP +1
== Known issues ==
Here are the changes found in Patchwork_9741_full that come from known issues:
=== IGT changes ===
==== Possible fixes ====
igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
shard-hsw: FAIL (fdo#105767) -> PASS
igt@kms_flip@dpms-vs-vblank-race:
shard-glk: FAIL (fdo#103060) -> PASS
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4521 -> Patchwork_9741
CI_DRM_4521: a4ebbd84c682fd30edbde6ac0e48d150d4c5c066 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4570: 65cdccdc7bcbb791d791aeeeecb784a382110a3c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9741: 2d67170971143977f59b4852f29c888fcb3b0d18 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9741/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-07-21 19:08 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-07-20 21:42 [v3] drm/i915/dsc: Add missing _MMIO() from PPS registers Anusha Srivatsa
2018-07-20 22:40 ` ✓ Fi.CI.BAT: success for drm/i915/dsc: Add missing _MMIO() from PPS registers (rev3) Patchwork
2018-07-20 22:59 ` [v3] drm/i915/dsc: Add missing _MMIO() from PPS registers Rodrigo Vivi
2018-07-20 23:00 ` Srivatsa, Anusha
2018-07-21 19:08 ` ✓ Fi.CI.IGT: success for drm/i915/dsc: Add missing _MMIO() from PPS registers (rev3) Patchwork
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