[PATCH v5 1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias

[PATCH v5 1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias

[Jakub Bartmiński]

It would appear that the calculated GuC pin bias was larger than it should
be, as the GuC address space does NOT contain the "HW contexts RSVD" part
of the WOPCM. Thus, the GuC pin bias is simply the GuC WOPCM size.

v5:
Clarify the diagram to better represent the GuC address space.
Since we now don't use guc.base for the pin bias there's no need to
validate it. It also has already been verified in WOPCM init.

Bspec: 1180

Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c | 49 +++++++++++++-------------------
 1 file changed, 20 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index e12bd259df17..aa28368f8ba7 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -582,50 +582,41 @@ int intel_guc_resume(struct intel_guc *guc)
  *
  * ::
  *
- *     +==============> +====================+ <== GUC_GGTT_TOP
- *     ^                |                    |
- *     |                |                    |
- *     |                |        DRAM        |
- *     |                |       Memory       |
- *     |                |                    |
- *    GuC               |                    |
- *  Address  +========> +====================+ <== WOPCM Top
- *   Space   ^          |   HW contexts RSVD |
- *     |     |          |        WOPCM       |
- *     |     |     +==> +--------------------+ <== GuC WOPCM Top
- *     |    GuC    ^    |                    |
- *     |    GGTT   |    |                    |
- *     |    Pin   GuC   |        GuC         |
- *     |    Bias WOPCM  |       WOPCM        |
- *     |     |    Size  |                    |
- *     |     |     |    |                    |
- *     v     v     v    |                    |
- *     +=====+=====+==> +====================+ <== GuC WOPCM Base
- *                      |   Non-GuC WOPCM    |
- *                      |   (HuC/Reserved)   |
- *                      +====================+ <== WOPCM Base
+ *     +===========> +====================+ <== FFFF_FFFF
+ *     ^             |      Reserved      |
+ *     |             +====================+ <== GUC_GGTT_TOP
+ *     |             |                    |
+ *     |             |        DRAM        |
+ *    GuC            |                    |
+ *  Address    +===> +====================+ <== GuC ggtt_pin_bias
+ *   Space     ^     |                    |
+ *     |       |     |                    |
+ *     |      GuC    |        GuC         |
+ *     |     WOPCM   |       WOPCM        |
+ *     |      Size   |                    |
+ *     |       |     |                    |
+ *     v       v     |                    |
+ *     +=======+===> +====================+ <== 0000_0000
  *
- * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to WOPCM
+ * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM
  * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
- * to DRAM. The value of the GuC ggtt_pin_bias is determined by WOPCM size and
- * actual GuC WOPCM size.
+ * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.
  */
 
 /**
  * guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
  * @guc: intel_guc structure.
  *
- * This function will calculate and initialize the ggtt_pin_bias value based on
- * overall WOPCM size and GuC WOPCM size.
+ * This function will calculate and initialize the ggtt_pin_bias value
+ * based on the GuC WOPCM size.
  */
 static void guc_init_ggtt_pin_bias(struct intel_guc *guc)
 {
 	struct drm_i915_private *i915 = guc_to_i915(guc);
 
 	GEM_BUG_ON(!i915->wopcm.size);
-	GEM_BUG_ON(i915->wopcm.size < i915->wopcm.guc.base);
 
-	guc->ggtt_pin_bias = i915->wopcm.size - i915->wopcm.guc.base;
+	guc->ggtt_pin_bias = i915->wopcm.guc.size;
 }
 
 /**
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v5 2/5] drm/i915/guc: Move the pin bias value from GuC to GGTT

[Jakub Bartmiński]

Removing the pin bias from GuC allows us to not check for GuC every time
we pin a context, which fixes the assertion error on unresolved GuC
platform default in mock contexts selftest.

It also seems that we were using uninitialized WOPCM variables when
setting the GuC pin bias. The pin bias has to be set after the WOPCM,
but before the call to i915_gem_contexts_init where the first contexts
are pinned.

v2:
This also makes it so that there's no need to set GuC variables from
within the WOPCM init function or to move the WOPCM init, while keeping
the correct initialization order. Also for mock tests the pin bias is
left at 0 and we make sure that the pin bias with GuC will not be
smaller than without GuC.

v3:
Avoid unused i915 in intel_guc_ggtt_offset if debug is disabled.

v4:
Squash with WOPCM init reordering.
Moved the i915_ggtt_pin_bias helper to this patch, and made some
functions use it instead of directly dereferencing i915->ggtt.

v5:
Since we now don't use wopcm.guc.base for the pin bias there's no need to
validate it. It also has already been verified in WOPCM init.

Fixes: f7dc0157e4b5 ("drm/i915/uc: Fetch GuC/HuC firmwares from guc/huc specific init")
Testcase: igt/drv_selftest/mock_contexts #GuC
Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c | 22 ++++++------------
 drivers/gpu/drm/i915/i915_gem_gtt.c     | 18 ++++++++++----
 drivers/gpu/drm/i915/i915_gem_gtt.h     |  2 ++
 drivers/gpu/drm/i915/i915_vma.h         |  5 ++++
 drivers/gpu/drm/i915/intel_guc.c        | 31 +++++--------------------
 drivers/gpu/drm/i915/intel_guc.h        | 11 ++++-----
 drivers/gpu/drm/i915/intel_huc.c        |  2 +-
 drivers/gpu/drm/i915/intel_uc_fw.c      |  2 +-
 drivers/gpu/drm/i915/intel_wopcm.h      | 16 +++++++++++++
 9 files changed, 55 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index b10770cfccd2..ae27caad1766 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -265,7 +265,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
 }
 
 static struct i915_gem_context *
-__create_hw_context(struct drm_i915_private *dev_priv,
+__create_hw_context(struct drm_i915_private *i915,
 		    struct drm_i915_file_private *file_priv)
 {
 	struct i915_gem_context *ctx;
@@ -276,15 +276,15 @@ __create_hw_context(struct drm_i915_private *dev_priv,
 	if (ctx == NULL)
 		return ERR_PTR(-ENOMEM);
 
-	ret = assign_hw_id(dev_priv, &ctx->hw_id);
+	ret = assign_hw_id(i915, &ctx->hw_id);
 	if (ret) {
 		kfree(ctx);
 		return ERR_PTR(ret);
 	}
 
 	kref_init(&ctx->ref);
-	list_add_tail(&ctx->link, &dev_priv->contexts.list);
-	ctx->i915 = dev_priv;
+	list_add_tail(&ctx->link, &i915->contexts.list);
+	ctx->i915 = i915;
 	ctx->sched.priority = I915_PRIORITY_NORMAL;
 
 	for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {
@@ -322,22 +322,14 @@ __create_hw_context(struct drm_i915_private *dev_priv,
 	/* NB: Mark all slices as needing a remap so that when the context first
 	 * loads it will restore whatever remap state already exists. If there
 	 * is no remap info, it will be a NOP. */
-	ctx->remap_slice = ALL_L3_SLICES(dev_priv);
+	ctx->remap_slice = ALL_L3_SLICES(i915);
 
 	i915_gem_context_set_bannable(ctx);
 	ctx->ring_size = 4 * PAGE_SIZE;
 	ctx->desc_template =
-		default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
+		default_desc_template(i915, i915->mm.aliasing_ppgtt);
 
-	/*
-	 * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not
-	 * present or not in use we still need a small bias as ring wraparound
-	 * at offset 0 sometimes hangs. No idea why.
-	 */
-	if (USES_GUC(dev_priv))
-		ctx->ggtt_offset_bias = dev_priv->guc.ggtt_pin_bias;
-	else
-		ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
+	ctx->ggtt_offset_bias = i915->ggtt.pin_bias;
 
 	return ctx;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d0acef299b9c..1f5d0334f0f5 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2901,7 +2901,7 @@ void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915)
 	ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
 }
 
-int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
+int i915_gem_init_ggtt(struct drm_i915_private *i915)
 {
 	/* Let GEM Manage all of the aperture.
 	 *
@@ -2912,12 +2912,20 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	 * aperture.  One page should be enough to keep any prefetching inside
 	 * of the aperture.
 	 */
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
+	struct i915_ggtt *ggtt = &i915->ggtt;
 	unsigned long hole_start, hole_end;
 	struct drm_mm_node *entry;
 	int ret;
 
-	ret = intel_vgt_balloon(dev_priv);
+	/*
+	 * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not
+	 * present or not in use we still need a small bias as ring wraparound
+	 * at offset 0 sometimes hangs. No idea why.
+	 */
+	ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
+			       intel_wopcm_guc_pin_bias(&i915->wopcm));
+
+	ret = intel_vgt_balloon(i915);
 	if (ret)
 		return ret;
 
@@ -2940,8 +2948,8 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	/* And finally clear the reserved guard page */
 	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
 
-	if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
-		ret = i915_gem_init_aliasing_ppgtt(dev_priv);
+	if (USES_PPGTT(i915) && !USES_FULL_PPGTT(i915)) {
+		ret = i915_gem_init_aliasing_ppgtt(i915);
 		if (ret)
 			goto err;
 	}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 14e62651010b..71e8cf24c800 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -396,6 +396,8 @@ struct i915_ggtt {
 
 	int mtrr;
 
+	u32 pin_bias;
+
 	struct drm_mm_node error_capture;
 };
 
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index f06d66377107..abf6144e3296 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -207,6 +207,11 @@ static inline u32 i915_ggtt_offset(const struct i915_vma *vma)
 	return lower_32_bits(vma->node.start);
 }
 
+static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
+{
+	return i915_vm_to_ggtt(vma->vm)->pin_bias;
+}
+
 static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
 {
 	i915_gem_object_get(vma->obj);
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index aa28368f8ba7..74043a13e9bc 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -27,8 +27,6 @@
 #include "intel_guc_submission.h"
 #include "i915_drv.h"
 
-static void guc_init_ggtt_pin_bias(struct intel_guc *guc);
-
 static void gen8_guc_raise_irq(struct intel_guc *guc)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -142,8 +140,6 @@ int intel_guc_init_misc(struct intel_guc *guc)
 	struct drm_i915_private *i915 = guc_to_i915(guc);
 	int ret;
 
-	guc_init_ggtt_pin_bias(guc);
-
 	ret = guc_init_wq(guc);
 	if (ret)
 		return ret;
@@ -603,22 +599,6 @@ int intel_guc_resume(struct intel_guc *guc)
  * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.
  */
 
-/**
- * guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
- * @guc: intel_guc structure.
- *
- * This function will calculate and initialize the ggtt_pin_bias value
- * based on the GuC WOPCM size.
- */
-static void guc_init_ggtt_pin_bias(struct intel_guc *guc)
-{
-	struct drm_i915_private *i915 = guc_to_i915(guc);
-
-	GEM_BUG_ON(!i915->wopcm.size);
-
-	guc->ggtt_pin_bias = i915->wopcm.guc.size;
-}
-
 /**
  * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
  * @guc:	the guc
@@ -634,21 +614,22 @@ static void guc_init_ggtt_pin_bias(struct intel_guc *guc)
  */
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 {
-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	struct drm_i915_private *i915 = guc_to_i915(guc);
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
+	u64 flags;
 	int ret;
 
-	obj = i915_gem_object_create(dev_priv, size);
+	obj = i915_gem_object_create(i915, size);
 	if (IS_ERR(obj))
 		return ERR_CAST(obj);
 
-	vma = i915_vma_instance(obj, &dev_priv->ggtt.vm, NULL);
+	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
 	if (IS_ERR(vma))
 		goto err;
 
-	ret = i915_vma_pin(vma, 0, PAGE_SIZE,
-			   PIN_GLOBAL | PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
+	flags = PIN_GLOBAL | PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
+	ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags);
 	if (ret) {
 		vma = ERR_PTR(ret);
 		goto err;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 4121928a495e..751f31c3c6c4 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -49,9 +49,6 @@ struct intel_guc {
 	struct intel_guc_log log;
 	struct intel_guc_ct ct;
 
-	/* Offset where Non-WOPCM memory starts. */
-	u32 ggtt_pin_bias;
-
 	/* Log snapshot if GuC errors during load */
 	struct drm_i915_gem_object *load_err_log;
 
@@ -130,10 +127,10 @@ static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
  * @vma: i915 graphics virtual memory area.
  *
  * GuC does not allow any gfx GGTT address that falls into range
- * [0, GuC ggtt_pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
- * Currently, in order to exclude [0, GuC ggtt_pin_bias) address space from
+ * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
+ * Currently, in order to exclude [0, ggtt.pin_bias) address space from
  * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
- * and pinned with PIN_OFFSET_BIAS along with the value of GuC ggtt_pin_bias.
+ * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
  *
  * Return: GGTT offset of the @vma.
  */
@@ -142,7 +139,7 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
 {
 	u32 offset = i915_ggtt_offset(vma);
 
-	GEM_BUG_ON(offset < guc->ggtt_pin_bias);
+	GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
 	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
 
 	return offset;
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index ffcad5fad6a7..37ef540dd280 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -63,7 +63,7 @@ int intel_huc_auth(struct intel_huc *huc)
 		return -ENOEXEC;
 
 	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
-				       PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
+				       PIN_OFFSET_BIAS | i915->ggtt.pin_bias);
 	if (IS_ERR(vma)) {
 		ret = PTR_ERR(vma);
 		DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
index 6e8e0b546743..fd496416087c 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -222,7 +222,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
 		goto fail;
 	}
 
-	ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->guc.ggtt_pin_bias;
+	ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->ggtt.pin_bias;
 	vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
 				       PIN_OFFSET_BIAS | ggtt_pin_bias);
 	if (IS_ERR(vma)) {
diff --git a/drivers/gpu/drm/i915/intel_wopcm.h b/drivers/gpu/drm/i915/intel_wopcm.h
index 6298910a384c..0130165a9cdd 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.h
+++ b/drivers/gpu/drm/i915/intel_wopcm.h
@@ -7,6 +7,8 @@
 #ifndef _INTEL_WOPCM_H_
 #define _INTEL_WOPCM_H_
 
+#include "i915_gem.h"
+#include "i915_utils.h"
 #include <linux/types.h>
 
 /**
@@ -24,6 +26,20 @@ struct intel_wopcm {
 	} guc;
 };
 
+/**
+ * intel_wopcm_guc_pin_bias() - Get the GuC pin bias value.
+ * @wopcm: pointer to intel_wopcm.
+ *
+ * Returns:
+ * 0 if GuC is not present or not in use.
+ * Otherwise, the GuC pin bias value based on the GuC WOPCM size.
+ */
+static inline u32 intel_wopcm_guc_pin_bias(struct intel_wopcm *wopcm)
+{
+	GEM_BUG_ON(!wopcm->size);
+	return wopcm->guc.size;
+}
+
 void intel_wopcm_init_early(struct intel_wopcm *wopcm);
 int intel_wopcm_init(struct intel_wopcm *wopcm);
 int intel_wopcm_init_hw(struct intel_wopcm *wopcm);
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v5 3/5] drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context

[Jakub Bartmiński]

Since ggtt_offset_bias is now stored in ggtt.pin_bias, it is duplicated
inside i915_gem_context, and can instead be accessed directly from ggtt.

v3:
Added a helper function to retrieve the ggtt.pin_bias from the vma.

v4:
Moved the helper function to the previous patch in the series.
Dropped the bias from intel_ring_pin. This introduces a slight functional
change since we are always pinning a ring a bit higher if GuC is present
even though we don't really need to.

Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c |  2 --
 drivers/gpu/drm/i915/i915_gem_context.h |  3 ---
 drivers/gpu/drm/i915/intel_lrc.c        |  6 ++----
 drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++++++--------
 drivers/gpu/drm/i915/intel_ringbuffer.h |  4 +---
 5 files changed, 9 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index ae27caad1766..6067563750de 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -329,8 +329,6 @@ __create_hw_context(struct drm_i915_private *i915,
 	ctx->desc_template =
 		default_desc_template(i915, i915->mm.aliasing_ppgtt);
 
-	ctx->ggtt_offset_bias = i915->ggtt.pin_bias;
-
 	return ctx;
 
 err_pid:
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h
index b116e4942c10..851dad6decd7 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -147,9 +147,6 @@ struct i915_gem_context {
 
 	struct i915_sched_attr sched;
 
-	/** ggtt_offset_bias: placement restriction for context objects */
-	u32 ggtt_offset_bias;
-
 	/** engine: per-engine logical HW state */
 	struct intel_context {
 		struct i915_gem_context *gem_context;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 35d37af0cb9a..c923eb998c28 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1363,9 +1363,7 @@ static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
 	}
 
 	flags = PIN_GLOBAL | PIN_HIGH;
-	if (ctx->ggtt_offset_bias)
-		flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
-
+	flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
 	return i915_vma_pin(vma, 0, GEN8_LR_CONTEXT_ALIGN, flags);
 }
 
@@ -1392,7 +1390,7 @@ __execlists_context_pin(struct intel_engine_cs *engine,
 		goto unpin_vma;
 	}
 
-	ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias);
+	ret = intel_ring_pin(ce->ring, ctx->i915);
 	if (ret)
 		goto unpin_map;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f4bd185c9369..8a48325249a3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1005,9 +1005,7 @@ i915_emit_bb_start(struct i915_request *rq,
 
 
 
-int intel_ring_pin(struct intel_ring *ring,
-		   struct drm_i915_private *i915,
-		   unsigned int offset_bias)
+int intel_ring_pin(struct intel_ring *ring, struct drm_i915_private *i915)
 {
 	enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
 	struct i915_vma *vma = ring->vma;
@@ -1017,10 +1015,11 @@ int intel_ring_pin(struct intel_ring *ring,
 
 	GEM_BUG_ON(ring->vaddr);
 
-
 	flags = PIN_GLOBAL;
-	if (offset_bias)
-		flags |= PIN_OFFSET_BIAS | offset_bias;
+
+	/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
+	flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
+
 	if (vma->obj->stolen)
 		flags |= PIN_MAPPABLE;
 	else
@@ -1404,8 +1403,7 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
 		goto err;
 	}
 
-	/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
-	err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE);
+	err = intel_ring_pin(ring, engine->i915);
 	if (err)
 		goto err_ring;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index d1eee08e5f6b..7fe07b2de2a7 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -784,9 +784,7 @@ struct intel_ring *
 intel_engine_create_ring(struct intel_engine_cs *engine,
 			 struct i915_timeline *timeline,
 			 int size);
-int intel_ring_pin(struct intel_ring *ring,
-		   struct drm_i915_private *i915,
-		   unsigned int offset_bias);
+int intel_ring_pin(struct intel_ring *ring, struct drm_i915_private *i915);
 void intel_ring_reset(struct intel_ring *ring, u32 tail);
 unsigned int intel_ring_update_space(struct intel_ring *ring);
 void intel_ring_unpin(struct intel_ring *ring);
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v5 4/5] drm/i915: Add a fault injection point to WOPCM init

[Jakub Bartmiński]

v4:
Move the injection inside the WOPCM init.

Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/intel_wopcm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
index 74bf76f3fddc..86c38b072926 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -165,6 +165,9 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
 
 	GEM_BUG_ON(!wopcm->size);
 
+	if (i915_inject_load_failure())
+		return -E2BIG;
+
 	if (guc_fw_size >= wopcm->size) {
 		DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
 			  guc_fw_size / 1024);
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v5 5/5] HAX enable GuC for CI

[Jakub Bartmiński]

From: Michal Wajdeczko <michal.wajdeczko@intel.com>

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index aebe0469ddaa..3e4e128237ac 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@ struct drm_printer;
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
 	param(int, invert_brightness, 0) \
-	param(int, enable_guc, 0) \
+	param(int, enable_guc, -1) \
 	param(int, guc_log_level, -1) \
 	param(char *, guc_firmware_path, NULL) \
 	param(char *, huc_firmware_path, NULL) \
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.SPARSE: warning for series starting with [v5,1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias
URL   : https://patchwork.freedesktop.org/series/47201/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias
Okay!

Commit: drm/i915/guc: Move the pin bias value from GuC to GGTT
+drivers/gpu/drm/i915/i915_gem_gtt.c:2937:26: warning: expression using sizeof(void)

Commit: drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context
Okay!

Commit: drm/i915: Add a fault injection point to WOPCM init
Okay!

Commit: HAX enable GuC for CI
Okay!

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for series starting with [v5,1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias
URL   : https://patchwork.freedesktop.org/series/47201/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4539 -> Patchwork_9763 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9763 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9763, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/47201/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9763:

  === IGT changes ===

    ==== Possible regressions ====

    igt@drv_module_reload@basic-reload:
      {fi-skl-iommu}:     PASS -> FAIL

    igt@drv_selftest@live_guc:
      fi-kbl-7567u:       PASS -> DMESG-WARN
      fi-skl-gvtdvm:      PASS -> DMESG-WARN
      fi-bxt-dsi:         PASS -> DMESG-WARN
      fi-whl-u:           PASS -> DMESG-WARN
      fi-kbl-7560u:       PASS -> DMESG-WARN
      {fi-kbl-8809g}:     PASS -> DMESG-WARN
      fi-kbl-r:           PASS -> DMESG-WARN
      fi-kbl-x1275:       PASS -> DMESG-WARN
      fi-bxt-j4205:       PASS -> DMESG-WARN
      fi-cfl-s3:          PASS -> DMESG-WARN
      {fi-cfl-8109u}:     PASS -> DMESG-WARN
      fi-kbl-7500u:       PASS -> DMESG-WARN
      fi-cfl-8700k:       PASS -> DMESG-WARN

    igt@drv_selftest@live_hangcheck:
      fi-bxt-dsi:         PASS -> DMESG-FAIL
      fi-bxt-j4205:       PASS -> DMESG-FAIL

    
== Known issues ==

  Here are the changes found in Patchwork_9763 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_guc:
      fi-skl-6600u:       PASS -> DMESG-WARN (fdo#107175)
      {fi-skl-iommu}:     PASS -> DMESG-WARN (fdo#107175)
      fi-skl-6260u:       PASS -> DMESG-WARN (fdo#107175)
      fi-skl-6700k2:      PASS -> DMESG-WARN (fdo#107175)
      fi-skl-6770hq:      PASS -> DMESG-WARN (fdo#107175)
      fi-skl-6700hq:      PASS -> DMESG-WARN (fdo#107175)

    igt@drv_selftest@live_objects:
      {fi-icl-u}:         NOTRUN -> DMESG-FAIL (fdo#107339)

    igt@gem_exec_suspend@basic-s4-devices:
      fi-snb-2520m:       NOTRUN -> FAIL (fdo#106825)

    igt@gem_workarounds@basic-read:
      {fi-icl-u}:         NOTRUN -> FAIL (fdo#107338)

    igt@kms_flip@basic-flip-vs-wf_vblank:
      {fi-icl-u}:         NOTRUN -> DMESG-WARN (fdo#107335) +42
      fi-glk-j4005:       PASS -> FAIL (fdo#100368)

    {igt@kms_psr@primary_page_flip}:
      {fi-icl-u}:         NOTRUN -> DMESG-FAIL (fdo#107335) +3

    igt@prime_vgem@basic-fence-flip:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#106097)

    
    ==== Possible fixes ====

    igt@debugfs_test@read_all_entries:
      fi-snb-2520m:       INCOMPLETE (fdo#103713) -> PASS

    igt@drv_selftest@live_hangcheck:
      fi-kbl-7567u:       DMESG-FAIL (fdo#106560, fdo#106947) -> PASS

    igt@kms_pipe_crc_basic@read-crc-pipe-b:
      fi-glk-j4005:       DMESG-WARN (fdo#106097) -> PASS

    
    ==== Warnings ====

    igt@drv_selftest@live_workarounds:
      fi-cnl-psr:         DMESG-WARN -> DMESG-FAIL (fdo#107292)

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#106825 https://bugs.freedesktop.org/show_bug.cgi?id=106825
  fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
  fdo#107175 https://bugs.freedesktop.org/show_bug.cgi?id=107175
  fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
  fdo#107335 https://bugs.freedesktop.org/show_bug.cgi?id=107335
  fdo#107338 https://bugs.freedesktop.org/show_bug.cgi?id=107338
  fdo#107339 https://bugs.freedesktop.org/show_bug.cgi?id=107339


== Participating hosts (51 -> 46) ==

  Additional (1): fi-icl-u 
  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


== Build changes ==

    * Linux: CI_DRM_4539 -> Patchwork_9763

  CI_DRM_4539: 764eb9fdd5683545c98da3e1c144824519306876 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4573: 2884f91dd6d7682ea738ef6f0943cc591643dda2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9763: 2dee984e585c8a64de502c1707e6d7e4665696fa @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

2dee984e585c HAX enable GuC for CI
88bd2dcfa626 drm/i915: Add a fault injection point to WOPCM init
5c482d93c554 drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context
44805d098351 drm/i915/guc: Move the pin bias value from GuC to GGTT
1bed23b4ccec drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9763/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v5 2/5] drm/i915/guc: Move the pin bias value from GuC to GGTT

[Michal Wajdeczko]

On Wed, 25 Jul 2018 12:56:53 +0200, Jakub Bartmiński  
<jakub.bartminski@intel.com> wrote:

> Removing the pin bias from GuC allows us to not check for GuC every time
> we pin a context, which fixes the assertion error on unresolved GuC
> platform default in mock contexts selftest.
>
> It also seems that we were using uninitialized WOPCM variables when
> setting the GuC pin bias. The pin bias has to be set after the WOPCM,
> but before the call to i915_gem_contexts_init where the first contexts
> are pinned.
>
> v2:
> This also makes it so that there's no need to set GuC variables from
> within the WOPCM init function or to move the WOPCM init, while keeping
> the correct initialization order. Also for mock tests the pin bias is
> left at 0 and we make sure that the pin bias with GuC will not be
> smaller than without GuC.
>
> v3:
> Avoid unused i915 in intel_guc_ggtt_offset if debug is disabled.
>
> v4:
> Squash with WOPCM init reordering.
> Moved the i915_ggtt_pin_bias helper to this patch, and made some
> functions use it instead of directly dereferencing i915->ggtt.
>
> v5:
> Since we now don't use wopcm.guc.base for the pin bias there's no need to
> validate it. It also has already been verified in WOPCM init.
>
> Fixes: f7dc0157e4b5 ("drm/i915/uc: Fetch GuC/HuC firmwares from guc/huc  
> specific init")
> Testcase: igt/drv_selftest/mock_contexts #GuC
> Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_context.c | 22 ++++++------------
>  drivers/gpu/drm/i915/i915_gem_gtt.c     | 18 ++++++++++----
>  drivers/gpu/drm/i915/i915_gem_gtt.h     |  2 ++
>  drivers/gpu/drm/i915/i915_vma.h         |  5 ++++
>  drivers/gpu/drm/i915/intel_guc.c        | 31 +++++--------------------
>  drivers/gpu/drm/i915/intel_guc.h        | 11 ++++-----
>  drivers/gpu/drm/i915/intel_huc.c        |  2 +-
>  drivers/gpu/drm/i915/intel_uc_fw.c      |  2 +-
>  drivers/gpu/drm/i915/intel_wopcm.h      | 16 +++++++++++++
>  9 files changed, 55 insertions(+), 54 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c  
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index b10770cfccd2..ae27caad1766 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -265,7 +265,7 @@ static u32 default_desc_template(const struct  
> drm_i915_private *i915,
>  }
> static struct i915_gem_context *
> -__create_hw_context(struct drm_i915_private *dev_priv,
> +__create_hw_context(struct drm_i915_private *i915,

please avoid s/dev_priv/i915 as it unnecessarily makes this patch
harder to review (actual changes vs renames ratio is unbalanced)

>  		    struct drm_i915_file_private *file_priv)
>  {
>  	struct i915_gem_context *ctx;
> @@ -276,15 +276,15 @@ __create_hw_context(struct drm_i915_private  
> *dev_priv,
>  	if (ctx == NULL)
>  		return ERR_PTR(-ENOMEM);
> -	ret = assign_hw_id(dev_priv, &ctx->hw_id);
> +	ret = assign_hw_id(i915, &ctx->hw_id);
>  	if (ret) {
>  		kfree(ctx);
>  		return ERR_PTR(ret);
>  	}
> 	kref_init(&ctx->ref);
> -	list_add_tail(&ctx->link, &dev_priv->contexts.list);
> -	ctx->i915 = dev_priv;
> +	list_add_tail(&ctx->link, &i915->contexts.list);
> +	ctx->i915 = i915;
>  	ctx->sched.priority = I915_PRIORITY_NORMAL;
> 	for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {
> @@ -322,22 +322,14 @@ __create_hw_context(struct drm_i915_private  
> *dev_priv,
>  	/* NB: Mark all slices as needing a remap so that when the context  
> first
>  	 * loads it will restore whatever remap state already exists. If there
>  	 * is no remap info, it will be a NOP. */
> -	ctx->remap_slice = ALL_L3_SLICES(dev_priv);
> +	ctx->remap_slice = ALL_L3_SLICES(i915);
> 	i915_gem_context_set_bannable(ctx);
>  	ctx->ring_size = 4 * PAGE_SIZE;
>  	ctx->desc_template =
> -		default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
> +		default_desc_template(i915, i915->mm.aliasing_ppgtt);
> -	/*
> -	 * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is  
> not
> -	 * present or not in use we still need a small bias as ring wraparound
> -	 * at offset 0 sometimes hangs. No idea why.
> -	 */
> -	if (USES_GUC(dev_priv))
> -		ctx->ggtt_offset_bias = dev_priv->guc.ggtt_pin_bias;
> -	else
> -		ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
> +	ctx->ggtt_offset_bias = i915->ggtt.pin_bias;
> 	return ctx;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c  
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d0acef299b9c..1f5d0334f0f5 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2901,7 +2901,7 @@ void i915_gem_fini_aliasing_ppgtt(struct  
> drm_i915_private *i915)
>  	ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
>  }
> -int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
> +int i915_gem_init_ggtt(struct drm_i915_private *i915)
>  {
>  	/* Let GEM Manage all of the aperture.
>  	 *
> @@ -2912,12 +2912,20 @@ int i915_gem_init_ggtt(struct drm_i915_private  
> *dev_priv)
>  	 * aperture.  One page should be enough to keep any prefetching inside
>  	 * of the aperture.
>  	 */
> -	struct i915_ggtt *ggtt = &dev_priv->ggtt;
> +	struct i915_ggtt *ggtt = &i915->ggtt;
>  	unsigned long hole_start, hole_end;
>  	struct drm_mm_node *entry;
>  	int ret;
> -	ret = intel_vgt_balloon(dev_priv);
> +	/*
> +	 * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is  
> not
> +	 * present or not in use we still need a small bias as ring wraparound
> +	 * at offset 0 sometimes hangs. No idea why.
> +	 */
> +	ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
> +			       intel_wopcm_guc_pin_bias(&i915->wopcm));
> +
> +	ret = intel_vgt_balloon(i915);
>  	if (ret)
>  		return ret;
> @@ -2940,8 +2948,8 @@ int i915_gem_init_ggtt(struct drm_i915_private  
> *dev_priv)
>  	/* And finally clear the reserved guard page */
>  	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
> -	if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
> -		ret = i915_gem_init_aliasing_ppgtt(dev_priv);
> +	if (USES_PPGTT(i915) && !USES_FULL_PPGTT(i915)) {
> +		ret = i915_gem_init_aliasing_ppgtt(i915);
>  		if (ret)
>  			goto err;
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h  
> b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index 14e62651010b..71e8cf24c800 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -396,6 +396,8 @@ struct i915_ggtt {
> 	int mtrr;
> +	u32 pin_bias;
> +
>  	struct drm_mm_node error_capture;
>  };
> diff --git a/drivers/gpu/drm/i915/i915_vma.h  
> b/drivers/gpu/drm/i915/i915_vma.h
> index f06d66377107..abf6144e3296 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -207,6 +207,11 @@ static inline u32 i915_ggtt_offset(const struct  
> i915_vma *vma)
>  	return lower_32_bits(vma->node.start);
>  }
> +static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
> +{
> +	return i915_vm_to_ggtt(vma->vm)->pin_bias;
> +}
> +
>  static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
>  {
>  	i915_gem_object_get(vma->obj);
> diff --git a/drivers/gpu/drm/i915/intel_guc.c  
> b/drivers/gpu/drm/i915/intel_guc.c
> index aa28368f8ba7..74043a13e9bc 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -27,8 +27,6 @@
>  #include "intel_guc_submission.h"
>  #include "i915_drv.h"
> -static void guc_init_ggtt_pin_bias(struct intel_guc *guc);
> -
>  static void gen8_guc_raise_irq(struct intel_guc *guc)
>  {
>  	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> @@ -142,8 +140,6 @@ int intel_guc_init_misc(struct intel_guc *guc)
>  	struct drm_i915_private *i915 = guc_to_i915(guc);
>  	int ret;
> -	guc_init_ggtt_pin_bias(guc);
> -
>  	ret = guc_init_wq(guc);
>  	if (ret)
>  		return ret;
> @@ -603,22 +599,6 @@ int intel_guc_resume(struct intel_guc *guc)
>   * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.
>   */
> -/**
> - * guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
> - * @guc: intel_guc structure.
> - *
> - * This function will calculate and initialize the ggtt_pin_bias value
> - * based on the GuC WOPCM size.
> - */
> -static void guc_init_ggtt_pin_bias(struct intel_guc *guc)
> -{
> -	struct drm_i915_private *i915 = guc_to_i915(guc);
> -
> -	GEM_BUG_ON(!i915->wopcm.size);
> -
> -	guc->ggtt_pin_bias = i915->wopcm.guc.size;
> -}
> -
>  /**
>   * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
>   * @guc:	the guc
> @@ -634,21 +614,22 @@ static void guc_init_ggtt_pin_bias(struct  
> intel_guc *guc)
>   */
>  struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
>  {
> -	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +	struct drm_i915_private *i915 = guc_to_i915(guc);
>  	struct drm_i915_gem_object *obj;
>  	struct i915_vma *vma;
> +	u64 flags;
>  	int ret;
> -	obj = i915_gem_object_create(dev_priv, size);
> +	obj = i915_gem_object_create(i915, size);
>  	if (IS_ERR(obj))
>  		return ERR_CAST(obj);
> -	vma = i915_vma_instance(obj, &dev_priv->ggtt.vm, NULL);
> +	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
>  	if (IS_ERR(vma))
>  		goto err;
> -	ret = i915_vma_pin(vma, 0, PAGE_SIZE,
> -			   PIN_GLOBAL | PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
> +	flags = PIN_GLOBAL | PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
> +	ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags);
>  	if (ret) {
>  		vma = ERR_PTR(ret);
>  		goto err;
> diff --git a/drivers/gpu/drm/i915/intel_guc.h  
> b/drivers/gpu/drm/i915/intel_guc.h
> index 4121928a495e..751f31c3c6c4 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -49,9 +49,6 @@ struct intel_guc {
>  	struct intel_guc_log log;
>  	struct intel_guc_ct ct;
> -	/* Offset where Non-WOPCM memory starts. */
> -	u32 ggtt_pin_bias;
> -
>  	/* Log snapshot if GuC errors during load */
>  	struct drm_i915_gem_object *load_err_log;
> @@ -130,10 +127,10 @@ static inline void  
> intel_guc_to_host_event_handler(struct intel_guc *guc)
>   * @vma: i915 graphics virtual memory area.
>   *
>   * GuC does not allow any gfx GGTT address that falls into range
> - * [0, GuC ggtt_pin_bias), which is reserved for Boot ROM, SRAM and  
> WOPCM.
> - * Currently, in order to exclude [0, GuC ggtt_pin_bias) address space  
> from
> + * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
> + * Currently, in order to exclude [0, ggtt.pin_bias) address space from
>   * GGTT, all gfx objects used by GuC are allocated with  
> intel_guc_allocate_vma()
> - * and pinned with PIN_OFFSET_BIAS along with the value of GuC  
> ggtt_pin_bias.
> + * and pinned with PIN_OFFSET_BIAS along with the value of  
> ggtt.pin_bias.
>   *
>   * Return: GGTT offset of the @vma.
>   */
> @@ -142,7 +139,7 @@ static inline u32 intel_guc_ggtt_offset(struct  
> intel_guc *guc,
>  {
>  	u32 offset = i915_ggtt_offset(vma);
> -	GEM_BUG_ON(offset < guc->ggtt_pin_bias);
> +	GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
>  	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
> 	return offset;
> diff --git a/drivers/gpu/drm/i915/intel_huc.c  
> b/drivers/gpu/drm/i915/intel_huc.c
> index ffcad5fad6a7..37ef540dd280 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -63,7 +63,7 @@ int intel_huc_auth(struct intel_huc *huc)
>  		return -ENOEXEC;
> 	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
> -				       PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
> +				       PIN_OFFSET_BIAS | i915->ggtt.pin_bias);
>  	if (IS_ERR(vma)) {
>  		ret = PTR_ERR(vma);
>  		DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c  
> b/drivers/gpu/drm/i915/intel_uc_fw.c
> index 6e8e0b546743..fd496416087c 100644
> --- a/drivers/gpu/drm/i915/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_uc_fw.c
> @@ -222,7 +222,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
>  		goto fail;
>  	}
> -	ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->guc.ggtt_pin_bias;
> +	ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->ggtt.pin_bias;
>  	vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
>  				       PIN_OFFSET_BIAS | ggtt_pin_bias);
>  	if (IS_ERR(vma)) {
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.h  
> b/drivers/gpu/drm/i915/intel_wopcm.h
> index 6298910a384c..0130165a9cdd 100644
> --- a/drivers/gpu/drm/i915/intel_wopcm.h
> +++ b/drivers/gpu/drm/i915/intel_wopcm.h
> @@ -7,6 +7,8 @@
>  #ifndef _INTEL_WOPCM_H_
>  #define _INTEL_WOPCM_H_
> +#include "i915_gem.h"

system headers shall be included first, so move new one down

> +#include "i915_utils.h"

do we really need this header here ?

>  #include <linux/types.h>
> /**
> @@ -24,6 +26,20 @@ struct intel_wopcm {
>  	} guc;
>  };
> +/**
> + * intel_wopcm_guc_pin_bias() - Get the GuC pin bias value.
> + * @wopcm: pointer to intel_wopcm.
> + *
> + * Returns:
> + * 0 if GuC is not present or not in use.
> + * Otherwise, the GuC pin bias value based on the GuC WOPCM size.
> + */
> +static inline u32 intel_wopcm_guc_pin_bias(struct intel_wopcm *wopcm)

hmm, I'm not sure that we should put GuC address space limitations/details
inside WOPCM code (which we wanted to be focused on partitioning only).

as this is used/needed only once in i915_gem_init_ggtt(), btw already with
some comment about wopcm, maybe you can inline this simply code there ?

or to be fully object oriented export this function from guc.c:

void intel_guc_get_ggtt_pin_bias(struct intel_guc *guc)
{
	return guc_to_i915(guc)->wopcm.guc.size;
}

> +{
> +	GEM_BUG_ON(!wopcm->size);
> +	return wopcm->guc.size;
> +}
> +
>  void intel_wopcm_init_early(struct intel_wopcm *wopcm);
>  int intel_wopcm_init(struct intel_wopcm *wopcm);
>  int intel_wopcm_init_hw(struct intel_wopcm *wopcm);
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v5 3/5] drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context

[Michal Wajdeczko]

On Wed, 25 Jul 2018 12:56:54 +0200, Jakub Bartmiński  
<jakub.bartminski@intel.com> wrote:

> Since ggtt_offset_bias is now stored in ggtt.pin_bias, it is duplicated
> inside i915_gem_context, and can instead be accessed directly from ggtt.

I'm tempted to merge this patch with previous one (without renames)

>
> v3:
> Added a helper function to retrieve the ggtt.pin_bias from the vma.
>
> v4:
> Moved the helper function to the previous patch in the series.
> Dropped the bias from intel_ring_pin. This introduces a slight functional
> change since we are always pinning a ring a bit higher if GuC is present
> even though we don't really need to.
>
> Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_context.c |  2 --
>  drivers/gpu/drm/i915/i915_gem_context.h |  3 ---
>  drivers/gpu/drm/i915/intel_lrc.c        |  6 ++----
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++++++--------
>  drivers/gpu/drm/i915/intel_ringbuffer.h |  4 +---
>  5 files changed, 9 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c  
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index ae27caad1766..6067563750de 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -329,8 +329,6 @@ __create_hw_context(struct drm_i915_private *i915,
>  	ctx->desc_template =
>  		default_desc_template(i915, i915->mm.aliasing_ppgtt);
> -	ctx->ggtt_offset_bias = i915->ggtt.pin_bias;
> -
>  	return ctx;
> err_pid:
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.h  
> b/drivers/gpu/drm/i915/i915_gem_context.h
> index b116e4942c10..851dad6decd7 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/i915_gem_context.h
> @@ -147,9 +147,6 @@ struct i915_gem_context {
> 	struct i915_sched_attr sched;
> -	/** ggtt_offset_bias: placement restriction for context objects */
> -	u32 ggtt_offset_bias;
> -
>  	/** engine: per-engine logical HW state */
>  	struct intel_context {
>  		struct i915_gem_context *gem_context;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c  
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 35d37af0cb9a..c923eb998c28 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1363,9 +1363,7 @@ static int __context_pin(struct i915_gem_context  
> *ctx, struct i915_vma *vma)
>  	}
> 	flags = PIN_GLOBAL | PIN_HIGH;
> -	if (ctx->ggtt_offset_bias)
> -		flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
> -
> +	flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);

This may unnecessarily turn on PIN_OFFSET_BIAS flag even if
i915_ggtt_pin_bias() returns 0. Maybe this would be safer:

	if (i915_ggtt_pin_bias(vma))
		flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);

>  	return i915_vma_pin(vma, 0, GEN8_LR_CONTEXT_ALIGN, flags);
>  }
> @@ -1392,7 +1390,7 @@ __execlists_context_pin(struct intel_engine_cs  
> *engine,
>  		goto unpin_vma;
>  	}
> -	ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias);
> +	ret = intel_ring_pin(ce->ring, ctx->i915);
>  	if (ret)
>  		goto unpin_map;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c  
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index f4bd185c9369..8a48325249a3 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1005,9 +1005,7 @@ i915_emit_bb_start(struct i915_request *rq,
> -int intel_ring_pin(struct intel_ring *ring,
> -		   struct drm_i915_private *i915,
> -		   unsigned int offset_bias)
> +int intel_ring_pin(struct intel_ring *ring, struct drm_i915_private  
> *i915)
>  {
>  	enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
>  	struct i915_vma *vma = ring->vma;
> @@ -1017,10 +1015,11 @@ int intel_ring_pin(struct intel_ring *ring,
> 	GEM_BUG_ON(ring->vaddr);
> -
>  	flags = PIN_GLOBAL;
> -	if (offset_bias)
> -		flags |= PIN_OFFSET_BIAS | offset_bias;
> +
> +	/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
> +	flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);

same here

> +
>  	if (vma->obj->stolen)
>  		flags |= PIN_MAPPABLE;
>  	else
> @@ -1404,8 +1403,7 @@ static int intel_init_ring_buffer(struct  
> intel_engine_cs *engine)
>  		goto err;
>  	}
> -	/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
> -	err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE);
> +	err = intel_ring_pin(ring, engine->i915);
>  	if (err)
>  		goto err_ring;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h  
> b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index d1eee08e5f6b..7fe07b2de2a7 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -784,9 +784,7 @@ struct intel_ring *
>  intel_engine_create_ring(struct intel_engine_cs *engine,
>  			 struct i915_timeline *timeline,
>  			 int size);
> -int intel_ring_pin(struct intel_ring *ring,
> -		   struct drm_i915_private *i915,
> -		   unsigned int offset_bias);
> +int intel_ring_pin(struct intel_ring *ring, struct drm_i915_private  
> *i915);
>  void intel_ring_reset(struct intel_ring *ring, u32 tail);
>  unsigned int intel_ring_update_space(struct intel_ring *ring);
>  void intel_ring_unpin(struct intel_ring *ring);
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v5 4/5] drm/i915: Add a fault injection point to WOPCM init

[Michal Wajdeczko]

On Wed, 25 Jul 2018 12:56:55 +0200, Jakub Bartmiński  
<jakub.bartminski@intel.com> wrote:

Missing commit message ... at minimum just repeat commit title

> v4:
> Move the injection inside the WOPCM init.
>
> Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_wopcm.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.c  
> b/drivers/gpu/drm/i915/intel_wopcm.c
> index 74bf76f3fddc..86c38b072926 100644
> --- a/drivers/gpu/drm/i915/intel_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> @@ -165,6 +165,9 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
> 	GEM_BUG_ON(!wopcm->size);
> +	if (i915_inject_load_failure())
> +		return -E2BIG;
> +
>  	if (guc_fw_size >= wopcm->size) {
>  		DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
>  			  guc_fw_size / 1024);
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for series starting with [v5,1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias
URL   : https://patchwork.freedesktop.org/series/47201/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4554 -> Patchwork_9783 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9783 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9783, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/47201/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9783:

  === IGT changes ===

    ==== Possible regressions ====

    igt@drv_selftest@live_gtt:
      fi-gdg-551:         PASS -> DMESG-WARN +14

    igt@drv_selftest@live_guc:
      fi-kbl-7567u:       PASS -> DMESG-WARN
      fi-skl-gvtdvm:      PASS -> DMESG-WARN
      fi-bxt-dsi:         PASS -> DMESG-WARN
      fi-whl-u:           PASS -> DMESG-WARN
      fi-kbl-7560u:       PASS -> DMESG-WARN
      fi-kbl-r:           PASS -> DMESG-WARN
      fi-kbl-x1275:       PASS -> DMESG-WARN
      fi-cfl-s3:          PASS -> DMESG-WARN
      {fi-cfl-8109u}:     PASS -> DMESG-WARN
      fi-kbl-7500u:       PASS -> DMESG-WARN
      fi-cfl-8700k:       PASS -> DMESG-WARN

    igt@drv_selftest@live_hangcheck:
      fi-bxt-dsi:         PASS -> DMESG-FAIL
      fi-bxt-j4205:       PASS -> DMESG-FAIL

    igt@drv_selftest@live_objects:
      fi-bwr-2160:        PASS -> DMESG-WARN +14

    igt@drv_selftest@live_requests:
      fi-elk-e7500:       PASS -> DMESG-WARN +14

    igt@drv_selftest@live_sanitycheck:
      fi-ilk-650:         PASS -> DMESG-WARN +14

    igt@drv_selftest@live_workarounds:
      fi-blb-e6850:       PASS -> DMESG-WARN +14

    
    ==== Warnings ====

    igt@drv_selftest@live_execlists:
      fi-bxt-j4205:       PASS -> SKIP +1

    
== Known issues ==

  Here are the changes found in Patchwork_9783 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_guc:
      fi-skl-6600u:       PASS -> DMESG-WARN (fdo#107175)
      {fi-skl-iommu}:     PASS -> DMESG-WARN (fdo#107175)
      fi-skl-6260u:       PASS -> DMESG-WARN (fdo#107175)
      fi-skl-6700k2:      PASS -> DMESG-WARN (fdo#107175)
      fi-skl-6770hq:      PASS -> DMESG-WARN (fdo#107175)
      fi-skl-6700hq:      PASS -> DMESG-WARN (fdo#107175)

    igt@drv_selftest@live_hangcheck:
      fi-kbl-7560u:       PASS -> DMESG-FAIL (fdo#106947)

    igt@drv_selftest@live_requests:
      {fi-skl-iommu}:     PASS -> DMESG-FAIL (fdo#107174)

    igt@gem_exec_suspend@basic:
      fi-snb-2520m:       PASS -> FAIL (fdo#106825)

    igt@kms_flip@basic-flip-vs-dpms:
      fi-skl-6700hq:      PASS -> DMESG-WARN (fdo#105998)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_coherency:
      {fi-icl-u}:         DMESG-FAIL -> PASS

    igt@kms_chamelium@dp-edid-read:
      fi-kbl-7500u:       FAIL (fdo#103841) -> PASS

    igt@kms_flip@basic-flip-vs-modeset:
      fi-skl-6700hq:      DMESG-WARN (fdo#105998) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       INCOMPLETE (fdo#103713) -> PASS

    {igt@kms_psr@primary_mmap_gtt}:
      fi-cnl-psr:         DMESG-WARN (fdo#107372) -> PASS

    
    ==== Warnings ====

    {igt@kms_psr@primary_page_flip}:
      fi-cnl-psr:         DMESG-FAIL (fdo#107372) -> DMESG-WARN (fdo#107372)

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#106825 https://bugs.freedesktop.org/show_bug.cgi?id=106825
  fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
  fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
  fdo#107175 https://bugs.freedesktop.org/show_bug.cgi?id=107175
  fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372


== Participating hosts (50 -> 43) ==

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


== Build changes ==

    * Linux: CI_DRM_4554 -> Patchwork_9783

  CI_DRM_4554: 5ce2e0fe88bd5a3615abb7289ab98d487201c450 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4576: bcb37a9b20eeec97f15fac2222408cc2e0b77631 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9783: 29c0813a029040416302b2b93691619118e0d8bf @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

29c0813a0290 HAX enable GuC for CI
3d176d2a8875 drm/i915: Add a fault injection point to WOPCM init
406193821e59 drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context
bf72168d77c4 drm/i915/guc: Move the pin bias value from GuC to GGTT
e75687604680 drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9783/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx