From: Mahesh Kumar <mahesh1.kumar@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: rodrigo.vivi@intel.com
Subject: [PATCH 5/5] drm/i915/skl+: don't trust IPC value set by BIOS
Date: Thu, 26 Jul 2018 19:44:10 +0530 [thread overview]
Message-ID: <20180726141410.2185-6-mahesh1.kumar@intel.com> (raw)
In-Reply-To: <20180726141410.2185-1-mahesh1.kumar@intel.com>
If KMS decide to disable IPC make sure we override IPC configuration set
by BIOS.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 39e400d5f555..77b34fe546a8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6097,10 +6097,8 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
u32 val;
/* Display WA #0477 WaDisableIPC: skl */
- if (IS_SKYLAKE(dev_priv) || !dev_priv->ipc_capable_mem) {
+ if (IS_SKYLAKE(dev_priv) || !dev_priv->ipc_capable_mem)
dev_priv->ipc_enabled = false;
- return;
- }
val = I915_READ(DISP_ARB_CTL2);
--
2.16.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2018-07-26 14:12 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-26 14:14 [PATCH 0/5] Decode memdev info and bandwidth and implemnt latency WA Mahesh Kumar
2018-07-26 14:14 ` [PATCH 1/5] drm/i915/bxt: Decode memory bandwidth and parameters Mahesh Kumar
2018-08-16 22:29 ` Rodrigo Vivi
2018-08-17 17:43 ` Rodrigo Vivi
2018-08-21 9:53 ` Kumar, Mahesh
2018-08-21 15:12 ` Rodrigo Vivi
2018-07-26 14:14 ` [PATCH 2/5] drm/i915/skl+: " Mahesh Kumar
2018-08-16 22:35 ` Rodrigo Vivi
2018-08-21 10:21 ` Kumar, Mahesh
2018-07-26 14:14 ` [PATCH 3/5] drm/i915: Implement 16GB dimm wa for latency level-0 Mahesh Kumar
2018-07-27 3:51 ` Matt Turner
2018-07-27 6:10 ` Kumar, Mahesh
2018-07-28 5:48 ` Rodrigo Vivi
2018-07-31 14:18 ` Kumar, Mahesh
2018-08-17 17:57 ` Rodrigo Vivi
2018-07-26 14:14 ` [PATCH 4/5] drm/i915/kbl+: Enable IPC only for symmetric memory configurations Mahesh Kumar
2018-08-17 18:20 ` Rodrigo Vivi
2018-08-21 14:57 ` Kumar, Mahesh
2018-08-21 16:00 ` Kumar, Mahesh
2018-08-21 18:56 ` Rodrigo Vivi
2018-08-22 13:02 ` Kumar, Mahesh
2018-08-22 15:39 ` Rodrigo Vivi
2018-07-26 14:14 ` Mahesh Kumar [this message]
2018-07-26 14:29 ` ✗ Fi.CI.SPARSE: warning for Decode memdev info and bandwidth and implemnt latency WA (rev2) Patchwork
2018-07-26 14:48 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-26 16:09 ` ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180726141410.2185-6-mahesh1.kumar@intel.com \
--to=mahesh1.kumar@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=rodrigo.vivi@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).