[PATCH v4 1/3] drm/i915: make PCH_GMBUS* definitions private to gvt

[PATCH v4 1/3] drm/i915: make PCH_GMBUS* definitions private to gvt

[Lucas De Marchi]

This is the only place that they are being used - the others use the
GMBUS* macros that rely on dev_priv being already properly initialized.

Cc: intel-gvt-dev@lists.freedesktop.org
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gvt/reg.h  | 7 +++++++
 drivers/gpu/drm/i915/i915_reg.h | 7 -------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index d4f7ce6dc1d7..fd5fd25d0a0f 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -77,4 +77,11 @@
 #define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
 		I915_GTT_PAGE_SIZE)
 
+#define PCH_GMBUS0	_MMIO(0xc5100)
+#define PCH_GMBUS1	_MMIO(0xc5104)
+#define PCH_GMBUS2	_MMIO(0xc5108)
+#define PCH_GMBUS3	_MMIO(0xc510c)
+#define PCH_GMBUS4	_MMIO(0xc5110)
+#define PCH_GMBUS5	_MMIO(0xc5120)
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5530c470f30d..07606677168c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7875,13 +7875,6 @@ enum {
 #define PCH_GPIOE               _MMIO(0xc5020)
 #define PCH_GPIOF               _MMIO(0xc5024)
 
-#define PCH_GMBUS0		_MMIO(0xc5100)
-#define PCH_GMBUS1		_MMIO(0xc5104)
-#define PCH_GMBUS2		_MMIO(0xc5108)
-#define PCH_GMBUS3		_MMIO(0xc510c)
-#define PCH_GMBUS4		_MMIO(0xc5110)
-#define PCH_GMBUS5		_MMIO(0xc5120)
-
 #define _PCH_DPLL_A              0xc6014
 #define _PCH_DPLL_B              0xc6018
 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
-- 
2.17.1

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[PATCH v4 2/3] drm/i915/gvt: use its own define for gpio

[Lucas De Marchi]

The definition on i915_reg.h is going to change to depend on
dev_priv->gpio_mmio_base being properly initialized. Define our own
macros since init_generic_mmio_info() is called before than
gpio_mmio_base being set.

Cc: intel-gvt-dev@lists.freedesktop.org
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
 drivers/gpu/drm/i915/gvt/reg.h      | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 7a58ca555197..0dc8692d7eb3 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2118,7 +2118,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
 
 	MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
 		gmbus_mmio_write);
-	MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
+	MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
 	MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
 
 	MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index fd5fd25d0a0f..c9d6cf6cc623 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -77,6 +77,8 @@
 #define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
 		I915_GTT_PAGE_SIZE)
 
+#define PCH_GPIO_BASE	_MMIO(0xc5010)
+
 #define PCH_GMBUS0	_MMIO(0xc5100)
 #define PCH_GMBUS1	_MMIO(0xc5104)
 #define PCH_GMBUS2	_MMIO(0xc5108)
-- 
2.17.1

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[PATCH v4 3/3] drm/i915: remove confusing GPIO vs PCH_GPIO

[Lucas De Marchi]

Instead of defining all registers twice, define just a PCH_GPIO_BASE
that has the same address as PCH_GPIO_A and use that to calculate all
the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
the same thing.

v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
    macro to return a particular gpio address and move the enum out of
    i915_reg.h (suggested by Jani)

v3: Move base offset inside the GPIO() macro so the GMBUS defines don't
    actually need to be changed (suggested by Daniel/Ville)

v4: Move definition of i915_gpio to intel_display.h and remove
    GMBUS/GPIO handling from gvt since now they have their own
    defines.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  3 ++-
 drivers/gpu/drm/i915/i915_reg.h      | 24 +++++-------------------
 drivers/gpu/drm/i915/intel_display.h | 16 ++++++++++++++++
 drivers/gpu/drm/i915/intel_i2c.c     | 16 ++++++++--------
 4 files changed, 31 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0f49f9988dfa..19ad2a52ab04 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1604,7 +1604,8 @@ struct drm_i915_private {
 	struct mutex gmbus_mutex;
 
 	/**
-	 * Base address of the gmbus and gpio block.
+	 * Base address of where the gmbus and gpio blocks are located (either
+	 * on PCH or on SoC for platforms without PCH).
 	 */
 	uint32_t gpio_mmio_base;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 07606677168c..827d442e1b12 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3168,18 +3168,9 @@ enum i915_power_well_id {
 /*
  * GPIO regs
  */
-#define GPIOA			_MMIO(0x5010)
-#define GPIOB			_MMIO(0x5014)
-#define GPIOC			_MMIO(0x5018)
-#define GPIOD			_MMIO(0x501c)
-#define GPIOE			_MMIO(0x5020)
-#define GPIOF			_MMIO(0x5024)
-#define GPIOG			_MMIO(0x5028)
-#define GPIOH			_MMIO(0x502c)
-#define GPIOJ			_MMIO(0x5034)
-#define GPIOK			_MMIO(0x5038)
-#define GPIOL			_MMIO(0x503C)
-#define GPIOM			_MMIO(0x5040)
+#define GPIO(gpio)		_MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
+				      4 * (gpio))
+
 # define GPIO_CLOCK_DIR_MASK		(1 << 0)
 # define GPIO_CLOCK_DIR_IN		(0 << 1)
 # define GPIO_CLOCK_DIR_OUT		(1 << 1)
@@ -7574,6 +7565,8 @@ enum {
 
 /* PCH */
 
+#define PCH_DISPLAY_BASE	0xc0000u
+
 /* south display engine interrupt: IBX */
 #define SDE_AUDIO_POWER_D	(1 << 27)
 #define SDE_AUDIO_POWER_C	(1 << 26)
@@ -7868,13 +7861,6 @@ enum {
 #define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
 #define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
 
-#define PCH_GPIOA               _MMIO(0xc5010)
-#define PCH_GPIOB               _MMIO(0xc5014)
-#define PCH_GPIOC               _MMIO(0xc5018)
-#define PCH_GPIOD               _MMIO(0xc501c)
-#define PCH_GPIOE               _MMIO(0xc5020)
-#define PCH_GPIOF               _MMIO(0xc5024)
-
 #define _PCH_DPLL_A              0xc6014
 #define _PCH_DPLL_B              0xc6018
 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 0a79a46d5805..e7f49f107e57 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -25,6 +25,22 @@
 #ifndef _INTEL_DISPLAY_H_
 #define _INTEL_DISPLAY_H_
 
+enum i915_gpio {
+	GPIOA,
+	GPIOB,
+	GPIOC,
+	GPIOD,
+	GPIOE,
+	GPIOF,
+	GPIOG,
+	GPIOH,
+	__GPIOI_UNUSED,
+	GPIOJ,
+	GPIOK,
+	GPIOL,
+	GPIOM,
+};
+
 enum pipe {
 	INVALID_PIPE = -1,
 
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index bef32b7c248e..33d87ab93fdd 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -37,7 +37,7 @@
 
 struct gmbus_pin {
 	const char *name;
-	i915_reg_t reg;
+	enum i915_gpio gpio;
 };
 
 /* Map gmbus pin pairs to names and registers. */
@@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 	else
 		size = ARRAY_SIZE(gmbus_pins);
 
-	return pin < size &&
-		i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
+	return pin < size && get_gmbus_pin(dev_priv, pin)->name;
 }
 
 /* Intel GPIO access functions */
@@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
 
 	algo = &bus->bit_algo;
 
-	bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
-			      i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
+	bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
 	bus->adapter.algo_data = algo;
 	algo->setsda = set_data;
 	algo->setscl = set_clock;
@@ -825,9 +823,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 	else if (!HAS_GMCH_DISPLAY(dev_priv))
-		dev_priv->gpio_mmio_base =
-			i915_mmio_reg_offset(PCH_GPIOA) -
-			i915_mmio_reg_offset(GPIOA);
+		/*
+		 * Broxton uses the same PCH offsets for South Display Engine,
+		 * even though it doesn't have a PCH.
+		 */
+		dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
 
 	mutex_init(&dev_priv->gmbus_mutex);
 	init_waitqueue_head(&dev_priv->gmbus_wait_queue);
-- 
2.17.1

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✗ Fi.CI.SPARSE: warning for series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions private to gvt

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions private to gvt
URL   : https://patchwork.freedesktop.org/series/47367/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: make PCH_GMBUS* definitions private to gvt
Okay!

Commit: drm/i915/gvt: use its own define for gpio
Okay!

Commit: drm/i915: remove confusing GPIO vs PCH_GPIO
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3645:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3646:16: warning: expression using sizeof(void)

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✗ Fi.CI.BAT: failure for series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions private to gvt

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions private to gvt
URL   : https://patchwork.freedesktop.org/series/47367/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4566 -> Patchwork_9796 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9796 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9796, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/47367/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9796:

  === IGT changes ===

    ==== Possible regressions ====

    igt@drv_selftest@live_coherency:
      fi-byt-n2820:       PASS -> DMESG-FAIL

    
== Known issues ==

  Here are the changes found in Patchwork_9796 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_hangcheck:
      fi-skl-6260u:       PASS -> DMESG-FAIL (fdo#106560, fdo#107174)

    igt@drv_selftest@live_workarounds:
      fi-bsw-n3050:       PASS -> DMESG-FAIL (fdo#107292)

    
    ==== Possible fixes ====

    igt@kms_chamelium@dp-edid-read:
      fi-kbl-7500u:       FAIL (fdo#103841) -> PASS

    
    ==== Warnings ====

    igt@drv_selftest@live_workarounds:
      fi-cnl-psr:         DMESG-WARN (fdo#105395) -> DMESG-FAIL (fdo#107292)

    {igt@kms_psr@primary_page_flip}:
      fi-cnl-psr:         DMESG-FAIL (fdo#107372) -> DMESG-WARN (fdo#107372)

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#105395 https://bugs.freedesktop.org/show_bug.cgi?id=105395
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
  fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
  fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372


== Participating hosts (52 -> 47) ==

  Additional (1): fi-hsw-peppy 
  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


== Build changes ==

    * Linux: CI_DRM_4566 -> Patchwork_9796

  CI_DRM_4566: 57e37535b29e6a90d36b0705968cdebff24c71ed @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4580: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9796: 07961b5a69f3d040b7355014733b174297081875 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

07961b5a69f3 drm/i915: remove confusing GPIO vs PCH_GPIO
764734ff666c drm/i915/gvt: use its own define for gpio
36405d2096b7 drm/i915: make PCH_GMBUS* definitions private to gvt

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9796/issues.html
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✗ Fi.CI.BAT: failure for series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions private to gvt

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions private to gvt
URL   : https://patchwork.freedesktop.org/series/47367/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4595 -> Patchwork_9815 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9815 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9815, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/47367/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9815:

  === IGT changes ===

    ==== Possible regressions ====

    igt@drv_selftest@live_objects:
      fi-bdw-5557u:       PASS -> INCOMPLETE

    
    ==== Warnings ====

    igt@drv_selftest@live_evict:
      fi-cnl-psr:         SKIP -> PASS +9

    
== Known issues ==

  Here are the changes found in Patchwork_9815 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_objects:
      fi-cnl-psr:         SKIP -> DMESG-FAIL (fdo#107398)

    
    ==== Possible fixes ====

    igt@debugfs_test@read_all_entries:
      fi-snb-2520m:       INCOMPLETE (fdo#103713) -> PASS

    igt@drv_selftest@live_coherency:
      {fi-icl-u}:         DMESG-FAIL -> PASS

    igt@drv_selftest@live_requests:
      {fi-bsw-kefka}:     INCOMPLETE (fdo#105876) -> PASS

    igt@drv_selftest@live_workarounds:
      {fi-cfl-8109u}:     DMESG-FAIL (fdo#107292) -> PASS
      {fi-bsw-kefka}:     DMESG-FAIL (fdo#107292) -> PASS

    igt@kms_chamelium@dp-edid-read:
      fi-kbl-7500u:       FAIL (fdo#103841) -> PASS

    
    ==== Warnings ====

    {igt@kms_psr@primary_page_flip}:
      fi-cnl-psr:         DMESG-FAIL (fdo#107372) -> DMESG-WARN (fdo#107372)

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#105876 https://bugs.freedesktop.org/show_bug.cgi?id=105876
  fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
  fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372
  fdo#107398 https://bugs.freedesktop.org/show_bug.cgi?id=107398


== Participating hosts (52 -> 47) ==

  Additional (1): fi-byt-j1900 
  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


== Build changes ==

    * Linux: CI_DRM_4595 -> Patchwork_9815

  CI_DRM_4595: f133adaa57cf7118381b5ffc081bba3bbb1dbc83 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9815: 19f3b0057acc280b8e4841a2261d69b36167e9f7 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

19f3b0057acc drm/i915: remove confusing GPIO vs PCH_GPIO
bdcb26307db7 drm/i915/gvt: use its own define for gpio
feb219c7e833 drm/i915: make PCH_GMBUS* definitions private to gvt

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9815/issues.html
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Re: [PATCH v4 1/3] drm/i915: make PCH_GMBUS* definitions private to gvt

[Zhenyu Wang]

[-- Attachment #1.1: Type: text/plain, Size: 2209 bytes --]

On 2018.07.27 12:36:45 -0700, Lucas De Marchi wrote:
> This is the only place that they are being used - the others use the
> GMBUS* macros that rely on dev_priv being already properly initialized.
>

Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>

thanks!

> Cc: intel-gvt-dev@lists.freedesktop.org
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/reg.h  | 7 +++++++
>  drivers/gpu/drm/i915/i915_reg.h | 7 -------
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> index d4f7ce6dc1d7..fd5fd25d0a0f 100644
> --- a/drivers/gpu/drm/i915/gvt/reg.h
> +++ b/drivers/gpu/drm/i915/gvt/reg.h
> @@ -77,4 +77,11 @@
>  #define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
>  		I915_GTT_PAGE_SIZE)
>  
> +#define PCH_GMBUS0	_MMIO(0xc5100)
> +#define PCH_GMBUS1	_MMIO(0xc5104)
> +#define PCH_GMBUS2	_MMIO(0xc5108)
> +#define PCH_GMBUS3	_MMIO(0xc510c)
> +#define PCH_GMBUS4	_MMIO(0xc5110)
> +#define PCH_GMBUS5	_MMIO(0xc5120)
> +
>  #endif
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5530c470f30d..07606677168c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7875,13 +7875,6 @@ enum {
>  #define PCH_GPIOE               _MMIO(0xc5020)
>  #define PCH_GPIOF               _MMIO(0xc5024)
>  
> -#define PCH_GMBUS0		_MMIO(0xc5100)
> -#define PCH_GMBUS1		_MMIO(0xc5104)
> -#define PCH_GMBUS2		_MMIO(0xc5108)
> -#define PCH_GMBUS3		_MMIO(0xc510c)
> -#define PCH_GMBUS4		_MMIO(0xc5110)
> -#define PCH_GMBUS5		_MMIO(0xc5120)
> -
>  #define _PCH_DPLL_A              0xc6014
>  #define _PCH_DPLL_B              0xc6018
>  #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
> -- 
> 2.17.1
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

-- 
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Re: [PATCH v4 2/3] drm/i915/gvt: use its own define for gpio

[Zhenyu Wang]

[-- Attachment #1.1: Type: text/plain, Size: 2120 bytes --]

On 2018.07.27 12:36:46 -0700, Lucas De Marchi wrote:
> The definition on i915_reg.h is going to change to depend on
> dev_priv->gpio_mmio_base being properly initialized. Define our own
> macros since init_generic_mmio_info() is called before than
> gpio_mmio_base being set.
>

Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>

> Cc: intel-gvt-dev@lists.freedesktop.org
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
>  drivers/gpu/drm/i915/gvt/reg.h      | 2 ++
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 7a58ca555197..0dc8692d7eb3 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2118,7 +2118,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>  
>  	MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>  		gmbus_mmio_write);
> -	MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> +	MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>  	MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>  
>  	MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> index fd5fd25d0a0f..c9d6cf6cc623 100644
> --- a/drivers/gpu/drm/i915/gvt/reg.h
> +++ b/drivers/gpu/drm/i915/gvt/reg.h
> @@ -77,6 +77,8 @@
>  #define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
>  		I915_GTT_PAGE_SIZE)
>  
> +#define PCH_GPIO_BASE	_MMIO(0xc5010)
> +
>  #define PCH_GMBUS0	_MMIO(0xc5100)
>  #define PCH_GMBUS1	_MMIO(0xc5104)
>  #define PCH_GMBUS2	_MMIO(0xc5108)
> -- 
> 2.17.1
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

-- 
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✓ Fi.CI.BAT: success for series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions private to gvt

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions private to gvt
URL   : https://patchwork.freedesktop.org/series/47367/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4599 -> Patchwork_9821 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/47367/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9821 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_workarounds:
      {fi-bsw-kefka}:     PASS -> DMESG-FAIL (fdo#107292)
      fi-whl-u:           PASS -> DMESG-FAIL (fdo#107292)

    igt@drv_selftest@mock_hugepages:
      fi-bwr-2160:        PASS -> DMESG-FAIL (fdo#107254)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-skl-6260u:       PASS -> INCOMPLETE (fdo#104108)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_workarounds:
      {fi-cfl-8109u}:     DMESG-FAIL (fdo#107292) -> PASS

    igt@kms_flip@basic-flip-vs-modeset:
      fi-skl-6700hq:      DMESG-WARN (fdo#105998) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       INCOMPLETE (fdo#103713) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#107254 https://bugs.freedesktop.org/show_bug.cgi?id=107254
  fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292


== Participating hosts (50 -> 45) ==

  Additional (1): fi-gdg-551 
  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-byt-squawks fi-ctg-p8600 fi-byt-clapper 


== Build changes ==

    * Linux: CI_DRM_4599 -> Patchwork_9821

  CI_DRM_4599: 64f0c5b2bf42d83cab790c4607d08d06a9e50e82 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9821: 3dfe5d390b1482b0326f6d9ee324206721c760e1 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3dfe5d390b14 drm/i915: remove confusing GPIO vs PCH_GPIO
25709fb172d6 drm/i915/gvt: use its own define for gpio
90b1a8ff8071 drm/i915: make PCH_GMBUS* definitions private to gvt

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9821/issues.html
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✓ Fi.CI.IGT: success for series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions private to gvt

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions private to gvt
URL   : https://patchwork.freedesktop.org/series/47367/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4599_full -> Patchwork_9821_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9821_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9821_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9821_full:

  === IGT changes ===

    ==== Warnings ====

    igt@kms_cursor_crc@cursor-128x128-onscreen:
      shard-snb:          SKIP -> PASS +2

    igt@kms_plane_lowres@pipe-a-tiling-none:
      shard-snb:          PASS -> SKIP +1

    
== Known issues ==

  Here are the changes found in Patchwork_9821_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_ctx_isolation@vcs0-s3:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665)

    igt@kms_flip@plain-flip-ts-check:
      shard-glk:          PASS -> FAIL (fdo#100368)

    igt@kms_flip@wf_vblank-ts-check-interruptible:
      shard-glk:          PASS -> FAIL (fdo#103928)

    igt@perf@blocking:
      shard-hsw:          PASS -> FAIL (fdo#102252)

    
    ==== Possible fixes ====

    igt@gem_ppgtt@blt-vs-render-ctxn:
      shard-kbl:          INCOMPLETE (fdo#103665, fdo#106023) -> PASS

    igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
      shard-hsw:          FAIL (fdo#105767) -> PASS

    igt@kms_flip@basic-flip-vs-wf_vblank:
      shard-glk:          FAIL (fdo#103928) -> PASS

    igt@kms_flip@flip-vs-expired-vblank:
      shard-kbl:          FAIL (fdo#105363, fdo#102887) -> PASS

    igt@pm_rps@min-max-config-loaded:
      shard-apl:          FAIL (fdo#102250) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4599 -> Patchwork_9821

  CI_DRM_4599: 64f0c5b2bf42d83cab790c4607d08d06a9e50e82 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9821: 3dfe5d390b1482b0326f6d9ee324206721c760e1 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9821/shards.html
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Re: [PATCH v4 3/3] drm/i915: remove confusing GPIO vs PCH_GPIO

[Lucas De Marchi]

On Fri, Jul 27, 2018 at 12:36:47PM -0700, Lucas De Marchi wrote:
> Instead of defining all registers twice, define just a PCH_GPIO_BASE
> that has the same address as PCH_GPIO_A and use that to calculate all
> the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> the same thing.
> 
> v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
>     macro to return a particular gpio address and move the enum out of
>     i915_reg.h (suggested by Jani)
> 
> v3: Move base offset inside the GPIO() macro so the GMBUS defines don't
>     actually need to be changed (suggested by Daniel/Ville)
> 
> v4: Move definition of i915_gpio to intel_display.h and remove
>     GMBUS/GPIO handling from gvt since now they have their own
>     defines.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---

Adding people that should have been in CC. Let me know if there's
anything missing.

Lucas De Marchi

>  drivers/gpu/drm/i915/i915_drv.h      |  3 ++-
>  drivers/gpu/drm/i915/i915_reg.h      | 24 +++++-------------------
>  drivers/gpu/drm/i915/intel_display.h | 16 ++++++++++++++++
>  drivers/gpu/drm/i915/intel_i2c.c     | 16 ++++++++--------
>  4 files changed, 31 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0f49f9988dfa..19ad2a52ab04 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1604,7 +1604,8 @@ struct drm_i915_private {
>  	struct mutex gmbus_mutex;
>  
>  	/**
> -	 * Base address of the gmbus and gpio block.
> +	 * Base address of where the gmbus and gpio blocks are located (either
> +	 * on PCH or on SoC for platforms without PCH).
>  	 */
>  	uint32_t gpio_mmio_base;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 07606677168c..827d442e1b12 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3168,18 +3168,9 @@ enum i915_power_well_id {
>  /*
>   * GPIO regs
>   */
> -#define GPIOA			_MMIO(0x5010)
> -#define GPIOB			_MMIO(0x5014)
> -#define GPIOC			_MMIO(0x5018)
> -#define GPIOD			_MMIO(0x501c)
> -#define GPIOE			_MMIO(0x5020)
> -#define GPIOF			_MMIO(0x5024)
> -#define GPIOG			_MMIO(0x5028)
> -#define GPIOH			_MMIO(0x502c)
> -#define GPIOJ			_MMIO(0x5034)
> -#define GPIOK			_MMIO(0x5038)
> -#define GPIOL			_MMIO(0x503C)
> -#define GPIOM			_MMIO(0x5040)
> +#define GPIO(gpio)		_MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
> +				      4 * (gpio))
> +
>  # define GPIO_CLOCK_DIR_MASK		(1 << 0)
>  # define GPIO_CLOCK_DIR_IN		(0 << 1)
>  # define GPIO_CLOCK_DIR_OUT		(1 << 1)
> @@ -7574,6 +7565,8 @@ enum {
>  
>  /* PCH */
>  
> +#define PCH_DISPLAY_BASE	0xc0000u
> +
>  /* south display engine interrupt: IBX */
>  #define SDE_AUDIO_POWER_D	(1 << 27)
>  #define SDE_AUDIO_POWER_C	(1 << 26)
> @@ -7868,13 +7861,6 @@ enum {
>  #define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
>  #define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
>  
> -#define PCH_GPIOA               _MMIO(0xc5010)
> -#define PCH_GPIOB               _MMIO(0xc5014)
> -#define PCH_GPIOC               _MMIO(0xc5018)
> -#define PCH_GPIOD               _MMIO(0xc501c)
> -#define PCH_GPIOE               _MMIO(0xc5020)
> -#define PCH_GPIOF               _MMIO(0xc5024)
> -
>  #define _PCH_DPLL_A              0xc6014
>  #define _PCH_DPLL_B              0xc6018
>  #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index 0a79a46d5805..e7f49f107e57 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -25,6 +25,22 @@
>  #ifndef _INTEL_DISPLAY_H_
>  #define _INTEL_DISPLAY_H_
>  
> +enum i915_gpio {
> +	GPIOA,
> +	GPIOB,
> +	GPIOC,
> +	GPIOD,
> +	GPIOE,
> +	GPIOF,
> +	GPIOG,
> +	GPIOH,
> +	__GPIOI_UNUSED,
> +	GPIOJ,
> +	GPIOK,
> +	GPIOL,
> +	GPIOM,
> +};
> +
>  enum pipe {
>  	INVALID_PIPE = -1,
>  
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index bef32b7c248e..33d87ab93fdd 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -37,7 +37,7 @@
>  
>  struct gmbus_pin {
>  	const char *name;
> -	i915_reg_t reg;
> +	enum i915_gpio gpio;
>  };
>  
>  /* Map gmbus pin pairs to names and registers. */
> @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
>  	else
>  		size = ARRAY_SIZE(gmbus_pins);
>  
> -	return pin < size &&
> -		i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
> +	return pin < size && get_gmbus_pin(dev_priv, pin)->name;
>  }
>  
>  /* Intel GPIO access functions */
> @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
>  
>  	algo = &bus->bit_algo;
>  
> -	bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
> -			      i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
> +	bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
>  	bus->adapter.algo_data = algo;
>  	algo->setsda = set_data;
>  	algo->setscl = set_clock;
> @@ -825,9 +823,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
>  	else if (!HAS_GMCH_DISPLAY(dev_priv))
> -		dev_priv->gpio_mmio_base =
> -			i915_mmio_reg_offset(PCH_GPIOA) -
> -			i915_mmio_reg_offset(GPIOA);
> +		/*
> +		 * Broxton uses the same PCH offsets for South Display Engine,
> +		 * even though it doesn't have a PCH.
> +		 */
> +		dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
>  
>  	mutex_init(&dev_priv->gmbus_mutex);
>  	init_waitqueue_head(&dev_priv->gmbus_wait_queue);
> -- 
> 2.17.1
> 
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Re: [PATCH v4 3/3] drm/i915: remove confusing GPIO vs PCH_GPIO

[Rodrigo Vivi]

On Fri, Jul 27, 2018 at 12:36:47PM -0700, Lucas De Marchi wrote:
> Instead of defining all registers twice, define just a PCH_GPIO_BASE
> that has the same address as PCH_GPIO_A and use that to calculate all
> the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> the same thing.
> 
> v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
>     macro to return a particular gpio address and move the enum out of
>     i915_reg.h (suggested by Jani)
> 
> v3: Move base offset inside the GPIO() macro so the GMBUS defines don't
>     actually need to be changed (suggested by Daniel/Ville)
> 
> v4: Move definition of i915_gpio to intel_display.h and remove
>     GMBUS/GPIO handling from gvt since now they have their own
>     defines.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  3 ++-
>  drivers/gpu/drm/i915/i915_reg.h      | 24 +++++-------------------
>  drivers/gpu/drm/i915/intel_display.h | 16 ++++++++++++++++
>  drivers/gpu/drm/i915/intel_i2c.c     | 16 ++++++++--------
>  4 files changed, 31 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0f49f9988dfa..19ad2a52ab04 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1604,7 +1604,8 @@ struct drm_i915_private {
>  	struct mutex gmbus_mutex;
>  
>  	/**
> -	 * Base address of the gmbus and gpio block.
> +	 * Base address of where the gmbus and gpio blocks are located (either
> +	 * on PCH or on SoC for platforms without PCH).
>  	 */
>  	uint32_t gpio_mmio_base;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 07606677168c..827d442e1b12 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3168,18 +3168,9 @@ enum i915_power_well_id {
>  /*
>   * GPIO regs
>   */
> -#define GPIOA			_MMIO(0x5010)
> -#define GPIOB			_MMIO(0x5014)
> -#define GPIOC			_MMIO(0x5018)
> -#define GPIOD			_MMIO(0x501c)
> -#define GPIOE			_MMIO(0x5020)
> -#define GPIOF			_MMIO(0x5024)
> -#define GPIOG			_MMIO(0x5028)
> -#define GPIOH			_MMIO(0x502c)
> -#define GPIOJ			_MMIO(0x5034)
> -#define GPIOK			_MMIO(0x5038)
> -#define GPIOL			_MMIO(0x503C)
> -#define GPIOM			_MMIO(0x5040)
> +#define GPIO(gpio)		_MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
> +				      4 * (gpio))
> +
>  # define GPIO_CLOCK_DIR_MASK		(1 << 0)
>  # define GPIO_CLOCK_DIR_IN		(0 << 1)
>  # define GPIO_CLOCK_DIR_OUT		(1 << 1)
> @@ -7574,6 +7565,8 @@ enum {
>  
>  /* PCH */
>  
> +#define PCH_DISPLAY_BASE	0xc0000u
> +
>  /* south display engine interrupt: IBX */
>  #define SDE_AUDIO_POWER_D	(1 << 27)
>  #define SDE_AUDIO_POWER_C	(1 << 26)
> @@ -7868,13 +7861,6 @@ enum {
>  #define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
>  #define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
>  
> -#define PCH_GPIOA               _MMIO(0xc5010)
> -#define PCH_GPIOB               _MMIO(0xc5014)
> -#define PCH_GPIOC               _MMIO(0xc5018)
> -#define PCH_GPIOD               _MMIO(0xc501c)
> -#define PCH_GPIOE               _MMIO(0xc5020)
> -#define PCH_GPIOF               _MMIO(0xc5024)
> -
>  #define _PCH_DPLL_A              0xc6014
>  #define _PCH_DPLL_B              0xc6018
>  #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index 0a79a46d5805..e7f49f107e57 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -25,6 +25,22 @@
>  #ifndef _INTEL_DISPLAY_H_
>  #define _INTEL_DISPLAY_H_
>  
> +enum i915_gpio {
> +	GPIOA,
> +	GPIOB,
> +	GPIOC,
> +	GPIOD,
> +	GPIOE,
> +	GPIOF,
> +	GPIOG,
> +	GPIOH,
> +	__GPIOI_UNUSED,
> +	GPIOJ,
> +	GPIOK,
> +	GPIOL,
> +	GPIOM,
> +};
> +
>  enum pipe {
>  	INVALID_PIPE = -1,
>  
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index bef32b7c248e..33d87ab93fdd 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -37,7 +37,7 @@
>  
>  struct gmbus_pin {
>  	const char *name;
> -	i915_reg_t reg;
> +	enum i915_gpio gpio;
>  };
>  
>  /* Map gmbus pin pairs to names and registers. */
> @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
>  	else
>  		size = ARRAY_SIZE(gmbus_pins);
>  
> -	return pin < size &&
> -		i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
> +	return pin < size && get_gmbus_pin(dev_priv, pin)->name;
>  }
>  
>  /* Intel GPIO access functions */
> @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
>  
>  	algo = &bus->bit_algo;
>  
> -	bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
> -			      i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
> +	bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
>  	bus->adapter.algo_data = algo;
>  	algo->setsda = set_data;
>  	algo->setscl = set_clock;
> @@ -825,9 +823,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
>  	else if (!HAS_GMCH_DISPLAY(dev_priv))
> -		dev_priv->gpio_mmio_base =
> -			i915_mmio_reg_offset(PCH_GPIOA) -
> -			i915_mmio_reg_offset(GPIOA);
> +		/*
> +		 * Broxton uses the same PCH offsets for South Display Engine,
> +		 * even though it doesn't have a PCH.
> +		 */
> +		dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
>  
>  	mutex_init(&dev_priv->gmbus_mutex);
>  	init_waitqueue_head(&dev_priv->gmbus_wait_queue);
> -- 
> 2.17.1
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v4 3/3] drm/i915: remove confusing GPIO vs PCH_GPIO

[Rodrigo Vivi]

On Thu, Aug 16, 2018 at 11:49:26AM -0700, Rodrigo Vivi wrote:
> On Fri, Jul 27, 2018 at 12:36:47PM -0700, Lucas De Marchi wrote:
> > Instead of defining all registers twice, define just a PCH_GPIO_BASE
> > that has the same address as PCH_GPIO_A and use that to calculate all
> > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> > the same thing.
> > 
> > v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
> >     macro to return a particular gpio address and move the enum out of
> >     i915_reg.h (suggested by Jani)
> > 
> > v3: Move base offset inside the GPIO() macro so the GMBUS defines don't
> >     actually need to be changed (suggested by Daniel/Ville)
> > 
> > v4: Move definition of i915_gpio to intel_display.h and remove
> >     GMBUS/GPIO handling from gvt since now they have their own
> >     defines.
> > 
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

and pushed

> 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      |  3 ++-
> >  drivers/gpu/drm/i915/i915_reg.h      | 24 +++++-------------------
> >  drivers/gpu/drm/i915/intel_display.h | 16 ++++++++++++++++
> >  drivers/gpu/drm/i915/intel_i2c.c     | 16 ++++++++--------
> >  4 files changed, 31 insertions(+), 28 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 0f49f9988dfa..19ad2a52ab04 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1604,7 +1604,8 @@ struct drm_i915_private {
> >  	struct mutex gmbus_mutex;
> >  
> >  	/**
> > -	 * Base address of the gmbus and gpio block.
> > +	 * Base address of where the gmbus and gpio blocks are located (either
> > +	 * on PCH or on SoC for platforms without PCH).
> >  	 */
> >  	uint32_t gpio_mmio_base;
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 07606677168c..827d442e1b12 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3168,18 +3168,9 @@ enum i915_power_well_id {
> >  /*
> >   * GPIO regs
> >   */
> > -#define GPIOA			_MMIO(0x5010)
> > -#define GPIOB			_MMIO(0x5014)
> > -#define GPIOC			_MMIO(0x5018)
> > -#define GPIOD			_MMIO(0x501c)
> > -#define GPIOE			_MMIO(0x5020)
> > -#define GPIOF			_MMIO(0x5024)
> > -#define GPIOG			_MMIO(0x5028)
> > -#define GPIOH			_MMIO(0x502c)
> > -#define GPIOJ			_MMIO(0x5034)
> > -#define GPIOK			_MMIO(0x5038)
> > -#define GPIOL			_MMIO(0x503C)
> > -#define GPIOM			_MMIO(0x5040)
> > +#define GPIO(gpio)		_MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
> > +				      4 * (gpio))
> > +
> >  # define GPIO_CLOCK_DIR_MASK		(1 << 0)
> >  # define GPIO_CLOCK_DIR_IN		(0 << 1)
> >  # define GPIO_CLOCK_DIR_OUT		(1 << 1)
> > @@ -7574,6 +7565,8 @@ enum {
> >  
> >  /* PCH */
> >  
> > +#define PCH_DISPLAY_BASE	0xc0000u
> > +
> >  /* south display engine interrupt: IBX */
> >  #define SDE_AUDIO_POWER_D	(1 << 27)
> >  #define SDE_AUDIO_POWER_C	(1 << 26)
> > @@ -7868,13 +7861,6 @@ enum {
> >  #define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
> >  #define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
> >  
> > -#define PCH_GPIOA               _MMIO(0xc5010)
> > -#define PCH_GPIOB               _MMIO(0xc5014)
> > -#define PCH_GPIOC               _MMIO(0xc5018)
> > -#define PCH_GPIOD               _MMIO(0xc501c)
> > -#define PCH_GPIOE               _MMIO(0xc5020)
> > -#define PCH_GPIOF               _MMIO(0xc5024)
> > -
> >  #define _PCH_DPLL_A              0xc6014
> >  #define _PCH_DPLL_B              0xc6018
> >  #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
> > diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> > index 0a79a46d5805..e7f49f107e57 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -25,6 +25,22 @@
> >  #ifndef _INTEL_DISPLAY_H_
> >  #define _INTEL_DISPLAY_H_
> >  
> > +enum i915_gpio {
> > +	GPIOA,
> > +	GPIOB,
> > +	GPIOC,
> > +	GPIOD,
> > +	GPIOE,
> > +	GPIOF,
> > +	GPIOG,
> > +	GPIOH,
> > +	__GPIOI_UNUSED,
> > +	GPIOJ,
> > +	GPIOK,
> > +	GPIOL,
> > +	GPIOM,
> > +};
> > +
> >  enum pipe {
> >  	INVALID_PIPE = -1,
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> > index bef32b7c248e..33d87ab93fdd 100644
> > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > @@ -37,7 +37,7 @@
> >  
> >  struct gmbus_pin {
> >  	const char *name;
> > -	i915_reg_t reg;
> > +	enum i915_gpio gpio;
> >  };
> >  
> >  /* Map gmbus pin pairs to names and registers. */
> > @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> >  	else
> >  		size = ARRAY_SIZE(gmbus_pins);
> >  
> > -	return pin < size &&
> > -		i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
> > +	return pin < size && get_gmbus_pin(dev_priv, pin)->name;
> >  }
> >  
> >  /* Intel GPIO access functions */
> > @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
> >  
> >  	algo = &bus->bit_algo;
> >  
> > -	bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
> > -			      i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
> > +	bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
> >  	bus->adapter.algo_data = algo;
> >  	algo->setsda = set_data;
> >  	algo->setscl = set_clock;
> > @@ -825,9 +823,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
> >  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> >  		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
> >  	else if (!HAS_GMCH_DISPLAY(dev_priv))
> > -		dev_priv->gpio_mmio_base =
> > -			i915_mmio_reg_offset(PCH_GPIOA) -
> > -			i915_mmio_reg_offset(GPIOA);
> > +		/*
> > +		 * Broxton uses the same PCH offsets for South Display Engine,
> > +		 * even though it doesn't have a PCH.
> > +		 */
> > +		dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
> >  
> >  	mutex_init(&dev_priv->gmbus_mutex);
> >  	init_waitqueue_head(&dev_priv->gmbus_wait_queue);
> > -- 
> > 2.17.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v4 2/3] drm/i915/gvt: use its own define for gpio

[Jani Nikula]

On Fri, 27 Jul 2018, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> The definition on i915_reg.h is going to change to depend on
> dev_priv->gpio_mmio_base being properly initialized. Define our own
> macros since init_generic_mmio_info() is called before than
> gpio_mmio_base being set.
>
> Cc: intel-gvt-dev@lists.freedesktop.org
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
>  drivers/gpu/drm/i915/gvt/reg.h      | 2 ++
>  2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 7a58ca555197..0dc8692d7eb3 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2118,7 +2118,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>  
>  	MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>  		gmbus_mmio_write);
> -	MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> +	MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);

Overall in i915 the preference is that register addresses are *not*
computed inline. Instead, define accessors in i915_reg.h. So maybe gvt
is different here, but just a note.

BR,
Jani.



>  	MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>  
>  	MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> index fd5fd25d0a0f..c9d6cf6cc623 100644
> --- a/drivers/gpu/drm/i915/gvt/reg.h
> +++ b/drivers/gpu/drm/i915/gvt/reg.h
> @@ -77,6 +77,8 @@
>  #define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
>  		I915_GTT_PAGE_SIZE)
>  
> +#define PCH_GPIO_BASE	_MMIO(0xc5010)
> +
>  #define PCH_GMBUS0	_MMIO(0xc5100)
>  #define PCH_GMBUS1	_MMIO(0xc5104)
>  #define PCH_GMBUS2	_MMIO(0xc5108)

-- 
Jani Nikula, Intel Open Source Graphics Center
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