* [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc
@ 2018-08-16 12:55 Juha-Pekka Heikkila
2018-08-16 12:55 ` [PATCH 2/4] drm/i915: Add P010, P012, P016 plane control definitions Juha-Pekka Heikkila
` (6 more replies)
0 siblings, 7 replies; 15+ messages in thread
From: Juha-Pekka Heikkila @ 2018-08-16 12:55 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add P010 definition, semi-planar yuv format where each component
is 16 bits 10 msb containing color value. First come Y plane [10:6]
followed by 2x2 subsampled Cr:Cb plane [10:6:10:6]
Add P012 definition, semi-planar yuv format where each component
is 16 bits 12 msb containing color value. First come Y plane [12:4]
followed by 2x2 subsampled Cr:Cb plane [12:4:12:4]
Add P016 definition, semi-planar yuv format where each component
is 16 bits. First come Y plane followed by 2x2 subsampled Cr:Cb
plane [16:16]
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 10 ++++++++++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 35c1e27..32e07a2 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
+ { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 721ab7e..cfb8873 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -142,6 +142,16 @@ extern "C" {
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
+ * 2 plane YCbCr
+ * index 0 = Y plane, [15:0] Y little endian where Pxxx indicate
+ * component xxx msb Y [xxx:16-xxx]
+ * index 1 = Cr:Cb plane, [31:0] Cr:Cb little endian [xxx:16-xxx:xxx:16-xxx]
+ */
+#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane, 10 bit per channel */
+#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane, 12 bit per channel */
+#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane, 16 bit per channel */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/4] drm/i915: Add P010, P012, P016 plane control definitions
2018-08-16 12:55 [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc Juha-Pekka Heikkila
@ 2018-08-16 12:55 ` Juha-Pekka Heikkila
2018-08-16 12:55 ` [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats Juha-Pekka Heikkila
` (5 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Juha-Pekka Heikkila @ 2018-08-16 12:55 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Juha-Pekka Heikkila
Add needed plane control flag definitions for P010, P012 and
P016 formats.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0c9f03d..06d4d90 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6506,8 +6506,11 @@ enum {
#define PLANE_CTL_FORMAT_YUV422 (0 << 24)
#define PLANE_CTL_FORMAT_NV12 (1 << 24)
#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
+#define PLANE_CTL_FORMAT_P010 (3 << 24)
#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
+#define PLANE_CTL_FORMAT_P012 (5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
+#define PLANE_CTL_FORMAT_P016 (7 << 24)
#define PLANE_CTL_FORMAT_AYUV (8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
--
2.7.4
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
2018-08-16 12:55 [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc Juha-Pekka Heikkila
2018-08-16 12:55 ` [PATCH 2/4] drm/i915: Add P010, P012, P016 plane control definitions Juha-Pekka Heikkila
@ 2018-08-16 12:55 ` Juha-Pekka Heikkila
2018-08-21 14:26 ` [Intel-gfx] " Sharma, Swati2
2018-08-27 11:28 ` Maarten Lankhorst
2018-08-16 12:55 ` [PATCH 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes Juha-Pekka Heikkila
` (4 subsequent siblings)
6 siblings, 2 replies; 15+ messages in thread
From: Juha-Pekka Heikkila @ 2018-08-16 12:55 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/intel_atomic.c | 3 +-
drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++++++++++----
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 19 ++++++-------
drivers/gpu/drm/i915/intel_sprite.c | 18 +++++++++++-
6 files changed, 69 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index b04952b..ab76b72 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
/* set scaler mode */
if ((INTEL_GEN(dev_priv) >= 9) &&
plane_state && plane_state->base.fb &&
- plane_state->base.fb->format->format ==
- DRM_FORMAT_NV12) {
+ is_planar_yuv_format(plane_state->base.fb->format->format)) {
if (INTEL_GEN(dev_priv) == 9 &&
!IS_GEMINILAKE(dev_priv) &&
!IS_SKYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index dcba645..58b2fc6 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
else
crtc_state->active_planes &= ~BIT(intel_plane->id);
- if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
+ if (state->visible && is_planar_yuv_format(state->fb->format->format))
crtc_state->nv12_planes |= BIT(intel_plane->id);
else
crtc_state->nv12_planes &= ~BIT(intel_plane->id);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 690e1e8..80ce742 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_P010:
+ return DRM_FORMAT_P010;
+ case PLANE_CTL_FORMAT_P012:
+ return DRM_FORMAT_P012;
+ case PLANE_CTL_FORMAT_P016:
+ return DRM_FORMAT_P016;
default:
case PLANE_CTL_FORMAT_XRGB_8888:
if (rgb_order) {
@@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
* Handle the AUX surface first since
* the main surface setup depends on it.
*/
- if (fb->format->format == DRM_FORMAT_NV12) {
+ if (is_planar_yuv_format(fb->format->format)) {
ret = skl_check_nv12_surface(crtc_state, plane_state);
if (ret)
return ret;
@@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+ case DRM_FORMAT_P010:
+ return PLANE_CTL_FORMAT_P010;
+ case DRM_FORMAT_P012:
+ return PLANE_CTL_FORMAT_P012;
+ case DRM_FORMAT_P016:
+ return PLANE_CTL_FORMAT_P016;
default:
MISSING_CASE(pixel_format);
}
@@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
need_scaling = src_w != dst_w || src_h != dst_h;
if (plane_scaler_check)
- if (pixel_format == DRM_FORMAT_NV12)
- need_scaling = true;
+ need_scaling = is_planar_yuv_format(pixel_format);
if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
@@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
return 0;
}
- if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
+ if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
(src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
DRM_DEBUG_KMS("NV12: src dimensions not met\n");
return -EINVAL;
@@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -13179,7 +13193,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
* or
* cdclk/crtc_clock
*/
- mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
+ mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
tmpclk1 = (1 << 16) * mult - 1;
tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
max_scale = min(tmpclk1, tmpclk2);
@@ -13411,6 +13425,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
/* fall through */
@@ -14556,6 +14573,23 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
break;
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
+ if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
+ mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
+ DRM_DEBUG_KMS("RC not to be enabled with %s\n",
+ drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
+ goto err;
+ }
+ if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
+ DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
+ goto err;
+ }
+ break;
default:
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format, &format_name));
@@ -14568,7 +14602,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
- if (fb->format->format == DRM_FORMAT_NV12 &&
+ if (is_planar_yuv_format(fb->format->format) &&
(fb->width < SKL_MIN_YUV_420_SRC_W ||
fb->height < SKL_MIN_YUV_420_SRC_H ||
(fb->width % 4) != 0 || (fb->height % 4) != 0)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7b984ae..20af577 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2097,6 +2097,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
/* intel_sprite.c */
+bool is_planar_yuv_format(uint32_t pixelformat);
int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
int usecs);
struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d99e5fa..e1292b2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3942,7 +3942,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) < 11)
val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
- if (fourcc == DRM_FORMAT_NV12) {
+ if (is_planar_yuv_format(fourcc)) {
skl_ddb_entry_init_from_hw(dev_priv,
&ddb->plane[pipe][plane_id], val2);
skl_ddb_entry_init_from_hw(dev_priv,
@@ -4150,7 +4150,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
if (intel_plane->id == PLANE_CURSOR)
return 0;
- if (plane == 1 && format != DRM_FORMAT_NV12)
+ if (plane == 1 && !is_planar_yuv_format(format))
return 0;
/*
@@ -4162,7 +4162,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
height = drm_rect_height(&intel_pstate->base.src) >> 16;
/* UV plane does 1/2 pixel sub-sampling */
- if (plane == 1 && format == DRM_FORMAT_NV12) {
+ if (plane == 1 && is_planar_yuv_format(format)) {
width /= 2;
height /= 2;
}
@@ -4229,7 +4229,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
return 0;
/* For packed formats, and uv-plane, return 0 */
- if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
+ if (plane == 1 && !is_planar_yuv_format(fb->format->format))
return 0;
/* For Non Y-tile return 8-blocks */
@@ -4247,7 +4247,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
- /* Halve UV plane width and height for NV12 */
+ /* Halve UV plane width and height for NV12 and other planar yuv */
if (plane == 1) {
src_w /= 2;
src_h /= 2;
@@ -4526,8 +4526,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
return 0;
/* only NV12 format has two planes */
- if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
- DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+ if (plane_id == 1 && !is_planar_yuv_format(fb->format->format)) {
+ DRM_DEBUG_KMS("Non planar format have single plane\n");
return -EINVAL;
}
@@ -4538,7 +4538,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
- wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
+ wp->is_planar = is_planar_yuv_format(fb->format->format);
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4813,8 +4813,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
return ret;
}
- if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
- wm->is_planar = true;
+ wm->is_planar = is_planar_yuv_format(intel_pstate->base.fb->format->format);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index f7026e8..68db026 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -41,6 +41,19 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+bool is_planar_yuv_format(uint32_t pixelformat)
+{
+ switch (pixelformat) {
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
+ return true;
+ default:
+ return false;
+ }
+}
+
int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
int usecs)
{
@@ -1039,7 +1052,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
src->y2 = (src_y + src_h) << 16;
if (fb->format->is_yuv &&
- fb->format->format != DRM_FORMAT_NV12 &&
+ !is_planar_yuv_format(fb->format->format) &&
(src_x % 2 || src_w % 2)) {
DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
src_x, src_w);
@@ -1419,6 +1432,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
/* fall through */
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes
2018-08-16 12:55 [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc Juha-Pekka Heikkila
2018-08-16 12:55 ` [PATCH 2/4] drm/i915: Add P010, P012, P016 plane control definitions Juha-Pekka Heikkila
2018-08-16 12:55 ` [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats Juha-Pekka Heikkila
@ 2018-08-16 12:55 ` Juha-Pekka Heikkila
2018-08-16 15:51 ` Maarten Lankhorst
2018-08-16 13:50 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc Patchwork
` (3 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Juha-Pekka Heikkila @ 2018-08-16 12:55 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Juha-Pekka Heikkila
Enabling of P010, P012 and P016 formats. These formats will
extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 24 +++++++++++++++++++++-
drivers/gpu/drm/i915/intel_sprite.c | 39 +++++++++++++++++++++++++++++++++++-
2 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 80ce742..5c7dc96 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -104,6 +104,25 @@ static const uint32_t skl_pri_planar_formats[] = {
DRM_FORMAT_NV12,
};
+static const uint32_t glk_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_P010,
+ DRM_FORMAT_P012,
+ DRM_FORMAT_P016,
+};
+
static const uint64_t skl_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -13721,7 +13740,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
PLANE_PRIMARY);
- if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
+ if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+ intel_primary_formats = glk_primary_formats;
+ num_formats = ARRAY_SIZE(glk_primary_formats);
+ } else if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
intel_primary_formats = skl_pri_planar_formats;
num_formats = ARRAY_SIZE(skl_pri_planar_formats);
} else {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 68db026..5cc97ba 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1292,6 +1292,22 @@ static uint32_t skl_planar_formats[] = {
DRM_FORMAT_NV12,
};
+static uint32_t glk_planar_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_P010,
+ DRM_FORMAT_P012,
+ DRM_FORMAT_P016,
+};
+
static const uint64_t skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -1537,7 +1553,28 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
}
intel_plane->base.state = &state->base;
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+ intel_plane->can_scale = true;
+ state->scaler_id = -1;
+
+ intel_plane->update_plane = skl_update_plane;
+ intel_plane->disable_plane = skl_disable_plane;
+ intel_plane->get_hw_state = skl_plane_get_hw_state;
+
+ if (skl_plane_has_planar(dev_priv, pipe,
+ PLANE_SPRITE0 + plane)) {
+ plane_formats = glk_planar_formats;
+ num_plane_formats = ARRAY_SIZE(glk_planar_formats);
+ } else {
+ plane_formats = skl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ }
+
+ if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
+ modifiers = skl_plane_format_modifiers_ccs;
+ else
+ modifiers = skl_plane_format_modifiers_noccs;
+ } else if (INTEL_GEN(dev_priv) >= 9) {
intel_plane->can_scale = true;
state->scaler_id = -1;
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc
2018-08-16 12:55 [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc Juha-Pekka Heikkila
` (2 preceding siblings ...)
2018-08-16 12:55 ` [PATCH 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes Juha-Pekka Heikkila
@ 2018-08-16 13:50 ` Patchwork
2018-08-16 13:53 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-08-16 13:50 UTC (permalink / raw)
To: Juha-Pekka Heikkila; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc
URL : https://patchwork.freedesktop.org/series/48316/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0cb3dff0a6d4 drm: Add P010, P012, P016 format definitions and fourcc
-:29: WARNING:LONG_LINE: line over 100 characters
#29: FILE: drivers/gpu/drm/drm_fourcc.c:176:
+ { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
-:30: WARNING:LONG_LINE: line over 100 characters
#30: FILE: drivers/gpu/drm/drm_fourcc.c:177:
+ { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
-:31: WARNING:LONG_LINE: line over 100 characters
#31: FILE: drivers/gpu/drm/drm_fourcc.c:178:
+ { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
-:49: WARNING:LONG_LINE_COMMENT: line over 100 characters
#49: FILE: include/uapi/drm/drm_fourcc.h:150:
+#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane, 10 bit per channel */
-:50: WARNING:LONG_LINE_COMMENT: line over 100 characters
#50: FILE: include/uapi/drm/drm_fourcc.h:151:
+#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane, 12 bit per channel */
-:51: WARNING:LONG_LINE_COMMENT: line over 100 characters
#51: FILE: include/uapi/drm/drm_fourcc.h:152:
+#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane, 16 bit per channel */
total: 0 errors, 6 warnings, 0 checks, 25 lines checked
7090dcc775cc drm/i915: Add P010, P012, P016 plane control definitions
0fa291bb82d1 drm/i915: preparations for enabling P010, P012, P016 formats
-:137: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#137: FILE: drivers/gpu/drm/i915/intel_display.c:14583:
+ drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
-:143: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#143: FILE: drivers/gpu/drm/i915/intel_display.c:14589:
+ drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
total: 0 errors, 0 warnings, 2 checks, 233 lines checked
0b2785973f16 drm/i915: enable P010, P012, P016 formats for primary and sprite planes
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc
2018-08-16 12:55 [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc Juha-Pekka Heikkila
` (3 preceding siblings ...)
2018-08-16 13:50 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc Patchwork
@ 2018-08-16 13:53 ` Patchwork
2018-08-16 14:07 ` ✓ Fi.CI.BAT: success " Patchwork
2018-08-16 17:17 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-08-16 13:53 UTC (permalink / raw)
To: Juha-Pekka Heikkila; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc
URL : https://patchwork.freedesktop.org/series/48316/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm: Add P010, P012, P016 format definitions and fourcc
Okay!
Commit: drm/i915: Add P010, P012, P016 plane control definitions
Okay!
Commit: drm/i915: preparations for enabling P010, P012, P016 formats
-O:drivers/gpu/drm/i915/intel_display.c:13185:21: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_display.c:13185:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_display.c:13199:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_display.c:13199:21: warning: expression using sizeof(void)
Commit: drm/i915: enable P010, P012, P016 formats for primary and sprite planes
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc
2018-08-16 12:55 [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc Juha-Pekka Heikkila
` (4 preceding siblings ...)
2018-08-16 13:53 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-08-16 14:07 ` Patchwork
2018-08-16 17:17 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-08-16 14:07 UTC (permalink / raw)
To: Juha-Pekka Heikkila; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc
URL : https://patchwork.freedesktop.org/series/48316/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4678 -> Patchwork_9963 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/48316/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9963:
=== IGT changes ===
==== Warnings ====
igt@drv_selftest@live_guc:
{fi-bdw-samus}: PASS -> SKIP +1
== Known issues ==
Here are the changes found in Patchwork_9963 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_hangcheck:
{fi-bdw-samus}: PASS -> DMESG-FAIL (fdo#106560)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
{fi-byt-clapper}: PASS -> FAIL (fdo#107362, fdo#103191)
==== Possible fixes ====
igt@drv_selftest@live_hangcheck:
fi-skl-guc: DMESG-FAIL (fdo#107174) -> PASS
fi-cfl-s3: DMESG-FAIL (fdo#106560) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b:
{fi-byt-clapper}: FAIL (fdo#107362) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS
==== Warnings ====
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-FAIL (fdo#107372) -> DMESG-WARN (fdo#107372)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372
== Participating hosts (54 -> 47) ==
Missing (7): fi-ilk-m540 fi-icl-u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u
== Build changes ==
* Linux: CI_DRM_4678 -> Patchwork_9963
CI_DRM_4678: 433fa6ccf8553afcc0159a996297b82bf50d1fac @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4603: 1598fdb717546e25e8077935daa8e97768ad245d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9963: 0b2785973f162407d58fb38784e80126cf2130bd @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0b2785973f16 drm/i915: enable P010, P012, P016 formats for primary and sprite planes
0fa291bb82d1 drm/i915: preparations for enabling P010, P012, P016 formats
7090dcc775cc drm/i915: Add P010, P012, P016 plane control definitions
0cb3dff0a6d4 drm: Add P010, P012, P016 format definitions and fourcc
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9963/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes
2018-08-16 12:55 ` [PATCH 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes Juha-Pekka Heikkila
@ 2018-08-16 15:51 ` Maarten Lankhorst
2018-08-24 9:23 ` Sharma, Swati2
0 siblings, 1 reply; 15+ messages in thread
From: Maarten Lankhorst @ 2018-08-16 15:51 UTC (permalink / raw)
To: Juha-Pekka Heikkila, intel-gfx; +Cc: dri-devel
Op 16-08-18 om 14:55 schreef Juha-Pekka Heikkila:
> Enabling of P010, P012 and P016 formats. These formats will
> extend NV12 for larger bit depths.
>
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 24 +++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_sprite.c | 39 +++++++++++++++++++++++++++++++++++-
> 2 files changed, 61 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 80ce742..5c7dc96 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -104,6 +104,25 @@ static const uint32_t skl_pri_planar_formats[] = {
> DRM_FORMAT_NV12,
> };
>
> +static const uint32_t glk_primary_formats[] = {
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_NV12,
> + DRM_FORMAT_P010,
> + DRM_FORMAT_P012,
> + DRM_FORMAT_P016,
> +};
> +
> static const uint64_t skl_format_modifiers_noccs[] = {
> I915_FORMAT_MOD_Yf_TILED,
> I915_FORMAT_MOD_Y_TILED,
> @@ -13721,7 +13740,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
> PLANE_PRIMARY);
>
> - if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
> + if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> + intel_primary_formats = glk_primary_formats;
> + num_formats = ARRAY_SIZE(glk_primary_formats);
> + } else if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
> intel_primary_formats = skl_pri_planar_formats;
> num_formats = ARRAY_SIZE(skl_pri_planar_formats);
> } else {
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 68db026..5cc97ba 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1292,6 +1292,22 @@ static uint32_t skl_planar_formats[] = {
> DRM_FORMAT_NV12,
> };
>
> +static uint32_t glk_planar_formats[] = {
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_NV12,
> + DRM_FORMAT_P010,
> + DRM_FORMAT_P012,
> + DRM_FORMAT_P016,
> +};
> +
> static const uint64_t skl_plane_format_modifiers_noccs[] = {
> I915_FORMAT_MOD_Yf_TILED,
> I915_FORMAT_MOD_Y_TILED,
> @@ -1537,7 +1553,28 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> }
> intel_plane->base.state = &state->base;
>
> - if (INTEL_GEN(dev_priv) >= 9) {
> + if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> + intel_plane->can_scale = true;
> + state->scaler_id = -1;
> +
> + intel_plane->update_plane = skl_update_plane;
> + intel_plane->disable_plane = skl_disable_plane;
> + intel_plane->get_hw_state = skl_plane_get_hw_state;
> +
> + if (skl_plane_has_planar(dev_priv, pipe,
> + PLANE_SPRITE0 + plane)) {
> + plane_formats = glk_planar_formats;
> + num_plane_formats = ARRAY_SIZE(glk_planar_formats);
> + } else {
> + plane_formats = skl_plane_formats;
> + num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> + }
> +
> + if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
> + modifiers = skl_plane_format_modifiers_ccs;
> + else
> + modifiers = skl_plane_format_modifiers_noccs;
> + } else if (INTEL_GEN(dev_priv) >= 9) {
> intel_plane->can_scale = true;
> state->scaler_id = -1;
>
Tested, still works ok against IGT. :)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc
2018-08-16 12:55 [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc Juha-Pekka Heikkila
` (5 preceding siblings ...)
2018-08-16 14:07 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-08-16 17:17 ` Patchwork
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-08-16 17:17 UTC (permalink / raw)
To: Juha-Pekka Heikkila; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc
URL : https://patchwork.freedesktop.org/series/48316/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4678_full -> Patchwork_9963_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9963_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9963_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9963_full:
=== IGT changes ===
==== Warnings ====
igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
shard-glk: PASS -> SKIP +1
== Known issues ==
Here are the changes found in Patchwork_9963_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_exec_await@wide-contexts:
shard-kbl: NOTRUN -> FAIL (fdo#105900)
igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
shard-glk: PASS -> FAIL (fdo#105454, fdo#106509)
==== Possible fixes ====
igt@kms_setmode@basic:
shard-kbl: FAIL (fdo#99912) -> PASS
fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900
fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4678 -> Patchwork_9963
CI_DRM_4678: 433fa6ccf8553afcc0159a996297b82bf50d1fac @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4603: 1598fdb717546e25e8077935daa8e97768ad245d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9963: 0b2785973f162407d58fb38784e80126cf2130bd @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9963/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
2018-08-16 12:55 ` [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats Juha-Pekka Heikkila
@ 2018-08-21 14:26 ` Sharma, Swati2
2018-08-27 10:21 ` Juha-Pekka Heikkila
2018-08-27 11:28 ` Maarten Lankhorst
1 sibling, 1 reply; 15+ messages in thread
From: Sharma, Swati2 @ 2018-08-21 14:26 UTC (permalink / raw)
To: Juha-Pekka Heikkila, intel-gfx; +Cc: dri-devel
On 16-Aug-18 6:25 PM, Juha-Pekka Heikkila wrote:
> Preparations for enabling P010, P012 and P016 formats. These
> formats will extend NV12 for larger bit depths.
>
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_atomic.c | 3 +-
> drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 19 ++++++-------
> drivers/gpu/drm/i915/intel_sprite.c | 18 +++++++++++-
> 6 files changed, 69 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index b04952b..ab76b72 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> /* set scaler mode */
> if ((INTEL_GEN(dev_priv) >= 9) &&
> plane_state && plane_state->base.fb &&
> - plane_state->base.fb->format->format ==
> - DRM_FORMAT_NV12) {
> + is_planar_yuv_format(plane_state->base.fb->format->format)) {
> if (INTEL_GEN(dev_priv) == 9 &&
> !IS_GEMINILAKE(dev_priv) &&
> !IS_SKYLAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index dcba645..58b2fc6 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> else
> crtc_state->active_planes &= ~BIT(intel_plane->id);
>
> - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
> + if (state->visible && is_planar_yuv_format(state->fb->format->format))
> crtc_state->nv12_planes |= BIT(intel_plane->id);
> else
> crtc_state->nv12_planes &= ~BIT(intel_plane->id);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 690e1e8..80ce742 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> return DRM_FORMAT_RGB565;
> case PLANE_CTL_FORMAT_NV12:
> return DRM_FORMAT_NV12;
> + case PLANE_CTL_FORMAT_P010:
> + return DRM_FORMAT_P010;
> + case PLANE_CTL_FORMAT_P012:
> + return DRM_FORMAT_P012;
> + case PLANE_CTL_FORMAT_P016:
> + return DRM_FORMAT_P016;
> default:
> case PLANE_CTL_FORMAT_XRGB_8888:
> if (rgb_order) {
> @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
> * Handle the AUX surface first since
> * the main surface setup depends on it.
> */
> - if (fb->format->format == DRM_FORMAT_NV12) {
> + if (is_planar_yuv_format(fb->format->format)) {
> ret = skl_check_nv12_surface(crtc_state, plane_state);
> if (ret)
> return ret;
> @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> case DRM_FORMAT_NV12:
> return PLANE_CTL_FORMAT_NV12;
> + case DRM_FORMAT_P010:
> + return PLANE_CTL_FORMAT_P010;
> + case DRM_FORMAT_P012:
> + return PLANE_CTL_FORMAT_P012;
> + case DRM_FORMAT_P016:
> + return PLANE_CTL_FORMAT_P016;
> default:
> MISSING_CASE(pixel_format);
> }
> @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> need_scaling = src_w != dst_w || src_h != dst_h;
>
> if (plane_scaler_check)
> - if (pixel_format == DRM_FORMAT_NV12)
> - need_scaling = true;
> + need_scaling = is_planar_yuv_format(pixel_format);
>
> if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
> need_scaling = true;
> @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> return 0;
> }
>
> - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
> + if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
> (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
> DRM_DEBUG_KMS("NV12: src dimensions not met\n");
> return -EINVAL;
> @@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> break;
> default:
> DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> @@ -13179,7 +13193,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
> * or
> * cdclk/crtc_clock
> */
> - mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
> + mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
> tmpclk1 = (1 << 16) * mult - 1;
> tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
> max_scale = min(tmpclk1, tmpclk2);
> @@ -13411,6 +13425,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> if (modifier == I915_FORMAT_MOD_Yf_TILED)
> return true;
> /* fall through */
> @@ -14556,6 +14573,23 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> goto err;
> }
> break;
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
Hi Juha,
Do we need this Y/Yf tiled ccs check here? Its already checked in the
beginning where its written RC supported only with RGB8888 formats.
> + if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
> + mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
> + DRM_DEBUG_KMS("RC not to be enabled with %s\n",
> + drm_get_format_name(mode_cmd->pixel_format,
> + &format_name));
> + goto err;
> + }
> + if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
> + DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> + drm_get_format_name(mode_cmd->pixel_format,
> + &format_name));
> + goto err;
> + }
> + break;
> default:
> DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> drm_get_format_name(mode_cmd->pixel_format, &format_name));
> @@ -14568,7 +14602,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>
> drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
>
> - if (fb->format->format == DRM_FORMAT_NV12 &&
> + if (is_planar_yuv_format(fb->format->format) &&
> (fb->width < SKL_MIN_YUV_420_SRC_W ||
> fb->height < SKL_MIN_YUV_420_SRC_H ||
> (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 7b984ae..20af577 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2097,6 +2097,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
>
>
> /* intel_sprite.c */
> +bool is_planar_yuv_format(uint32_t pixelformat);
> int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> int usecs);
> struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d99e5fa..e1292b2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3942,7 +3942,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
> if (INTEL_GEN(dev_priv) < 11)
> val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
>
> - if (fourcc == DRM_FORMAT_NV12) {
> + if (is_planar_yuv_format(fourcc)) {
> skl_ddb_entry_init_from_hw(dev_priv,
> &ddb->plane[pipe][plane_id], val2);
> skl_ddb_entry_init_from_hw(dev_priv,
> @@ -4150,7 +4150,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>
> if (intel_plane->id == PLANE_CURSOR)
> return 0;
> - if (plane == 1 && format != DRM_FORMAT_NV12)
> + if (plane == 1 && !is_planar_yuv_format(format))
> return 0;
>
> /*
> @@ -4162,7 +4162,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
> height = drm_rect_height(&intel_pstate->base.src) >> 16;
>
> /* UV plane does 1/2 pixel sub-sampling */
> - if (plane == 1 && format == DRM_FORMAT_NV12) {
> + if (plane == 1 && is_planar_yuv_format(format)) {
> width /= 2;
> height /= 2;
> }
> @@ -4229,7 +4229,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
> return 0;
>
> /* For packed formats, and uv-plane, return 0 */
> - if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
> + if (plane == 1 && !is_planar_yuv_format(fb->format->format))
> return 0;
>
> /* For Non Y-tile return 8-blocks */
> @@ -4247,7 +4247,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
> src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
> src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
>
> - /* Halve UV plane width and height for NV12 */
> + /* Halve UV plane width and height for NV12 and other planar yuv */
> if (plane == 1) {
> src_w /= 2;
> src_h /= 2;
> @@ -4526,8 +4526,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> return 0;
>
> /* only NV12 format has two planes */
> - if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
> - DRM_DEBUG_KMS("Non NV12 format have single plane\n");
> + if (plane_id == 1 && !is_planar_yuv_format(fb->format->format)) {
> + DRM_DEBUG_KMS("Non planar format have single plane\n");
> return -EINVAL;
> }
>
> @@ -4538,7 +4538,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
> wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> - wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
> + wp->is_planar = is_planar_yuv_format(fb->format->format);
>
> if (plane->id == PLANE_CURSOR) {
> wp->width = intel_pstate->base.crtc_w;
> @@ -4813,8 +4813,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
> return ret;
> }
>
> - if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
> - wm->is_planar = true;
> + wm->is_planar = is_planar_yuv_format(intel_pstate->base.fb->format->format);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index f7026e8..68db026 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -41,6 +41,19 @@
> #include <drm/i915_drm.h>
> #include "i915_drv.h"
>
> +bool is_planar_yuv_format(uint32_t pixelformat)
> +{
> + switch (pixelformat) {
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> int usecs)
> {
> @@ -1039,7 +1052,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
> src->y2 = (src_y + src_h) << 16;
>
> if (fb->format->is_yuv &&
> - fb->format->format != DRM_FORMAT_NV12 &&
> + !is_planar_yuv_format(fb->format->format) &&
> (src_x % 2 || src_w % 2)) {
> DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
> src_x, src_w);
> @@ -1419,6 +1432,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> if (modifier == I915_FORMAT_MOD_Yf_TILED)
> return true;
> /* fall through */
--
Thanks and Regards,
Swati
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes
2018-08-16 15:51 ` Maarten Lankhorst
@ 2018-08-24 9:23 ` Sharma, Swati2
0 siblings, 0 replies; 15+ messages in thread
From: Sharma, Swati2 @ 2018-08-24 9:23 UTC (permalink / raw)
To: Maarten Lankhorst, Juha-Pekka Heikkila, intel-gfx; +Cc: dri-devel
On 16-Aug-18 9:21 PM, Maarten Lankhorst wrote:
> Op 16-08-18 om 14:55 schreef Juha-Pekka Heikkila:
>> Enabling of P010, P012 and P016 formats. These formats will
>> extend NV12 for larger bit depths.
>>
>> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
>> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_display.c | 24 +++++++++++++++++++++-
>> drivers/gpu/drm/i915/intel_sprite.c | 39 +++++++++++++++++++++++++++++++++++-
>> 2 files changed, 61 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 80ce742..5c7dc96 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -104,6 +104,25 @@ static const uint32_t skl_pri_planar_formats[] = {
>> DRM_FORMAT_NV12,
>> };
>>
Hi Juha,
Shouldn't we add planar prefix with glk_primary_formats i.e.
glk_pri_planar_formats to make it more clear?
>> +static const uint32_t glk_primary_formats[] = {
>> + DRM_FORMAT_C8,
>> + DRM_FORMAT_RGB565,
>> + DRM_FORMAT_XRGB8888,
>> + DRM_FORMAT_XBGR8888,
>> + DRM_FORMAT_ARGB8888,
>> + DRM_FORMAT_ABGR8888,
>> + DRM_FORMAT_XRGB2101010,
>> + DRM_FORMAT_XBGR2101010,
>> + DRM_FORMAT_YUYV,
>> + DRM_FORMAT_YVYU,
>> + DRM_FORMAT_UYVY,
>> + DRM_FORMAT_VYUY,
>> + DRM_FORMAT_NV12,
>> + DRM_FORMAT_P010,
>> + DRM_FORMAT_P012,
>> + DRM_FORMAT_P016,
>> +};
>> +
>> static const uint64_t skl_format_modifiers_noccs[] = {
>> I915_FORMAT_MOD_Yf_TILED,
>> I915_FORMAT_MOD_Y_TILED,
>> @@ -13721,7 +13740,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>> primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
>> PLANE_PRIMARY);
>>
>> - if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
>> + if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>> + intel_primary_formats = glk_primary_formats;
>> + num_formats = ARRAY_SIZE(glk_primary_formats);
>> + } else if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
>> intel_primary_formats = skl_pri_planar_formats;
>> num_formats = ARRAY_SIZE(skl_pri_planar_formats);
>> } else {
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
>> index 68db026..5cc97ba 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -1292,6 +1292,22 @@ static uint32_t skl_planar_formats[] = {
>> DRM_FORMAT_NV12,
>> };
>>
>> +static uint32_t glk_planar_formats[] = {
>> + DRM_FORMAT_RGB565,
>> + DRM_FORMAT_ABGR8888,
>> + DRM_FORMAT_ARGB8888,
>> + DRM_FORMAT_XBGR8888,
>> + DRM_FORMAT_XRGB8888,
>> + DRM_FORMAT_YUYV,
>> + DRM_FORMAT_YVYU,
>> + DRM_FORMAT_UYVY,
>> + DRM_FORMAT_VYUY,
>> + DRM_FORMAT_NV12,
>> + DRM_FORMAT_P010,
>> + DRM_FORMAT_P012,
>> + DRM_FORMAT_P016,
>> +};
>> +
>> static const uint64_t skl_plane_format_modifiers_noccs[] = {
>> I915_FORMAT_MOD_Yf_TILED,
>> I915_FORMAT_MOD_Y_TILED,
>> @@ -1537,7 +1553,28 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>> }
>> intel_plane->base.state = &state->base;
>>
>> - if (INTEL_GEN(dev_priv) >= 9) {
>> + if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>> + intel_plane->can_scale = true;
>> + state->scaler_id = -1;
>> +
>> + intel_plane->update_plane = skl_update_plane;
>> + intel_plane->disable_plane = skl_disable_plane;
>> + intel_plane->get_hw_state = skl_plane_get_hw_state;
>> +
>> + if (skl_plane_has_planar(dev_priv, pipe,
>> + PLANE_SPRITE0 + plane)) {
>> + plane_formats = glk_planar_formats;
>> + num_plane_formats = ARRAY_SIZE(glk_planar_formats);
>> + } else {
>> + plane_formats = skl_plane_formats;
>> + num_plane_formats = ARRAY_SIZE(skl_plane_formats);
>> + }
>> +
>> + if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
>> + modifiers = skl_plane_format_modifiers_ccs;
>> + else
>> + modifiers = skl_plane_format_modifiers_noccs;
>> + } else if (INTEL_GEN(dev_priv) >= 9) {
>> intel_plane->can_scale = true;
>> state->scaler_id = -1;
>>
> Tested, still works ok against IGT. :)
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Thanks and Regards,
Swati
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
2018-08-21 14:26 ` [Intel-gfx] " Sharma, Swati2
@ 2018-08-27 10:21 ` Juha-Pekka Heikkila
0 siblings, 0 replies; 15+ messages in thread
From: Juha-Pekka Heikkila @ 2018-08-27 10:21 UTC (permalink / raw)
To: Sharma, Swati2, intel-gfx; +Cc: dri-devel
On 21.08.2018 17:26, Sharma, Swati2 wrote:
> On 16-Aug-18 6:25 PM, Juha-Pekka Heikkila wrote:
>> Preparations for enabling P010, P012 and P016 formats. These
>> formats will extend NV12 for larger bit depths.
>>
>> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
>> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_atomic.c | 3 +-
>> drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
>> drivers/gpu/drm/i915/intel_display.c | 46
>> +++++++++++++++++++++++++++----
>> drivers/gpu/drm/i915/intel_drv.h | 1 +
>> drivers/gpu/drm/i915/intel_pm.c | 19 ++++++-------
>> drivers/gpu/drm/i915/intel_sprite.c | 18 +++++++++++-
>> 6 files changed, 69 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_atomic.c
>> b/drivers/gpu/drm/i915/intel_atomic.c
>> index b04952b..ab76b72 100644
>> --- a/drivers/gpu/drm/i915/intel_atomic.c
>> +++ b/drivers/gpu/drm/i915/intel_atomic.c
>> @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct
>> drm_i915_private *dev_priv,
>> /* set scaler mode */
>> if ((INTEL_GEN(dev_priv) >= 9) &&
>> plane_state && plane_state->base.fb &&
>> - plane_state->base.fb->format->format ==
>> - DRM_FORMAT_NV12) {
>> +
>> is_planar_yuv_format(plane_state->base.fb->format->format)) {
>> if (INTEL_GEN(dev_priv) == 9 &&
>> !IS_GEMINILAKE(dev_priv) &&
>> !IS_SKYLAKE(dev_priv))
>> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
>> b/drivers/gpu/drm/i915/intel_atomic_plane.c
>> index dcba645..58b2fc6 100644
>> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
>> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
>> @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const
>> struct intel_crtc_state *old_crtc_
>> else
>> crtc_state->active_planes &= ~BIT(intel_plane->id);
>> - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
>> + if (state->visible &&
>> is_planar_yuv_format(state->fb->format->format))
>> crtc_state->nv12_planes |= BIT(intel_plane->id);
>> else
>> crtc_state->nv12_planes &= ~BIT(intel_plane->id);
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 690e1e8..80ce742 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool
>> rgb_order, bool alpha)
>> return DRM_FORMAT_RGB565;
>> case PLANE_CTL_FORMAT_NV12:
>> return DRM_FORMAT_NV12;
>> + case PLANE_CTL_FORMAT_P010:
>> + return DRM_FORMAT_P010;
>> + case PLANE_CTL_FORMAT_P012:
>> + return DRM_FORMAT_P012;
>> + case PLANE_CTL_FORMAT_P016:
>> + return DRM_FORMAT_P016;
>> default:
>> case PLANE_CTL_FORMAT_XRGB_8888:
>> if (rgb_order) {
>> @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct
>> intel_crtc_state *crtc_state,
>> * Handle the AUX surface first since
>> * the main surface setup depends on it.
>> */
>> - if (fb->format->format == DRM_FORMAT_NV12) {
>> + if (is_planar_yuv_format(fb->format->format)) {
>> ret = skl_check_nv12_surface(crtc_state, plane_state);
>> if (ret)
>> return ret;
>> @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t
>> pixel_format)
>> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
>> case DRM_FORMAT_NV12:
>> return PLANE_CTL_FORMAT_NV12;
>> + case DRM_FORMAT_P010:
>> + return PLANE_CTL_FORMAT_P010;
>> + case DRM_FORMAT_P012:
>> + return PLANE_CTL_FORMAT_P012;
>> + case DRM_FORMAT_P016:
>> + return PLANE_CTL_FORMAT_P016;
>> default:
>> MISSING_CASE(pixel_format);
>> }
>> @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state
>> *crtc_state, bool force_detach,
>> need_scaling = src_w != dst_w || src_h != dst_h;
>> if (plane_scaler_check)
>> - if (pixel_format == DRM_FORMAT_NV12)
>> - need_scaling = true;
>> + need_scaling = is_planar_yuv_format(pixel_format);
>> if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
>> need_scaling = true;
>> @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state
>> *crtc_state, bool force_detach,
>> return 0;
>> }
>> - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
>> + if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
>> (src_h < SKL_MIN_YUV_420_SRC_H || src_w <
>> SKL_MIN_YUV_420_SRC_W)) {
>> DRM_DEBUG_KMS("NV12: src dimensions not met\n");
>> return -EINVAL;
>> @@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct
>> intel_crtc_state *crtc_state,
>> case DRM_FORMAT_UYVY:
>> case DRM_FORMAT_VYUY:
>> case DRM_FORMAT_NV12:
>> + case DRM_FORMAT_P010:
>> + case DRM_FORMAT_P012:
>> + case DRM_FORMAT_P016:
>> break;
>> default:
>> DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling
>> format 0x%x\n",
>> @@ -13179,7 +13193,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
>> * or
>> * cdclk/crtc_clock
>> */
>> - mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
>> + mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
>> tmpclk1 = (1 << 16) * mult - 1;
>> tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
>> max_scale = min(tmpclk1, tmpclk2);
>> @@ -13411,6 +13425,9 @@ static bool
>> skl_plane_format_mod_supported(struct drm_plane *_plane,
>> case DRM_FORMAT_UYVY:
>> case DRM_FORMAT_VYUY:
>> case DRM_FORMAT_NV12:
>> + case DRM_FORMAT_P010:
>> + case DRM_FORMAT_P012:
>> + case DRM_FORMAT_P016:
>> if (modifier == I915_FORMAT_MOD_Yf_TILED)
>> return true;
>> /* fall through */
>> @@ -14556,6 +14573,23 @@ static int intel_framebuffer_init(struct
>> intel_framebuffer *intel_fb,
>> goto err;
>> }
>> break;
>> + case DRM_FORMAT_P010:
>> + case DRM_FORMAT_P012:
>> + case DRM_FORMAT_P016:
> Hi Juha,
> Do we need this Y/Yf tiled ccs check here? Its already checked in the
> beginning where its written RC supported only with RGB8888 formats.
You're right. I think underlying code has changed in past months since
this was written. I'll make another version.
>> + if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
>> + mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
>> + DRM_DEBUG_KMS("RC not to be enabled with %s\n",
>> + drm_get_format_name(mode_cmd->pixel_format,
>> + &format_name));
>> + goto err;
>> + }
>> + if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
>> + DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>> + drm_get_format_name(mode_cmd->pixel_format,
>> + &format_name));
>> + goto err;
>> + }
>> + break;
>> default:
>> DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>> drm_get_format_name(mode_cmd->pixel_format,
>> &format_name));
>> @@ -14568,7 +14602,7 @@ static int intel_framebuffer_init(struct
>> intel_framebuffer *intel_fb,
>> drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
>> - if (fb->format->format == DRM_FORMAT_NV12 &&
>> + if (is_planar_yuv_format(fb->format->format) &&
>> (fb->width < SKL_MIN_YUV_420_SRC_W ||
>> fb->height < SKL_MIN_YUV_420_SRC_H ||
>> (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index 7b984ae..20af577 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -2097,6 +2097,7 @@ bool intel_sdvo_init(struct drm_i915_private
>> *dev_priv,
>> /* intel_sprite.c */
>> +bool is_planar_yuv_format(uint32_t pixelformat);
>> int intel_usecs_to_scanlines(const struct drm_display_mode
>> *adjusted_mode,
>> int usecs);
>> struct intel_plane *intel_sprite_plane_create(struct
>> drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index d99e5fa..e1292b2 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -3942,7 +3942,7 @@ skl_ddb_get_hw_plane_state(struct
>> drm_i915_private *dev_priv,
>> if (INTEL_GEN(dev_priv) < 11)
>> val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
>> - if (fourcc == DRM_FORMAT_NV12) {
>> + if (is_planar_yuv_format(fourcc)) {
>> skl_ddb_entry_init_from_hw(dev_priv,
>> &ddb->plane[pipe][plane_id], val2);
>> skl_ddb_entry_init_from_hw(dev_priv,
>> @@ -4150,7 +4150,7 @@ skl_plane_relative_data_rate(const struct
>> intel_crtc_state *cstate,
>> if (intel_plane->id == PLANE_CURSOR)
>> return 0;
>> - if (plane == 1 && format != DRM_FORMAT_NV12)
>> + if (plane == 1 && !is_planar_yuv_format(format))
>> return 0;
>> /*
>> @@ -4162,7 +4162,7 @@ skl_plane_relative_data_rate(const struct
>> intel_crtc_state *cstate,
>> height = drm_rect_height(&intel_pstate->base.src) >> 16;
>> /* UV plane does 1/2 pixel sub-sampling */
>> - if (plane == 1 && format == DRM_FORMAT_NV12) {
>> + if (plane == 1 && is_planar_yuv_format(format)) {
>> width /= 2;
>> height /= 2;
>> }
>> @@ -4229,7 +4229,7 @@ skl_ddb_min_alloc(const struct drm_plane_state
>> *pstate, const int plane)
>> return 0;
>> /* For packed formats, and uv-plane, return 0 */
>> - if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
>> + if (plane == 1 && !is_planar_yuv_format(fb->format->format))
>> return 0;
>> /* For Non Y-tile return 8-blocks */
>> @@ -4247,7 +4247,7 @@ skl_ddb_min_alloc(const struct drm_plane_state
>> *pstate, const int plane)
>> src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
>> src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
>> - /* Halve UV plane width and height for NV12 */
>> + /* Halve UV plane width and height for NV12 and other planar yuv */
>> if (plane == 1) {
>> src_w /= 2;
>> src_h /= 2;
>> @@ -4526,8 +4526,8 @@ skl_compute_plane_wm_params(const struct
>> drm_i915_private *dev_priv,
>> return 0;
>> /* only NV12 format has two planes */
>> - if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
>> - DRM_DEBUG_KMS("Non NV12 format have single plane\n");
>> + if (plane_id == 1 && !is_planar_yuv_format(fb->format->format)) {
>> + DRM_DEBUG_KMS("Non planar format have single plane\n");
>> return -EINVAL;
>> }
>> @@ -4538,7 +4538,7 @@ skl_compute_plane_wm_params(const struct
>> drm_i915_private *dev_priv,
>> wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
>> wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>> fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
>> - wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
>> + wp->is_planar = is_planar_yuv_format(fb->format->format);
>> if (plane->id == PLANE_CURSOR) {
>> wp->width = intel_pstate->base.crtc_w;
>> @@ -4813,8 +4813,7 @@ skl_compute_wm_levels(const struct
>> drm_i915_private *dev_priv,
>> return ret;
>> }
>> - if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
>> - wm->is_planar = true;
>> + wm->is_planar =
>> is_planar_yuv_format(intel_pstate->base.fb->format->format);
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
>> b/drivers/gpu/drm/i915/intel_sprite.c
>> index f7026e8..68db026 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -41,6 +41,19 @@
>> #include <drm/i915_drm.h>
>> #include "i915_drv.h"
>> +bool is_planar_yuv_format(uint32_t pixelformat)
>> +{
>> + switch (pixelformat) {
>> + case DRM_FORMAT_NV12:
>> + case DRM_FORMAT_P010:
>> + case DRM_FORMAT_P012:
>> + case DRM_FORMAT_P016:
>> + return true;
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> int intel_usecs_to_scanlines(const struct drm_display_mode
>> *adjusted_mode,
>> int usecs)
>> {
>> @@ -1039,7 +1052,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>> src->y2 = (src_y + src_h) << 16;
>> if (fb->format->is_yuv &&
>> - fb->format->format != DRM_FORMAT_NV12 &&
>> + !is_planar_yuv_format(fb->format->format) &&
>> (src_x % 2 || src_w % 2)) {
>> DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2
>> for YUV planes\n",
>> src_x, src_w);
>> @@ -1419,6 +1432,9 @@ static bool
>> skl_plane_format_mod_supported(struct drm_plane *_plane,
>> case DRM_FORMAT_UYVY:
>> case DRM_FORMAT_VYUY:
>> case DRM_FORMAT_NV12:
>> + case DRM_FORMAT_P010:
>> + case DRM_FORMAT_P012:
>> + case DRM_FORMAT_P016:
>> if (modifier == I915_FORMAT_MOD_Yf_TILED)
>> return true;
>> /* fall through */
>
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
2018-08-16 12:55 ` [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats Juha-Pekka Heikkila
2018-08-21 14:26 ` [Intel-gfx] " Sharma, Swati2
@ 2018-08-27 11:28 ` Maarten Lankhorst
2018-08-27 13:09 ` Juha-Pekka Heikkila
1 sibling, 1 reply; 15+ messages in thread
From: Maarten Lankhorst @ 2018-08-27 11:28 UTC (permalink / raw)
To: Juha-Pekka Heikkila, intel-gfx; +Cc: dri-devel
Op 16-08-18 om 14:55 schreef Juha-Pekka Heikkila:
> Preparations for enabling P010, P012 and P016 formats. These
> formats will extend NV12 for larger bit depths.
>
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_atomic.c | 3 +-
> drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 19 ++++++-------
> drivers/gpu/drm/i915/intel_sprite.c | 18 +++++++++++-
> 6 files changed, 69 insertions(+), 20 deletions(-)
For patches 2, 3, 4:
Acked-by: Jani Nikula <jani.nikula@intel.com> #irc, for merging through drm-misc-next.
Are you ok with Swati Sharma's comment on patch 4? I can fix it up when committing.
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index b04952b..ab76b72 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> /* set scaler mode */
> if ((INTEL_GEN(dev_priv) >= 9) &&
> plane_state && plane_state->base.fb &&
> - plane_state->base.fb->format->format ==
> - DRM_FORMAT_NV12) {
> + is_planar_yuv_format(plane_state->base.fb->format->format)) {
> if (INTEL_GEN(dev_priv) == 9 &&
> !IS_GEMINILAKE(dev_priv) &&
> !IS_SKYLAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index dcba645..58b2fc6 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> else
> crtc_state->active_planes &= ~BIT(intel_plane->id);
>
> - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
> + if (state->visible && is_planar_yuv_format(state->fb->format->format))
> crtc_state->nv12_planes |= BIT(intel_plane->id);
> else
> crtc_state->nv12_planes &= ~BIT(intel_plane->id);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 690e1e8..80ce742 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> return DRM_FORMAT_RGB565;
> case PLANE_CTL_FORMAT_NV12:
> return DRM_FORMAT_NV12;
> + case PLANE_CTL_FORMAT_P010:
> + return DRM_FORMAT_P010;
> + case PLANE_CTL_FORMAT_P012:
> + return DRM_FORMAT_P012;
> + case PLANE_CTL_FORMAT_P016:
> + return DRM_FORMAT_P016;
> default:
> case PLANE_CTL_FORMAT_XRGB_8888:
> if (rgb_order) {
> @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
> * Handle the AUX surface first since
> * the main surface setup depends on it.
> */
> - if (fb->format->format == DRM_FORMAT_NV12) {
> + if (is_planar_yuv_format(fb->format->format)) {
> ret = skl_check_nv12_surface(crtc_state, plane_state);
> if (ret)
> return ret;
> @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> case DRM_FORMAT_NV12:
> return PLANE_CTL_FORMAT_NV12;
> + case DRM_FORMAT_P010:
> + return PLANE_CTL_FORMAT_P010;
> + case DRM_FORMAT_P012:
> + return PLANE_CTL_FORMAT_P012;
> + case DRM_FORMAT_P016:
> + return PLANE_CTL_FORMAT_P016;
> default:
> MISSING_CASE(pixel_format);
> }
> @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> need_scaling = src_w != dst_w || src_h != dst_h;
>
> if (plane_scaler_check)
> - if (pixel_format == DRM_FORMAT_NV12)
> - need_scaling = true;
> + need_scaling = is_planar_yuv_format(pixel_format);
>
> if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
> need_scaling = true;
> @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> return 0;
> }
>
> - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
> + if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
> (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
> DRM_DEBUG_KMS("NV12: src dimensions not met\n");
> return -EINVAL;
> @@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> break;
> default:
> DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> @@ -13179,7 +13193,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
> * or
> * cdclk/crtc_clock
> */
> - mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
> + mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
> tmpclk1 = (1 << 16) * mult - 1;
> tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
> max_scale = min(tmpclk1, tmpclk2);
> @@ -13411,6 +13425,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> if (modifier == I915_FORMAT_MOD_Yf_TILED)
> return true;
> /* fall through */
> @@ -14556,6 +14573,23 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> goto err;
> }
> break;
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> + if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
> + mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
> + DRM_DEBUG_KMS("RC not to be enabled with %s\n",
> + drm_get_format_name(mode_cmd->pixel_format,
> + &format_name));
> + goto err;
> + }
> + if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
> + DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> + drm_get_format_name(mode_cmd->pixel_format,
> + &format_name));
> + goto err;
> + }
> + break;
> default:
> DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> drm_get_format_name(mode_cmd->pixel_format, &format_name));
> @@ -14568,7 +14602,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>
> drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
>
> - if (fb->format->format == DRM_FORMAT_NV12 &&
> + if (is_planar_yuv_format(fb->format->format) &&
> (fb->width < SKL_MIN_YUV_420_SRC_W ||
> fb->height < SKL_MIN_YUV_420_SRC_H ||
> (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 7b984ae..20af577 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2097,6 +2097,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
>
>
> /* intel_sprite.c */
> +bool is_planar_yuv_format(uint32_t pixelformat);
> int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> int usecs);
> struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d99e5fa..e1292b2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3942,7 +3942,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
> if (INTEL_GEN(dev_priv) < 11)
> val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
>
> - if (fourcc == DRM_FORMAT_NV12) {
> + if (is_planar_yuv_format(fourcc)) {
> skl_ddb_entry_init_from_hw(dev_priv,
> &ddb->plane[pipe][plane_id], val2);
> skl_ddb_entry_init_from_hw(dev_priv,
> @@ -4150,7 +4150,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>
> if (intel_plane->id == PLANE_CURSOR)
> return 0;
> - if (plane == 1 && format != DRM_FORMAT_NV12)
> + if (plane == 1 && !is_planar_yuv_format(format))
> return 0;
>
> /*
> @@ -4162,7 +4162,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
> height = drm_rect_height(&intel_pstate->base.src) >> 16;
>
> /* UV plane does 1/2 pixel sub-sampling */
> - if (plane == 1 && format == DRM_FORMAT_NV12) {
> + if (plane == 1 && is_planar_yuv_format(format)) {
> width /= 2;
> height /= 2;
> }
> @@ -4229,7 +4229,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
> return 0;
>
> /* For packed formats, and uv-plane, return 0 */
> - if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
> + if (plane == 1 && !is_planar_yuv_format(fb->format->format))
> return 0;
>
> /* For Non Y-tile return 8-blocks */
> @@ -4247,7 +4247,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
> src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
> src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
>
> - /* Halve UV plane width and height for NV12 */
> + /* Halve UV plane width and height for NV12 and other planar yuv */
> if (plane == 1) {
> src_w /= 2;
> src_h /= 2;
> @@ -4526,8 +4526,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> return 0;
>
> /* only NV12 format has two planes */
> - if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
> - DRM_DEBUG_KMS("Non NV12 format have single plane\n");
> + if (plane_id == 1 && !is_planar_yuv_format(fb->format->format)) {
> + DRM_DEBUG_KMS("Non planar format have single plane\n");
> return -EINVAL;
> }
>
> @@ -4538,7 +4538,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
> wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> - wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
> + wp->is_planar = is_planar_yuv_format(fb->format->format);
>
> if (plane->id == PLANE_CURSOR) {
> wp->width = intel_pstate->base.crtc_w;
> @@ -4813,8 +4813,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
> return ret;
> }
>
> - if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
> - wm->is_planar = true;
> + wm->is_planar = is_planar_yuv_format(intel_pstate->base.fb->format->format);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index f7026e8..68db026 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -41,6 +41,19 @@
> #include <drm/i915_drm.h>
> #include "i915_drv.h"
>
> +bool is_planar_yuv_format(uint32_t pixelformat)
> +{
> + switch (pixelformat) {
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> int usecs)
> {
> @@ -1039,7 +1052,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
> src->y2 = (src_y + src_h) << 16;
>
> if (fb->format->is_yuv &&
> - fb->format->format != DRM_FORMAT_NV12 &&
> + !is_planar_yuv_format(fb->format->format) &&
> (src_x % 2 || src_w % 2)) {
> DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
> src_x, src_w);
> @@ -1419,6 +1432,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> if (modifier == I915_FORMAT_MOD_Yf_TILED)
> return true;
> /* fall through */
_______________________________________________
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
2018-08-27 11:28 ` Maarten Lankhorst
@ 2018-08-27 13:09 ` Juha-Pekka Heikkila
0 siblings, 0 replies; 15+ messages in thread
From: Juha-Pekka Heikkila @ 2018-08-27 13:09 UTC (permalink / raw)
To: Maarten Lankhorst, intel-gfx; +Cc: dri-devel
On 27.08.2018 14:28, Maarten Lankhorst wrote:
> Op 16-08-18 om 14:55 schreef Juha-Pekka Heikkila:
>> Preparations for enabling P010, P012 and P016 formats. These
>> formats will extend NV12 for larger bit depths.
>>
>> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
>> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_atomic.c | 3 +-
>> drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
>> drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++++++++++----
>> drivers/gpu/drm/i915/intel_drv.h | 1 +
>> drivers/gpu/drm/i915/intel_pm.c | 19 ++++++-------
>> drivers/gpu/drm/i915/intel_sprite.c | 18 +++++++++++-
>> 6 files changed, 69 insertions(+), 20 deletions(-)
> For patches 2, 3, 4:
>
> Acked-by: Jani Nikula <jani.nikula@intel.com> #irc, for merging through drm-misc-next.
>
> Are you ok with Swati Sharma's comment on patch 4? I can fix it up when committing.
I'm all ok with Swati Sharma's comment.
/Juha-Pekka
>> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
>> index b04952b..ab76b72 100644
>> --- a/drivers/gpu/drm/i915/intel_atomic.c
>> +++ b/drivers/gpu/drm/i915/intel_atomic.c
>> @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>> /* set scaler mode */
>> if ((INTEL_GEN(dev_priv) >= 9) &&
>> plane_state && plane_state->base.fb &&
>> - plane_state->base.fb->format->format ==
>> - DRM_FORMAT_NV12) {
>> + is_planar_yuv_format(plane_state->base.fb->format->format)) {
>> if (INTEL_GEN(dev_priv) == 9 &&
>> !IS_GEMINILAKE(dev_priv) &&
>> !IS_SKYLAKE(dev_priv))
>> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
>> index dcba645..58b2fc6 100644
>> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
>> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
>> @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>> else
>> crtc_state->active_planes &= ~BIT(intel_plane->id);
>>
>> - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
>> + if (state->visible && is_planar_yuv_format(state->fb->format->format))
>> crtc_state->nv12_planes |= BIT(intel_plane->id);
>> else
>> crtc_state->nv12_planes &= ~BIT(intel_plane->id);
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 690e1e8..80ce742 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>> return DRM_FORMAT_RGB565;
>> case PLANE_CTL_FORMAT_NV12:
>> return DRM_FORMAT_NV12;
>> + case PLANE_CTL_FORMAT_P010:
>> + return DRM_FORMAT_P010;
>> + case PLANE_CTL_FORMAT_P012:
>> + return DRM_FORMAT_P012;
>> + case PLANE_CTL_FORMAT_P016:
>> + return DRM_FORMAT_P016;
>> default:
>> case PLANE_CTL_FORMAT_XRGB_8888:
>> if (rgb_order) {
>> @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
>> * Handle the AUX surface first since
>> * the main surface setup depends on it.
>> */
>> - if (fb->format->format == DRM_FORMAT_NV12) {
>> + if (is_planar_yuv_format(fb->format->format)) {
>> ret = skl_check_nv12_surface(crtc_state, plane_state);
>> if (ret)
>> return ret;
>> @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
>> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
>> case DRM_FORMAT_NV12:
>> return PLANE_CTL_FORMAT_NV12;
>> + case DRM_FORMAT_P010:
>> + return PLANE_CTL_FORMAT_P010;
>> + case DRM_FORMAT_P012:
>> + return PLANE_CTL_FORMAT_P012;
>> + case DRM_FORMAT_P016:
>> + return PLANE_CTL_FORMAT_P016;
>> default:
>> MISSING_CASE(pixel_format);
>> }
>> @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>> need_scaling = src_w != dst_w || src_h != dst_h;
>>
>> if (plane_scaler_check)
>> - if (pixel_format == DRM_FORMAT_NV12)
>> - need_scaling = true;
>> + need_scaling = is_planar_yuv_format(pixel_format);
>>
>> if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
>> need_scaling = true;
>> @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>> return 0;
>> }
>>
>> - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
>> + if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
>> (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
>> DRM_DEBUG_KMS("NV12: src dimensions not met\n");
>> return -EINVAL;
>> @@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>> case DRM_FORMAT_UYVY:
>> case DRM_FORMAT_VYUY:
>> case DRM_FORMAT_NV12:
>> + case DRM_FORMAT_P010:
>> + case DRM_FORMAT_P012:
>> + case DRM_FORMAT_P016:
>> break;
>> default:
>> DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
>> @@ -13179,7 +13193,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
>> * or
>> * cdclk/crtc_clock
>> */
>> - mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
>> + mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
>> tmpclk1 = (1 << 16) * mult - 1;
>> tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
>> max_scale = min(tmpclk1, tmpclk2);
>> @@ -13411,6 +13425,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>> case DRM_FORMAT_UYVY:
>> case DRM_FORMAT_VYUY:
>> case DRM_FORMAT_NV12:
>> + case DRM_FORMAT_P010:
>> + case DRM_FORMAT_P012:
>> + case DRM_FORMAT_P016:
>> if (modifier == I915_FORMAT_MOD_Yf_TILED)
>> return true;
>> /* fall through */
>> @@ -14556,6 +14573,23 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>> goto err;
>> }
>> break;
>> + case DRM_FORMAT_P010:
>> + case DRM_FORMAT_P012:
>> + case DRM_FORMAT_P016:
>> + if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
>> + mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
>> + DRM_DEBUG_KMS("RC not to be enabled with %s\n",
>> + drm_get_format_name(mode_cmd->pixel_format,
>> + &format_name));
>> + goto err;
>> + }
>> + if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
>> + DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>> + drm_get_format_name(mode_cmd->pixel_format,
>> + &format_name));
>> + goto err;
>> + }
>> + break;
>> default:
>> DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>> drm_get_format_name(mode_cmd->pixel_format, &format_name));
>> @@ -14568,7 +14602,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>>
>> drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
>>
>> - if (fb->format->format == DRM_FORMAT_NV12 &&
>> + if (is_planar_yuv_format(fb->format->format) &&
>> (fb->width < SKL_MIN_YUV_420_SRC_W ||
>> fb->height < SKL_MIN_YUV_420_SRC_H ||
>> (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 7b984ae..20af577 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -2097,6 +2097,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
>>
>>
>> /* intel_sprite.c */
>> +bool is_planar_yuv_format(uint32_t pixelformat);
>> int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>> int usecs);
>> struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index d99e5fa..e1292b2 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -3942,7 +3942,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
>> if (INTEL_GEN(dev_priv) < 11)
>> val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
>>
>> - if (fourcc == DRM_FORMAT_NV12) {
>> + if (is_planar_yuv_format(fourcc)) {
>> skl_ddb_entry_init_from_hw(dev_priv,
>> &ddb->plane[pipe][plane_id], val2);
>> skl_ddb_entry_init_from_hw(dev_priv,
>> @@ -4150,7 +4150,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>>
>> if (intel_plane->id == PLANE_CURSOR)
>> return 0;
>> - if (plane == 1 && format != DRM_FORMAT_NV12)
>> + if (plane == 1 && !is_planar_yuv_format(format))
>> return 0;
>>
>> /*
>> @@ -4162,7 +4162,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>> height = drm_rect_height(&intel_pstate->base.src) >> 16;
>>
>> /* UV plane does 1/2 pixel sub-sampling */
>> - if (plane == 1 && format == DRM_FORMAT_NV12) {
>> + if (plane == 1 && is_planar_yuv_format(format)) {
>> width /= 2;
>> height /= 2;
>> }
>> @@ -4229,7 +4229,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
>> return 0;
>>
>> /* For packed formats, and uv-plane, return 0 */
>> - if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
>> + if (plane == 1 && !is_planar_yuv_format(fb->format->format))
>> return 0;
>>
>> /* For Non Y-tile return 8-blocks */
>> @@ -4247,7 +4247,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
>> src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
>> src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
>>
>> - /* Halve UV plane width and height for NV12 */
>> + /* Halve UV plane width and height for NV12 and other planar yuv */
>> if (plane == 1) {
>> src_w /= 2;
>> src_h /= 2;
>> @@ -4526,8 +4526,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
>> return 0;
>>
>> /* only NV12 format has two planes */
>> - if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
>> - DRM_DEBUG_KMS("Non NV12 format have single plane\n");
>> + if (plane_id == 1 && !is_planar_yuv_format(fb->format->format)) {
>> + DRM_DEBUG_KMS("Non planar format have single plane\n");
>> return -EINVAL;
>> }
>>
>> @@ -4538,7 +4538,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
>> wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
>> wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>> fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
>> - wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
>> + wp->is_planar = is_planar_yuv_format(fb->format->format);
>>
>> if (plane->id == PLANE_CURSOR) {
>> wp->width = intel_pstate->base.crtc_w;
>> @@ -4813,8 +4813,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
>> return ret;
>> }
>>
>> - if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
>> - wm->is_planar = true;
>> + wm->is_planar = is_planar_yuv_format(intel_pstate->base.fb->format->format);
>>
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
>> index f7026e8..68db026 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -41,6 +41,19 @@
>> #include <drm/i915_drm.h>
>> #include "i915_drv.h"
>>
>> +bool is_planar_yuv_format(uint32_t pixelformat)
>> +{
>> + switch (pixelformat) {
>> + case DRM_FORMAT_NV12:
>> + case DRM_FORMAT_P010:
>> + case DRM_FORMAT_P012:
>> + case DRM_FORMAT_P016:
>> + return true;
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>> int usecs)
>> {
>> @@ -1039,7 +1052,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>> src->y2 = (src_y + src_h) << 16;
>>
>> if (fb->format->is_yuv &&
>> - fb->format->format != DRM_FORMAT_NV12 &&
>> + !is_planar_yuv_format(fb->format->format) &&
>> (src_x % 2 || src_w % 2)) {
>> DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
>> src_x, src_w);
>> @@ -1419,6 +1432,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>> case DRM_FORMAT_UYVY:
>> case DRM_FORMAT_VYUY:
>> case DRM_FORMAT_NV12:
>> + case DRM_FORMAT_P010:
>> + case DRM_FORMAT_P012:
>> + case DRM_FORMAT_P016:
>> if (modifier == I915_FORMAT_MOD_Yf_TILED)
>> return true;
>> /* fall through */
>
>
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^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc
2018-08-30 12:41 [PATCH 1/4] " Juha-Pekka Heikkila
@ 2018-08-30 17:48 ` Patchwork
0 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-08-30 17:48 UTC (permalink / raw)
To: Juha-Pekka Heikkila; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc
URL : https://patchwork.freedesktop.org/series/48947/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739_full -> Patchwork_10049_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10049_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665)
igt@perf@blocking:
shard-hsw: PASS -> FAIL (fdo#102252) +1
==== Possible fixes ====
igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
shard-hsw: FAIL (fdo#105767) -> PASS
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt:
shard-glk: FAIL (fdo#103167) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-c:
shard-hsw: DMESG-WARN (fdo#102614) -> PASS +1
igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
shard-apl: FAIL (fdo#103375) -> PASS
igt@kms_setmode@basic:
shard-apl: FAIL (fdo#99912) -> PASS
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4739 -> Patchwork_10049
CI_DRM_4739: f65e436af74d73b095b211d5294f5d7cd5132882 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10049: bcd3b9a19948bd0667c4d37e6a31b995f1cad0a1 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10049/shards.html
_______________________________________________
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^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-08-30 17:48 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-08-16 12:55 [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc Juha-Pekka Heikkila
2018-08-16 12:55 ` [PATCH 2/4] drm/i915: Add P010, P012, P016 plane control definitions Juha-Pekka Heikkila
2018-08-16 12:55 ` [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats Juha-Pekka Heikkila
2018-08-21 14:26 ` [Intel-gfx] " Sharma, Swati2
2018-08-27 10:21 ` Juha-Pekka Heikkila
2018-08-27 11:28 ` Maarten Lankhorst
2018-08-27 13:09 ` Juha-Pekka Heikkila
2018-08-16 12:55 ` [PATCH 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes Juha-Pekka Heikkila
2018-08-16 15:51 ` Maarten Lankhorst
2018-08-24 9:23 ` Sharma, Swati2
2018-08-16 13:50 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc Patchwork
2018-08-16 13:53 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-08-16 14:07 ` ✓ Fi.CI.BAT: success " Patchwork
2018-08-16 17:17 ` ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2018-08-30 12:41 [PATCH 1/4] " Juha-Pekka Heikkila
2018-08-30 17:48 ` ✓ Fi.CI.IGT: success for series starting with [1/4] " Patchwork
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